Home
last modified time | relevance | path

Searched +refs:tablegen +refs:mode +refs:map (Results 1 – 25 of 33) sorted by relevance

12

/external/llvm-project/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
33 // A special mode recognized by tablegen. This mode is considered active
34 // when no other mode is active. For targets that do not use specific hw
35 // modes, this is the only mode.
48 // dependent on a HW mode. This class inherits from ValueType itself,
66 // The register size/alignment information, parameterized by a HW mode.
163 // is invalid for this mode/flavour.
215 // The register size/alignment information, parameterized by a HW mode.
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
33 // A special mode recognized by tablegen. This mode is considered active
34 // when no other mode is active. For targets that do not use specific hw
35 // modes, this is the only mode.
48 // dependent on a HW mode. This class inherits from ValueType itself,
66 // The register size/alignment information, parameterized by a HW mode.
163 // is invalid for this mode/flavour.
214 // The register size/alignment information, parameterized by a HW mode.
[all …]
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
238 // Floating point stack registers. These don't map one-to-one to the FP
319 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
324 // 64-bit mode. The main complication is that they cannot be encoded in an
399 // mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
124 // Class specifying the opcode map.
145 // Operand size for encodings that change based on mode.
150 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
151 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
153 // Address size for encodings that change based on mode.
249 // based on operand size of the mode?
252 // based on address size of the mode?
257 Map OpMap = OB; // Which opcode map does this inst have?
918 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
41 // "pseudo" or "target". This is used to map a pseduo memory instruction to
181 // bits<4> Mn : mode value for operand n
2409 AddressingMode mode = bdaddr12only>
2410 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2416 AddressingMode mode = bdaddr20only>
2417 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2465 AddressingMode mode = bdxaddr12only>
2466 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2468 [(operator cls:$R1, mode:$XBD2)]> {
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
151 // Class specifying the opcode map.
173 // Operand size for encodings that change based on mode.
178 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
179 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
181 // Address size for encodings that change based on mode.
295 // based on operand size of the mode?
298 // based on address size of the mode?
303 Map OpMap = OB; // Which opcode map does this inst have?
981 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
[all …]
DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
288 // Floating point stack registers. These don't map one-to-one to the FP
390 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
395 // 64-bit mode. The main complication is that they cannot be encoded in an
523 // register in 32-bit mode. The second register is always the next in
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
144 // Class specifying the opcode map.
166 // Operand size for encodings that change based on mode.
171 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
172 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
174 // Address size for encodings that change based on mode.
284 // based on operand size of the mode?
287 // based on address size of the mode?
292 Map OpMap = OB; // Which opcode map does this inst have?
968 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
[all …]
DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
278 // Floating point stack registers. These don't map one-to-one to the FP
380 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
385 // 64-bit mode. The main complication is that they cannot be encoded in an
513 // register in 32-bit mode. The second register is always the next in
DX86InstrAVX512.td1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
130 // We map scalar types to the smallest (128-bit) vector type
461 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
6586 // 213 and 231 patterns this helps tablegen's duplicate pattern detection.
6594 // 213 and 231 patterns this helps tablegen's duplicate pattern detection.
6721 // 213 and 231 patterns this helps tablegen's duplicate pattern detection.
6888 // Patterns with rounding mode.
6976 // This enables commuted load patterns to be autogenerated by tablegen.
8534 // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
41 // "pseudo" or "target". This is used to map a pseduo memory instruction to
181 // bits<4> Mn : mode value for operand n
2463 AddressingMode mode = bdaddr12only>
2464 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2470 AddressingMode mode = bdaddr20only>
2471 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2519 AddressingMode mode = bdxaddr12only>
2520 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2522 [(operator cls:$R1, mode:$XBD2)]> {
[all …]
/external/llvm-project/mlir/include/mlir/Dialect/Vector/
DVectorOps.td1 //===- VectorOps.td - Vector op definitions ---------------*- tablegen -*-====//
87 An indexing map attribute list must be specified with an entry for lhs, rhs
88 and acc arguments. An indexing map attribute specifies a mapping from each
184 // op indexing map attribute (i.e. one for each input and output, with
185 // the output listed last). Each index map, maps from this operations
462 let summary = "vector extract map operation";
508 "AffineMap":$map)>];
517 AffineMap map();
703 let summary = "vector insert map operation";
757 // Return a map indicating the dimension mapping to the given ids.
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
308 // For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of
310 // whereas 'bitconvert' will map it to the high byte in big-endian mode,
529 // Operands that are part of a memory addressing mode.
540 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
546 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
566 // Target for BLX *from* ARM mode.
2123 /// mode). Used mostly in ARM and Thumb-1 modes.
2225 bits<5> mode;
2231 let Inst{17} = M; // Enabled if mode is set;
[all …]
DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1566 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1700 // pseudos map between the two.
1723 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1808 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2329 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3990 bits<5> mode;
3997 let Inst{4-0} = mode;
4002 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
4003 "$imod\t$iflags, $mode">;
[all …]
/external/clang/docs/
DInternalsManual.rst110 you to map almost any diagnostic to the output level that you want. The only
430 mentioned, the diagnostic machinery goes through some filtering to map a
444 mode. Instead of formatting and printing out the diagnostics, this
448 documentation for the ``-verify`` mode can be found in the Clang API
522 To map from this representation to a character-based representation, the "last"
599 not reading in "raw" mode) this contains a pointer to the unique hash value
731 * The lexer can operate in "raw" mode. This mode has several features that
734 This mode is used for lexing within an "``#if 0``" block, for example.
736 support the ``-C`` preprocessor mode, which passes comments through, and is
738 * The lexer can be in ``ParsingFilename`` mode, which happens when
[all …]
/external/llvm-project/mlir/include/mlir/Dialect/StandardOps/IR/
DOps.td1 //===- Ops.td - Standard operation definitions -------------*- tablegen -*-===//
176 // to the symbols of the memref's layout map.
316 math, contraction, rounding mode, and other controls.
380 memrefs affine map. In the example below, the ssa value '%s' is bound to
381 the symbol 's0' in the affine map specified in the allocs memref type.
429 memref's affine map. In the example below, the SSA value '%s' is bound to
430 the symbol 's0' in the affine map specified in the allocs memref type.
1606 a "parallel map" operation.
1836 rounding mode. Only scalars are currently supported.
2243 layout map. The following combinations are possible:
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
291 AssemblerPredicate<"!ModeThumb", "arm-mode">;
410 // Operands that are part of a memory addressing mode.
421 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
427 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
447 // Target for BLX *from* ARM mode.
1866 /// mode). Used mostly in ARM and Thumb-1 modes.
1965 bits<5> mode;
1971 let Inst{17} = M; // Enabled if mode is set;
1975 let Inst{4-0} = mode;
[all …]
DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1385 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1508 // pseudos map between the two.
1528 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1611 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2043 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3693 bits<5> mode;
3700 let Inst{4-0} = mode;
3705 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3706 "$imod\t$iflags, $mode">;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
416 // Operands that are part of a memory addressing mode.
427 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
433 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
453 // Target for BLX *from* ARM mode.
2008 /// mode). Used mostly in ARM and Thumb-1 modes.
2110 bits<5> mode;
2116 let Inst{17} = M; // Enabled if mode is set;
2120 let Inst{4-0} = mode;
2125 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
[all …]
DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1564 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1697 // pseudos map between the two.
1720 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1805 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2280 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3921 bits<5> mode;
3928 let Inst{4-0} = mode;
3933 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3934 "$imod\t$iflags, $mode">;
[all …]
/external/llvm-project/clang/docs/
DInternalsManual.rst110 you to map almost any diagnostic to the output level that you want. The only
459 mentioned, the diagnostic machinery goes through some filtering to map a
473 mode. Instead of formatting and printing out the diagnostics, this
477 documentation for the ``-verify`` mode can be found in the Clang API
551 To map from this representation to a character-based representation, the "last"
624 not reading in "raw" mode) this contains a pointer to the unique hash value
756 * The lexer can operate in "raw" mode. This mode has several features that
759 This mode is used for lexing within an "``#if 0``" block, for example.
761 support the ``-C`` preprocessor mode, which passes comments through, and is
763 * The lexer can be in ``ParsingFilename`` mode, which happens when
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSOPInstructions.td487 // is it possible to map such copy to a single instruction (S_CMP_LG_U64).
829 // s_getreg_b32 should use hasSideEffects = 1 for tablegen to allow
1031 // Setting the GPR index mode is really writing the fields in the mode
1032 // register. We don't want to add mode register uses to every
1041 let Uses = [M0, MODE]; // Other bits of mode, m0 unmodified.
1042 let hasSideEffects = 1; // Sets mode.gpr_idx_en
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
392 // Template class for load instructions with Absolute set addressing mode.
536 // base + register offset addressing mode
560 // base + register offset addressing mode
595 // addressing mode
684 // Template class for store instructions with Absolute set addressing mode.
853 // base + register offset addressing mode
882 // base + register offset addressing mode
920 // base + register offset addressing mode
946 // base + register offset addressing mode
[all …]
/external/tensorflow/tensorflow/compiler/mlir/lite/ir/
Dtfl_ops.td1350 This op also supports a Soft-NMS (with Gaussian weighting) mode (c.f.
1353 To enable this Soft-NMS mode, set the `soft_nms_sigma` parameter to be
1947 // per Predicate inside the trait and get tablegen to use that to emit error
2535 // non-quantization tablegen patterns. Currently, it is used by the
2563 // non-quantization tablegen patterns. Currently, it is used by the
2591 // non-quantization tablegen patterns. Currently, it is used by the
2989 // non-quantization tablegen patterns. Currently, it is used by the
3509 TFL_MirrorPaddingAttr:$mode
4419 // Used to map StatelessWhile and While op defined in TensorFlow to a common
/external/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
110 // is invalid for this mode/flavour.
301 // is invalid for this mode/flavour.
497 /// Which instruction it expands to and how the operands map from the

12