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Searched refs:uqrshrnb (Results 1 – 7 of 7) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE2/
Duqrshrnb-diagnostics.s3 uqrshrnb z30.b, z10.h, #0 label
8 uqrshrnb z18.b, z27.h, #9 label
13 uqrshrnb z26.h, z4.s, #0 label
18 uqrshrnb z25.h, z10.s, #17 label
23 uqrshrnb z17.s, z0.d, #0 label
28 uqrshrnb z0.s, z15.d, #33 label
37 uqrshrnb z0.b, z0.b, #1 label
42 uqrshrnb z0.h, z0.h, #1 label
47 uqrshrnb z0.s, z0.s, #1 label
52 uqrshrnb z0.d, z0.d, #1 label
[all …]
Duqrshrnb.s10 uqrshrnb z0.b, z0.h, #1 label
16 uqrshrnb z31.b, z31.h, #8 label
22 uqrshrnb z0.h, z0.s, #1 label
28 uqrshrnb z31.h, z31.s, #16 label
34 uqrshrnb z0.s, z0.d, #1 label
40 uqrshrnb z31.s, z31.d, #32 label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve2-intrinsics-binary-narrowing-shr.ll137 ; CHECK: uqrshrnb z0.b, z0.h, #2
139 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnb.nxv8i16(<vscale x 8 x i16> %a,
146 ; CHECK: uqrshrnb z0.h, z0.s, #2
148 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnb.nxv4i32(<vscale x 4 x i32> %a,
155 ; CHECK: uqrshrnb z0.s, z0.d, #2
157 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnb.nxv2i64(<vscale x 2 x i64> %a,
474 declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnb.nxv8i16(<vscale x 8 x i16>, i32)
475 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnb.nxv4i32(<vscale x 4 x i32>, i32)
476 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnb.nxv2i64(<vscale x 2 x i64>, i32)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1457 …defm UQRSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b111, "uqrshrnb", int_aarch64_sv…
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12609 "shlr\007uqrshrn\010uqrshrn2\010uqrshrnb\010uqrshrnt\005uqshl\006uqshlr\006"
19691 …{ 6625 /* uqrshrnb */, AArch64::UQRSHRNB_ZZI_H, Convert__SVEVectorHReg1_0__SVEVectorSReg1_1__Imm1_…
19692 …{ 6625 /* uqrshrnb */, AArch64::UQRSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_…
19693 …{ 6625 /* uqrshrnb */, AArch64::UQRSHRNB_ZZI_B, Convert__SVEVectorBReg1_0__SVEVectorHReg1_1__Imm1_…
27064 …{ 6625 /* uqrshrnb */, AArch64::UQRSHRNB_ZZI_H, Convert__SVEVectorHReg1_0__SVEVectorSReg1_1__Imm1_…
27065 …{ 6625 /* uqrshrnb */, AArch64::UQRSHRNB_ZZI_S, Convert__SVEVectorSReg1_0__SVEVectorDReg1_1__Imm1_…
27066 …{ 6625 /* uqrshrnb */, AArch64::UQRSHRNB_ZZI_B, Convert__SVEVectorBReg1_0__SVEVectorHReg1_1__Imm1_…
40089 { 6625 /* uqrshrnb */, 1 /* 0 */, MCK_SVEVectorHReg, AMFBS_HasSVE2 },
40090 { 6625 /* uqrshrnb */, 2 /* 1 */, MCK_SVEVectorSReg, AMFBS_HasSVE2 },
40091 { 6625 /* uqrshrnb */, 1 /* 0 */, MCK_SVEVectorHReg, AMFBS_HasSVE2 },
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td2636 …defm UQRSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b111, "uqrshrnb", int_aarch64_sv…
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc829 "llvm.aarch64.sve.uqrshrnb",
10962 48, // llvm.aarch64.sve.uqrshrnb