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/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrPrefix.td14 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,
21 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisInt<2>
27 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1>
1273 [(set v512i1:$ASo, (int_ppc_mma_xxmfacc v512i1:$AS))]>,
1278 [(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>,
1291 [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>;
1363 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),
1365 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1368 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)),
1370 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
[all …]
DPPCRegisterInfo.td427 def ACCRC : RegisterClass<"PPC", [v512i1], 128, (add ACC0, ACC1, ACC2, ACC3,
442 def UACCRC : RegisterClass<"PPC", [v512i1], 128,
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrIntrinsicVL.gen.td166 def : Pat<(int_ve_vl_lvm_MMss v512i1:$ptm, uimm6:$N, i64:$sz), (LVMyir_y (ULO7 $N), i64:$sz, v512i1…
168 def : Pat<(int_ve_vl_svm_sMs v512i1:$vmz, uimm6:$N), (SVMyi v512i1:$vmz, (ULO7 $N))>;
189 def : Pat<(int_ve_vl_pvbrd_vsMvl i64:$sy, v512i1:$vm, v256f64:$pt, i32:$vl), (PVBRDrml_v i64:$sy, v…
215 …du_vvvMvl v256f64:$vy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVADDUvvml_v v256f64:$vy, …
216 …l_pvaddu_vsvMvl i64:$sy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVADDUrvml_v i64:$sy, v2…
239 …ds_vvvMvl v256f64:$vy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVADDSvvml_v v256f64:$vy, …
240 …l_pvadds_vsvMvl i64:$sy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVADDSrvml_v i64:$sy, v2…
272 …bu_vvvMvl v256f64:$vy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVSUBUvvml_v v256f64:$vy, …
273 …l_pvsubu_vsvMvl i64:$sy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVSUBUrvml_v i64:$sy, v2…
296 …bs_vvvMvl v256f64:$vy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVSUBSvvml_v v256f64:$vy, …
[all …]
DVECallingConv.td117 CCIfType<[v512i1],
138 CCIfType<[v512i1],
DVERegisterInfo.td194 def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>;
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsVEVL.gen.td88 … : GCCBuiltin<"__builtin_ve_vl_lvm_MMss">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v512i1>, LLVMTy…
90 …Builtin<"__builtin_ve_vl_svm_sMs">, Intrinsic<[LLVMType<i64>], [LLVMType<v512i1>, LLVMType<i64>], …
105 …l_pvbrd_vsMvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v512i1>, LLVMType<v256f64…
125 …sic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64…
126 …trinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64…
143 …sic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64…
144 …trinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64…
167 …sic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64…
168 …trinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64…
185 …sic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td280 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
281 (v512i1 (V6_vandvrt (v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
284 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
285 (v512i1 (V6_vandvrt (v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
288 def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))),
289 (v512i1 (V6_vandvrt (v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
292 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
293 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
296 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
297 (v32i16 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
[all …]
DHexagonIntrinsicsV60.td28 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
31 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
32 (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
34 def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))),
35 (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
37 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
38 (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
40 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
41 (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonRegisterInfo.td286 [v512i1, v1024i1, v512i1]>;
DHexagonISelDAGToDAGHVX.cpp2206 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1); in SelectHVXDualOutput()
2220 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1); in SelectHVXDualOutput()
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td84 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
85 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
89 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
90 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
94 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
95 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1),
99 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
100 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1),
104 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
105 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
[all …]
DHexagonISelLowering.cpp198 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) { in CC_Hexagon_VarArg()
338 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) { in CC_HexagonVector()
414 LocVT == MVT::v512i1) { in RetCC_Hexagon()
549 ty == MVT::v512i1 || ty == MVT::v1024i1); in IsHvxVectorType()
1146 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { in LowerFormalArguments()
1763 addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass); in HexagonTargetLowering()
2872 case MVT::v512i1: in getRegForInlineAsmConstraint()
DHexagonRegisterInfo.td241 def VecPredRegs : RegisterClass<"Hexagon", [v512i1], 512,
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h65 v512i1 = 19, // 512 x i1 enumerator
265 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || in is512BitVector()
323 case v512i1: in getVectorElementType()
376 case v512i1: return 512; in getVectorNumElements()
496 case v512i1: in getSizeInBits()
599 if (NumElements == 512) return MVT::v512i1; in getVectorVT()
DValueTypes.td42 def v512i1 : ValueType<512, 19>; // 512 x i1 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h69 v512i1 = 23, // 512 x i1 enumerator
368 SimpleTy == MVT::v8f64 || SimpleTy == MVT::v512i1 || in is512BitVector()
437 case v512i1: in getVectorElementType()
556 case v512i1: in getVectorNumElements()
790 case v512i1: in getSizeInBits()
932 if (NumElements == 512) return MVT::v512i1; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h70 v512i1 = 24, // 512 x i1 enumerator
401 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || in is512BitVector()
504 case v512i1: in getVectorElementType()
649 case v512i1: in getVectorNumElements()
926 case v512i1: in getSizeInBits()
1119 if (NumElements == 512) return MVT::v512i1; in getVectorVT()
/external/llvm/lib/IR/
DValueTypes.cpp151 case MVT::v512i1: return "v512i1"; in getEVTString()
229 case MVT::v512i1: return VectorType::get(Type::getInt1Ty(Context), 512); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp79 case MVT::v512i1: return "MVT::v512i1"; in getEnumName()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td44 def v512i1 : ValueType<512, 23>; // 512 x i1 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp168 case MVT::v512i1: return VectorType::get(Type::getInt1Ty(Context), 512); in getTypeForEVT()
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td46 def v512i1 : ValueType<512, 24>; // 512 x i1 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp216 case MVT::v512i1: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp90 case MVT::v512i1: return "MVT::v512i1"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td175 def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1

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