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Searched refs:v_pk_add_u16 (Results 1 – 25 of 27) sorted by relevance

12

/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop3p-err.s4 v_pk_add_u16 v1, v2, v3 op_sel label
7 v_pk_add_u16 v1, v2, v3 op_sel: label
10 v_pk_add_u16 v1, v2, v3 op_sel:[ label
13 v_pk_add_u16 v1, v2, v3 op_sel:[] label
16 v_pk_add_u16 v1, v2, v3 op_sel:[,] label
22 v_pk_add_u16 v1, v2, v3 op_sel:[0 0] label
25 v_pk_add_u16 v1, v2, v3 op_sel:[0,] label
28 v_pk_add_u16 v1, v2, v3 op_sel:[,0] label
40 v_pk_add_u16 v1, v2, v3 op_sel:[0,2] label
43 v_pk_add_u16 v1, v2, v3 op_sel:[2,0] label
[all …]
Dvop3p.s6 v_pk_add_u16 v1, v2, v3 label
9 v_pk_add_u16 v1, v2, v3 op_sel:[0,0] label
12 v_pk_add_u16 v1, v2, v3 op_sel_hi:[1,1] label
15 v_pk_add_u16 v1, v2, v3 op_sel:[0,0] op_sel_hi:[1,1] label
18 v_pk_add_u16 v1, v2, v3 op_sel_hi:[0,0] label
21 v_pk_add_u16 v1, v2, v3 op_sel:[0,0] op_sel_hi:[0,0] label
24 v_pk_add_u16 v1, v2, v3 op_sel:[1,0] label
27 v_pk_add_u16 v1, v2, v3 op_sel:[0,1] label
30 v_pk_add_u16 v1, v2, v3 op_sel:[1,1] label
33 v_pk_add_u16 v1, v2, v3 op_sel_hi:[0,1] label
[all …]
Dliteralv216.s179 v_pk_add_u16 v5, v1, 0x12345678 label
183 v_pk_add_u16 v5, 0x12345678, v2 label
187 v_pk_add_u16 v5, -256, v2 label
191 v_pk_add_u16 v5, v1, 256 label
199 v_pk_add_u16 v5, v1, 0x123456780 label
243 v_pk_add_u16 v5, v1, 0.1234 label
275 v_pk_add_u16 v5, v1, 123456.0 label
Dvop3-literal.s90 v_pk_add_u16 v1, -200, v2 label
94 v_pk_add_u16 v1, 64, v2 label
98 v_pk_add_u16 v1, 65, v2 label
102 v_pk_add_u16 v1, -1, v2 label
106 v_pk_add_u16 v1, -5, v2 label
110 v_pk_add_u16 v1, -100, v2 label
114 v_pk_add_u16 v1, -100, -100 label
Dgfx10_err_pos.s190 v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0] label
226 v_pk_add_u16 v1, v2, v3 op_sel:[0 0] label
294 v_pk_add_u16 v1, v2, v3 op_sel: label
639 v_pk_add_u16 v1, v2, v3 op_sel:[-1,0] label
1049 v_pk_add_u16 v1, v2, v3 op_sel:[ label
1054 v_pk_add_u16 v1, v2, v3 op_sel:[,0] label
1059 v_pk_add_u16 v1, v2, v3 op_sel:[,] label
1064 v_pk_add_u16 v1, v2, v3 op_sel:[0,] label
1069 v_pk_add_u16 v1, v2, v3 op_sel:[] label
Dexpressions-gfx9.s44 v_pk_add_u16 v1, v2, v3 op_sel:[2-i1,i1-1] label
47 v_pk_add_u16 v1, v2, v3 neg_lo:[2-i1,i1-1] label
Dgfx8_unsupported.s1507 v_pk_add_u16 v0, v1, v2 label
Dgfx7_unsupported.s2173 v_pk_add_u16 v0, v1, v2 label
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dvop3-literal.txt33 # GFX10: v_pk_add_u16 v1, 0xffffff38, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x38,…
36 # GFX10: v_pk_add_u16 v1, 64, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xc0,0x04,0x02,0x18]
39 # GFX10: v_pk_add_u16 v1, 0x41, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x41,…
42 # GFX10: v_pk_add_u16 v1, -1, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xc1,0x04,0x02,0x18]
45 # GFX10: v_pk_add_u16 v1, -5, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xc5,0x04,0x02,0x18]
48 # GFX10: v_pk_add_u16 v1, 0xffffff9c, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x9c,…
Dliteralv216_gfx10.txt107 # GFX10: v_pk_add_u16 v5, v1, 0x12345678 ; encoding: [0x05,0x00,0x0a,0xcc,0x01,0xff,0x01,0x18,0x78,…
110 # GFX10: v_pk_add_u16 v5, 0x12345678, v2 ; encoding: [0x05,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x78,…
113 # GFX10: v_pk_add_u16 v5, 0xffffff00, v2 ; encoding: [0x05,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x00,…
116 # GFX10: v_pk_add_u16 v5, v1, 0x100 ; encoding: [0x05,0x00,0x0a,0xcc,0x01,0xff,0x01,0x18,0x00,0x01,…
Dgfx9_dasm_all.txt50616 # CHECK: v_pk_add_u16 v5, v1, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x…
50619 # CHECK: v_pk_add_u16 v255, v1, v2 ; encoding: [0xff,0x00,0x8a,0xd3,0x01,0x05,0x02,0x…
50622 # CHECK: v_pk_add_u16 v5, v255, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0xff,0x05,0x02,0x…
50625 # CHECK: v_pk_add_u16 v5, s1, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0x01,0x04,0x02,0x…
50628 # CHECK: v_pk_add_u16 v5, s101, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0x65,0x04,0x02,0x…
50631 # CHECK: v_pk_add_u16 v5, flat_scratch_lo, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0x66,0x04,0x02,0x…
50634 # CHECK: v_pk_add_u16 v5, flat_scratch_hi, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0x67,0x04,0x02,0x…
50637 # CHECK: v_pk_add_u16 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0x6a,0x04,0x02,0x…
50640 # CHECK: v_pk_add_u16 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0x6b,0x04,0x02,0x…
50643 # CHECK: v_pk_add_u16 v5, m0, v2 ; encoding: [0x05,0x00,0x8a,0xd3,0x7c,0x04,0x02,0x…
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dadd.v2i16.ll6 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
28 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]]
42 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL]], [[VAL]]
55 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
71 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]]
90 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]]
124 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}}
145 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]{{$}}
167 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]]
200 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]]
[all …]
Dinlineasm-packed.ll40 ; GCN: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
43 %val = call <2 x i16> asm "v_pk_add_u16 $0, $1, $2", "=v,r,v"(<2 x i16> %in0, <2 x i16> %in1) #0
Dreduce-build-vec-ext-to-ext-build-vec.ll11 ; GFX9-NEXT: v_pk_add_u16 v1, v0, v1
Dsext-in-reg.ll653 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]]
665 ; GFX9: v_pk_add_u16
666 ; GFX9: v_pk_add_u16
680 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]]
692 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]]
704 ; GFX9: v_pk_add_u16
705 ; GFX9: v_pk_add_u16
Duaddsat.ll117 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
158 ; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
159 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
206 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
207 ; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
Dbuild-vector-packed-partial-undef.ll84 ; GFX9-NEXT: v_pk_add_u16 v0, v0, s4 op_sel_hi:[1,0]
275 ; GFX9-NEXT: v_pk_add_u16 v0, v0, s4 op_sel_hi:[1,0]
Dreduction.ll82 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}}
125 ; GFX9: v_pk_add_u16 [[ADD1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}}
126 ; GFX9-NEXT: v_pk_add_u16 [[ADD2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}}
127 ; GFX9-NEXT: v_pk_add_u16 [[ADD3:v[0-9]+]], [[ADD2]], [[ADD1]]{{$}}
Dpacked-op-sel.ll184 ; GCN: v_pk_add_u16 v{{[0-9]+}}, [[VEC0]], [[SCALAR0]] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]{{$…
326 ; GCN: v_pk_add_u16 v{{[0-9]+}}, [[VEC0]], [[VEC1]] op_sel:[0,1]{{$}}
598 ; GCN: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+$}}
Dsdwa-peephole.ll461 ; GFX9_10: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dadd.v2i16.ll9 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
27 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]
48 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
69 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]
95 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
116 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
136 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
Duaddsat.ll235 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
255 ; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp
325 ; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
348 ; GFX10-NEXT: v_pk_add_u16 v0, s0, s1 clamp
454 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
459 ; GFX9-NEXT: v_pk_add_u16 v1, v2, v3 clamp
492 ; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp
495 ; GFX10-NEXT: v_pk_add_u16 v1, v3, v1 clamp
623 ; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
628 ; GFX9-NEXT: v_pk_add_u16 v1, s2, v1 clamp
[all …]
/external/llvm-project/llvm/docs/
DAMDGPUInstructionSyntax.rst109 v_pk_add_u16
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP3PInstructions.td55 def V_PK_ADD_U16 : VOP3PInst<"v_pk_add_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, add>;
/external/llvm-project/llvm/lib/Target/AMDGPU/
DVOP3PInstructions.td62 def V_PK_ADD_U16 : VOP3PInst<"v_pk_add_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, add>;

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