1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15
16 #include "AArch64.h"
17 #include "AArch64RegisterInfo.h"
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/Support/TypeSize.h"
22
23 #define GET_INSTRINFO_HEADER
24 #include "AArch64GenInstrInfo.inc"
25
26 namespace llvm {
27
28 class AArch64Subtarget;
29 class AArch64TargetMachine;
30
31 static const MachineMemOperand::Flags MOSuppressPair =
32 MachineMemOperand::MOTargetFlag1;
33 static const MachineMemOperand::Flags MOStridedAccess =
34 MachineMemOperand::MOTargetFlag2;
35
36 #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
37
38 class AArch64InstrInfo final : public AArch64GenInstrInfo {
39 const AArch64RegisterInfo RI;
40 const AArch64Subtarget &Subtarget;
41
42 public:
43 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
44
45 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
46 /// such, whenever a client has an instance of instruction info, it should
47 /// always be able to get register info as well (through this method).
getRegisterInfo()48 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
49
50 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
51
52 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
53
54 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
55 Register &DstReg, unsigned &SubIdx) const override;
56
57 bool
58 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
59 const MachineInstr &MIb) const override;
60
61 unsigned isLoadFromStackSlot(const MachineInstr &MI,
62 int &FrameIndex) const override;
63 unsigned isStoreToStackSlot(const MachineInstr &MI,
64 int &FrameIndex) const override;
65
66 /// Does this instruction set its full destination register to zero?
67 static bool isGPRZero(const MachineInstr &MI);
68
69 /// Does this instruction rename a GPR without modifying bits?
70 static bool isGPRCopy(const MachineInstr &MI);
71
72 /// Does this instruction rename an FPR without modifying bits?
73 static bool isFPRCopy(const MachineInstr &MI);
74
75 /// Return true if pairing the given load or store is hinted to be
76 /// unprofitable.
77 static bool isLdStPairSuppressed(const MachineInstr &MI);
78
79 /// Return true if the given load or store is a strided memory access.
80 static bool isStridedAccess(const MachineInstr &MI);
81
82 /// Return true if this is an unscaled load/store.
83 static bool isUnscaledLdSt(unsigned Opc);
isUnscaledLdSt(MachineInstr & MI)84 static bool isUnscaledLdSt(MachineInstr &MI) {
85 return isUnscaledLdSt(MI.getOpcode());
86 }
87
88 /// Returns the unscaled load/store for the scaled load/store opcode,
89 /// if there is a corresponding unscaled variant available.
90 static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
91
92 /// Scaling factor for (scaled or unscaled) load or store.
93 static int getMemScale(unsigned Opc);
getMemScale(const MachineInstr & MI)94 static int getMemScale(const MachineInstr &MI) {
95 return getMemScale(MI.getOpcode());
96 }
97
98
99 /// Returns the index for the immediate for a given instruction.
100 static unsigned getLoadStoreImmIdx(unsigned Opc);
101
102 /// Return true if pairing the given load or store may be paired with another.
103 static bool isPairableLdStInst(const MachineInstr &MI);
104
105 /// Return the opcode that set flags when possible. The caller is
106 /// responsible for ensuring the opc has a flag setting equivalent.
107 static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
108
109 /// Return true if this is a load/store that can be potentially paired/merged.
110 bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
111
112 /// Hint that pairing the given load or store is unprofitable.
113 static void suppressLdStPair(MachineInstr &MI);
114
115 Optional<ExtAddrMode>
116 getAddrModeFromMemoryOp(const MachineInstr &MemI,
117 const TargetRegisterInfo *TRI) const override;
118
119 bool getMemOperandsWithOffsetWidth(
120 const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
121 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
122 const TargetRegisterInfo *TRI) const override;
123
124 /// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
125 /// This is true for some SVE instructions like ldr/str that have a
126 /// 'reg + imm' addressing mode where the immediate is an index to the
127 /// scalable vector located at 'reg + imm * vscale x #bytes'.
128 bool getMemOperandWithOffsetWidth(const MachineInstr &MI,
129 const MachineOperand *&BaseOp,
130 int64_t &Offset, bool &OffsetIsScalable,
131 unsigned &Width,
132 const TargetRegisterInfo *TRI) const;
133
134 /// Return the immediate offset of the base register in a load/store \p LdSt.
135 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
136
137 /// Returns true if opcode \p Opc is a memory operation. If it is, set
138 /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
139 ///
140 /// For unscaled instructions, \p Scale is set to 1.
141 static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width,
142 int64_t &MinOffset, int64_t &MaxOffset);
143
144 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
145 ArrayRef<const MachineOperand *> BaseOps2,
146 unsigned NumLoads, unsigned NumBytes) const override;
147
148 void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
149 const DebugLoc &DL, MCRegister DestReg,
150 MCRegister SrcReg, bool KillSrc, unsigned Opcode,
151 llvm::ArrayRef<unsigned> Indices) const;
152 void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
153 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
154 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
155 llvm::ArrayRef<unsigned> Indices) const;
156 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
157 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
158 bool KillSrc) const override;
159
160 void storeRegToStackSlot(MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator MBBI, Register SrcReg,
162 bool isKill, int FrameIndex,
163 const TargetRegisterClass *RC,
164 const TargetRegisterInfo *TRI) const override;
165
166 void loadRegFromStackSlot(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MBBI, Register DestReg,
168 int FrameIndex, const TargetRegisterClass *RC,
169 const TargetRegisterInfo *TRI) const override;
170
171 // This tells target independent code that it is okay to pass instructions
172 // with subreg operands to foldMemoryOperandImpl.
isSubregFoldable()173 bool isSubregFoldable() const override { return true; }
174
175 using TargetInstrInfo::foldMemoryOperandImpl;
176 MachineInstr *
177 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
178 ArrayRef<unsigned> Ops,
179 MachineBasicBlock::iterator InsertPt, int FrameIndex,
180 LiveIntervals *LIS = nullptr,
181 VirtRegMap *VRM = nullptr) const override;
182
183 /// \returns true if a branch from an instruction with opcode \p BranchOpc
184 /// bytes is capable of jumping to a position \p BrOffset bytes away.
185 bool isBranchOffsetInRange(unsigned BranchOpc,
186 int64_t BrOffset) const override;
187
188 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
189
190 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
191 MachineBasicBlock *&FBB,
192 SmallVectorImpl<MachineOperand> &Cond,
193 bool AllowModify = false) const override;
194 bool analyzeBranchPredicate(MachineBasicBlock &MBB,
195 MachineBranchPredicate &MBP,
196 bool AllowModify) const override;
197 unsigned removeBranch(MachineBasicBlock &MBB,
198 int *BytesRemoved = nullptr) const override;
199 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
200 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
201 const DebugLoc &DL,
202 int *BytesAdded = nullptr) const override;
203 bool
204 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
205 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
206 Register, Register, Register, int &, int &,
207 int &) const override;
208 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
209 const DebugLoc &DL, Register DstReg,
210 ArrayRef<MachineOperand> Cond, Register TrueReg,
211 Register FalseReg) const override;
212 void getNoop(MCInst &NopInst) const override;
213
214 bool isSchedulingBoundary(const MachineInstr &MI,
215 const MachineBasicBlock *MBB,
216 const MachineFunction &MF) const override;
217
218 /// analyzeCompare - For a comparison instruction, return the source registers
219 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
220 /// Return true if the comparison instruction can be analyzed.
221 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
222 Register &SrcReg2, int &CmpMask,
223 int &CmpValue) const override;
224 /// optimizeCompareInstr - Convert the instruction supplying the argument to
225 /// the comparison into one that sets the zero bit in the flags register.
226 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
227 Register SrcReg2, int CmpMask, int CmpValue,
228 const MachineRegisterInfo *MRI) const override;
229 bool optimizeCondBranch(MachineInstr &MI) const override;
230
231 /// Return true when a code sequence can improve throughput. It
232 /// should be called only for instructions in loops.
233 /// \param Pattern - combiner pattern
234 bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
235 /// Return true when there is potentially a faster code sequence
236 /// for an instruction chain ending in ``Root``. All potential patterns are
237 /// listed in the ``Patterns`` array.
238 bool getMachineCombinerPatterns(
239 MachineInstr &Root,
240 SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
241 /// Return true when Inst is associative and commutative so that it can be
242 /// reassociated.
243 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
244 /// When getMachineCombinerPatterns() finds patterns, this function generates
245 /// the instructions that could replace the original code sequence
246 void genAlternativeCodeSequence(
247 MachineInstr &Root, MachineCombinerPattern Pattern,
248 SmallVectorImpl<MachineInstr *> &InsInstrs,
249 SmallVectorImpl<MachineInstr *> &DelInstrs,
250 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
251 /// AArch64 supports MachineCombiner.
252 bool useMachineCombiner() const override;
253
254 bool expandPostRAPseudo(MachineInstr &MI) const override;
255
256 std::pair<unsigned, unsigned>
257 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
258 ArrayRef<std::pair<unsigned, const char *>>
259 getSerializableDirectMachineOperandTargetFlags() const override;
260 ArrayRef<std::pair<unsigned, const char *>>
261 getSerializableBitmaskMachineOperandTargetFlags() const override;
262 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
263 getSerializableMachineMemOperandTargetFlags() const override;
264
265 bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
266 bool OutlineFromLinkOnceODRs) const override;
267 outliner::OutlinedFunction getOutliningCandidateInfo(
268 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
269 outliner::InstrType
270 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
271 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
272 unsigned &Flags) const override;
273 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
274 const outliner::OutlinedFunction &OF) const override;
275 MachineBasicBlock::iterator
276 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
277 MachineBasicBlock::iterator &It, MachineFunction &MF,
278 const outliner::Candidate &C) const override;
279 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
280 /// Returns the vector element size (B, H, S or D) of an SVE opcode.
281 uint64_t getElementSizeForOpcode(unsigned Opc) const;
282 /// Returns true if the instruction has a shift by immediate that can be
283 /// executed in one cycle less.
284 static bool isFalkorShiftExtFast(const MachineInstr &MI);
285 /// Return true if the instructions is a SEH instruciton used for unwinding
286 /// on Windows.
287 static bool isSEHInstruction(const MachineInstr &MI);
288
289 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
290 Register Reg) const override;
291
292 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
293 Register Reg) const override;
294
295 static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset,
296 int64_t &NumBytes,
297 int64_t &NumPredicateVectors,
298 int64_t &NumDataVectors);
299 static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset,
300 int64_t &ByteSized,
301 int64_t &VGSized);
302 #define GET_INSTRINFO_HELPER_DECLS
303 #include "AArch64GenInstrInfo.inc"
304
305 protected:
306 /// If the specific machine instruction is an instruction that moves/copies
307 /// value from one register to another register return destination and source
308 /// registers as machine operands.
309 Optional<DestSourcePair>
310 isCopyInstrImpl(const MachineInstr &MI) const override;
311
312 private:
313 unsigned getInstBundleLength(const MachineInstr &MI) const;
314
315 /// Sets the offsets on outlined instructions in \p MBB which use SP
316 /// so that they will be valid post-outlining.
317 ///
318 /// \param MBB A \p MachineBasicBlock in an outlined function.
319 void fixupPostOutline(MachineBasicBlock &MBB) const;
320
321 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
322 MachineBasicBlock *TBB,
323 ArrayRef<MachineOperand> Cond) const;
324 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
325 const MachineRegisterInfo *MRI) const;
326
327 /// Returns an unused general-purpose register which can be used for
328 /// constructing an outlined call if one exists. Returns 0 otherwise.
329 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
330 };
331
332 /// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
333 /// which either reads or clobbers NZCV.
334 bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
335 const MachineInstr &UseMI,
336 const TargetRegisterInfo *TRI);
337
338 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
339 /// plus Offset. This is intended to be used from within the prolog/epilog
340 /// insertion (PEI) pass, where a virtual scratch register may be allocated
341 /// if necessary, to be replaced by the scavenger at the end of PEI.
342 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
343 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
344 StackOffset Offset, const TargetInstrInfo *TII,
345 MachineInstr::MIFlag = MachineInstr::NoFlags,
346 bool SetNZCV = false, bool NeedsWinCFI = false,
347 bool *HasWinCFI = nullptr);
348
349 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
350 /// FP. Return false if the offset could not be handled directly in MI, and
351 /// return the left-over portion by reference.
352 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
353 unsigned FrameReg, StackOffset &Offset,
354 const AArch64InstrInfo *TII);
355
356 /// Use to report the frame offset status in isAArch64FrameOffsetLegal.
357 enum AArch64FrameOffsetStatus {
358 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
359 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
360 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
361 };
362
363 /// Check if the @p Offset is a valid frame offset for @p MI.
364 /// The returned value reports the validity of the frame offset for @p MI.
365 /// It uses the values defined by AArch64FrameOffsetStatus for that.
366 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
367 /// use an offset.eq
368 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
369 /// rewritten in @p MI.
370 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
371 /// amount that is off the limit of the legal offset.
372 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
373 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
374 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
375 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
376 /// is a legal offset.
377 int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
378 bool *OutUseUnscaledOp = nullptr,
379 unsigned *OutUnscaledOp = nullptr,
380 int64_t *EmittableOffset = nullptr);
381
isUncondBranchOpcode(int Opc)382 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
383
isCondBranchOpcode(int Opc)384 static inline bool isCondBranchOpcode(int Opc) {
385 switch (Opc) {
386 case AArch64::Bcc:
387 case AArch64::CBZW:
388 case AArch64::CBZX:
389 case AArch64::CBNZW:
390 case AArch64::CBNZX:
391 case AArch64::TBZW:
392 case AArch64::TBZX:
393 case AArch64::TBNZW:
394 case AArch64::TBNZX:
395 return true;
396 default:
397 return false;
398 }
399 }
400
isIndirectBranchOpcode(int Opc)401 static inline bool isIndirectBranchOpcode(int Opc) {
402 switch (Opc) {
403 case AArch64::BR:
404 case AArch64::BRAA:
405 case AArch64::BRAB:
406 case AArch64::BRAAZ:
407 case AArch64::BRABZ:
408 return true;
409 }
410 return false;
411 }
412
413 /// Return opcode to be used for indirect calls.
414 unsigned getBLRCallOpcode(const MachineFunction &MF);
415
416 // struct TSFlags {
417 #define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
418 #define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bit
419 #define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
420 // }
421
422 namespace AArch64 {
423
424 enum ElementSizeType {
425 ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7),
426 ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0),
427 ElementSizeB = TSFLAG_ELEMENT_SIZE_TYPE(0x1),
428 ElementSizeH = TSFLAG_ELEMENT_SIZE_TYPE(0x2),
429 ElementSizeS = TSFLAG_ELEMENT_SIZE_TYPE(0x3),
430 ElementSizeD = TSFLAG_ELEMENT_SIZE_TYPE(0x4),
431 };
432
433 enum DestructiveInstType {
434 DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0xf),
435 NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0),
436 DestructiveOther = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
437 DestructiveUnary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x2),
438 DestructiveBinaryImm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x3),
439 DestructiveBinaryShImmUnpred = TSFLAG_DESTRUCTIVE_INST_TYPE(0x4),
440 DestructiveBinary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x5),
441 DestructiveBinaryComm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x6),
442 DestructiveBinaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x7),
443 DestructiveTernaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x8),
444 };
445
446 enum FalseLaneType {
447 FalseLanesMask = TSFLAG_FALSE_LANE_TYPE(0x3),
448 FalseLanesZero = TSFLAG_FALSE_LANE_TYPE(0x1),
449 FalseLanesUndef = TSFLAG_FALSE_LANE_TYPE(0x2),
450 };
451
452 #undef TSFLAG_ELEMENT_SIZE_TYPE
453 #undef TSFLAG_DESTRUCTIVE_INST_TYPE
454 #undef TSFLAG_FALSE_LANE_TYPE
455
456 int getSVEPseudoMap(uint16_t Opcode);
457 int getSVERevInstr(uint16_t Opcode);
458 int getSVENonRevInstr(uint16_t Opcode);
459 }
460
461 } // end namespace llvm
462
463 #endif
464