1 // Copyright 2014, VIXL authors
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26 
27 #ifndef VIXL_CPU_AARCH64_H
28 #define VIXL_CPU_AARCH64_H
29 
30 #include "../cpu-features.h"
31 #include "../globals-vixl.h"
32 
33 #include "instructions-aarch64.h"
34 
35 #ifndef VIXL_INCLUDE_TARGET_AARCH64
36 // The supporting .cc file is only compiled when the A64 target is selected.
37 // Throw an explicit error now to avoid a harder-to-debug linker error later.
38 //
39 // These helpers _could_ work on any AArch64 host, even when generating AArch32
40 // code, but we don't support this because the available features may differ
41 // between AArch32 and AArch64 on the same platform, so basing AArch32 code
42 // generation on aarch64::CPU features is probably broken.
43 #error cpu-aarch64.h requires VIXL_INCLUDE_TARGET_AARCH64 (scons target=a64).
44 #endif
45 
46 namespace vixl {
47 namespace aarch64 {
48 
49 // A CPU ID register, for use with CPUFeatures::kIDRegisterEmulation. Fields
50 // specific to each register are described in relevant subclasses.
51 class IDRegister {
52  protected:
value_(value)53   explicit IDRegister(uint64_t value = 0) : value_(value) {}
54 
55   class Field {
56    public:
57     enum Type { kUnsigned, kSigned };
58 
59     // This needs to be constexpr so that fields have "constant initialisation".
60     // This avoids initialisation order problems when these values are used to
61     // (dynamically) initialise static variables, etc.
62     explicit constexpr Field(int lsb, Type type = kUnsigned)
lsb_(lsb)63         : lsb_(lsb), type_(type) {}
64 
65     static const int kMaxWidthInBits = 4;
66 
GetWidthInBits()67     int GetWidthInBits() const {
68       // All current ID fields have four bits.
69       return kMaxWidthInBits;
70     }
GetLsb()71     int GetLsb() const { return lsb_; }
GetMsb()72     int GetMsb() const { return lsb_ + GetWidthInBits() - 1; }
GetType()73     Type GetType() const { return type_; }
74 
75    private:
76     int lsb_;
77     Type type_;
78   };
79 
80  public:
81   // Extract the specified field, performing sign-extension for signed fields.
82   // This allows us to implement the 'value >= number' detection mechanism
83   // recommended by the Arm ARM, for both signed and unsigned fields.
84   int Get(Field field) const;
85 
86  private:
87   uint64_t value_;
88 };
89 
90 class AA64PFR0 : public IDRegister {
91  public:
AA64PFR0(uint64_t value)92   explicit AA64PFR0(uint64_t value) : IDRegister(value) {}
93 
94   CPUFeatures GetCPUFeatures() const;
95 
96  private:
97   static const Field kFP;
98   static const Field kAdvSIMD;
99   static const Field kRAS;
100   static const Field kSVE;
101   static const Field kDIT;
102   static const Field kCSV2;
103   static const Field kCSV3;
104 };
105 
106 class AA64PFR1 : public IDRegister {
107  public:
AA64PFR1(uint64_t value)108   explicit AA64PFR1(uint64_t value) : IDRegister(value) {}
109 
110   CPUFeatures GetCPUFeatures() const;
111 
112  private:
113   static const Field kBT;
114   static const Field kSSBS;
115   static const Field kMTE;
116 };
117 
118 class AA64ISAR0 : public IDRegister {
119  public:
AA64ISAR0(uint64_t value)120   explicit AA64ISAR0(uint64_t value) : IDRegister(value) {}
121 
122   CPUFeatures GetCPUFeatures() const;
123 
124  private:
125   static const Field kAES;
126   static const Field kSHA1;
127   static const Field kSHA2;
128   static const Field kCRC32;
129   static const Field kAtomic;
130   static const Field kRDM;
131   static const Field kSHA3;
132   static const Field kSM3;
133   static const Field kSM4;
134   static const Field kDP;
135   static const Field kFHM;
136   static const Field kTS;
137   static const Field kRNDR;
138 };
139 
140 class AA64ISAR1 : public IDRegister {
141  public:
AA64ISAR1(uint64_t value)142   explicit AA64ISAR1(uint64_t value) : IDRegister(value) {}
143 
144   CPUFeatures GetCPUFeatures() const;
145 
146  private:
147   static const Field kDPB;
148   static const Field kAPA;
149   static const Field kAPI;
150   static const Field kJSCVT;
151   static const Field kFCMA;
152   static const Field kLRCPC;
153   static const Field kGPA;
154   static const Field kGPI;
155   static const Field kFRINTTS;
156   static const Field kSB;
157   static const Field kSPECRES;
158   static const Field kBF16;
159   static const Field kDGH;
160   static const Field kI8MM;
161 };
162 
163 class AA64MMFR1 : public IDRegister {
164  public:
AA64MMFR1(uint64_t value)165   explicit AA64MMFR1(uint64_t value) : IDRegister(value) {}
166 
167   CPUFeatures GetCPUFeatures() const;
168 
169  private:
170   static const Field kLO;
171 };
172 
173 class AA64MMFR2 : public IDRegister {
174  public:
AA64MMFR2(uint64_t value)175   explicit AA64MMFR2(uint64_t value) : IDRegister(value) {}
176 
177   CPUFeatures GetCPUFeatures() const;
178 
179  private:
180   static const Field kAT;
181 };
182 
183 class AA64ZFR0 : public IDRegister {
184  public:
AA64ZFR0(uint64_t value)185   explicit AA64ZFR0(uint64_t value) : IDRegister(value) {}
186 
187   CPUFeatures GetCPUFeatures() const;
188 
189  private:
190   static const Field kBF16;
191   static const Field kI8MM;
192   static const Field kF32MM;
193   static const Field kF64MM;
194 };
195 
196 class CPU {
197  public:
198   // Initialise CPU support.
199   static void SetUp();
200 
201   // Ensures the data at a given address and with a given size is the same for
202   // the I and D caches. I and D caches are not automatically coherent on ARM
203   // so this operation is required before any dynamically generated code can
204   // safely run.
205   static void EnsureIAndDCacheCoherency(void *address, size_t length);
206 
207   // Read and interpret the ID registers. This requires
208   // CPUFeatures::kIDRegisterEmulation, and therefore cannot be called on
209   // non-AArch64 platforms.
210   static CPUFeatures InferCPUFeaturesFromIDRegisters();
211 
212   // Read and interpret CPUFeatures reported by the OS. Failed queries (or
213   // unsupported platforms) return an empty list. Note that this is
214   // indistinguishable from a successful query on a platform that advertises no
215   // features.
216   //
217   // Non-AArch64 hosts are considered to be unsupported platforms, and this
218   // function returns an empty list.
219   static CPUFeatures InferCPUFeaturesFromOS(
220       CPUFeatures::QueryIDRegistersOption option =
221           CPUFeatures::kQueryIDRegistersIfAvailable);
222 
223   // Query the SVE vector length. This requires CPUFeatures::kSVE.
224   static int ReadSVEVectorLengthInBits();
225 
226   // Handle tagged pointers.
227   template <typename T>
SetPointerTag(T pointer,uint64_t tag)228   static T SetPointerTag(T pointer, uint64_t tag) {
229     VIXL_ASSERT(IsUintN(kAddressTagWidth, tag));
230 
231     // Use C-style casts to get static_cast behaviour for integral types (T),
232     // and reinterpret_cast behaviour for other types.
233 
234     uint64_t raw = (uint64_t)pointer;
235     VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw));
236 
237     raw = (raw & ~kAddressTagMask) | (tag << kAddressTagOffset);
238     return (T)raw;
239   }
240 
241   template <typename T>
GetPointerTag(T pointer)242   static uint64_t GetPointerTag(T pointer) {
243     // Use C-style casts to get static_cast behaviour for integral types (T),
244     // and reinterpret_cast behaviour for other types.
245 
246     uint64_t raw = (uint64_t)pointer;
247     VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw));
248 
249     return (raw & kAddressTagMask) >> kAddressTagOffset;
250   }
251 
252  private:
253 #define VIXL_AARCH64_ID_REG_LIST(V)                                           \
254   V(AA64PFR0, "ID_AA64PFR0_EL1")                                              \
255   V(AA64PFR1, "ID_AA64PFR1_EL1")                                              \
256   V(AA64ISAR0, "ID_AA64ISAR0_EL1")                                            \
257   V(AA64ISAR1, "ID_AA64ISAR1_EL1")                                            \
258   V(AA64MMFR1, "ID_AA64MMFR1_EL1")                                            \
259   /* These registers are RES0 in the baseline Arm8.0. We can always safely */ \
260   /* read them, but some compilers don't accept the symbolic names. */        \
261   V(AA64MMFR2, "S3_0_C0_C7_2")                                                \
262   V(AA64ZFR0, "S3_0_C0_C4_4")
263 
264 #define VIXL_READ_ID_REG(NAME, MRS_ARG) static NAME Read##NAME();
265   // On native AArch64 platforms, read the named CPU ID registers. These require
266   // CPUFeatures::kIDRegisterEmulation, and should not be called on non-AArch64
267   // platforms.
268   VIXL_AARCH64_ID_REG_LIST(VIXL_READ_ID_REG)
269 #undef VIXL_READ_ID_REG
270 
271   // Return the content of the cache type register.
272   static uint32_t GetCacheType();
273 
274   // I and D cache line size in bytes.
275   static unsigned icache_line_size_;
276   static unsigned dcache_line_size_;
277 };
278 
279 }  // namespace aarch64
280 }  // namespace vixl
281 
282 #endif  // VIXL_CPU_AARCH64_H
283