Lines Matching refs:r2
21 and r2, r0, #255 @ r2<- BB
23 GET_VREG r0, r2 @ r0<- vBB
85 mov r2, rINST, lsr #12 @ r2<- B
87 GET_VREG r0, r2 @ r0<- vB
121 and r2, r3, #255 @ r2<- BB
122 GET_VREG r0, r2 @ r0<- vBB
155 and r2, r0, #255 @ r2<- BB
158 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB]
160 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
161 GET_VREG_WIDE_BY_ADDR r2, r3, r3 @ r2/r3<- vCC/vCC+1
163 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
195 GET_VREG_WIDE_BY_ADDR r2, r3, r1 @ r2/r3<- vBB/vBB+1
198 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
272 $instr @ r0/r1<- op, r2-r3 changed
344 and r2, r0, #255 @ r2<- BB
346 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB]
348 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
349 GET_VREG_WIDE_BY_ADDR r2, r3, r3 @ r2/r3<- vCC/vCC+1
350 cmp r0, r2
356 cmpeq r0, r2
378 and r2, r0, #255 @ r2<- BB
380 GET_VREG r0, r2 @ r0<- vBB
437 mov r2, rINST, lsr #12 @ r2<- B
439 GET_VREG r0, r2 @ r0<- vB
467 and r2, r3, #255 @ r2<- BB
468 GET_VREG r0, r2 @ r0<- vBB
545 and r2, r0, #255 @ r2<- BB
547 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB]
549 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
550 GET_VREG_WIDE_BY_ADDR r2, r3, r3 @ r2/r3<- vCC/vCC+1
552 umull r0, lr, r2, r0 @ r0/lr <- ZxX RdLo == Rn - this is OK.
553 mla r3, r1, r2, ip @ r3<- YxX + (ZxW)
557 VREG_INDEX_TO_ADDR r4, r4 @ r2<- &fp[AA]
560 SET_VREG_WIDE_BY_ADDR r0, r1 , r4 @ vAA/vAA+1<- r1/r2
577 GET_VREG_WIDE_BY_ADDR r2, r3, r1 @ r2/r3<- vBB/vBB+1
580 umull r0, lr, r2, r0 @ r0/lr <- ZxX RdLo == Rn - this is OK.
581 mla r3, r1, r2, ip @ r3<- YxX + (ZxW)
635 and r2, r0, #255 @ r2<- BB
637 GET_VREG r0, r2 @ r0<- vBB
643 sdiv r2, r0, r1
644 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed
675 sdiv r2, r0, r1
676 mls r1, r1, r2, r0 @ r1<- op
700 mov r2, rINST, lsr #12 @ r2<- B
702 GET_VREG r0, r2 @ r0<- vB
708 sdiv r2, r0, r1
709 mls r1, r1, r2, r0 @ r1<- op
733 and r2, r3, #255 @ r2<- BB
734 GET_VREG r0, r2 @ r0<- vBB
741 sdiv r2, r0, r1
742 mls r1, r1, r2, r0 @ r1<- op
788 GET_VREG r2, r0 @ r2<- vCC
791 and r2, r2, #63 @ r2<- r2 & 0x3f
793 mov r1, r1, asl r2 @ r1<- r1 << r2
794 rsb r3, r2, #32 @ r3<- 32 - r2
795 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
796 subs ip, r2, #32 @ ip<- r2 - 32
798 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
800 mov r0, r0, asl r2 @ r0<- r0 << r2
813 GET_VREG r2, r3 @ r2<- vB
816 and r2, r2, #63 @ r2<- r2 & 0x3f
818 mov r1, r1, asl r2 @ r1<- r1 << r2
819 rsb r3, r2, #32 @ r3<- 32 - r2
820 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
821 subs ip, r2, #32 @ ip<- r2 - 32
824 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
825 mov r0, r0, asl r2 @ r0<- r0 << r2
852 GET_VREG r2, r0 @ r2<- vCC
855 and r2, r2, #63 @ r0<- r0 & 0x3f
857 mov r0, r0, lsr r2 @ r0<- r2 >> r2
858 rsb r3, r2, #32 @ r3<- 32 - r2
859 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
860 subs ip, r2, #32 @ ip<- r2 - 32
862 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
864 mov r1, r1, asr r2 @ r1<- r1 >> r2
877 GET_VREG r2, r3 @ r2<- vB
880 and r2, r2, #63 @ r2<- r2 & 0x3f
882 mov r0, r0, lsr r2 @ r0<- r2 >> r2
883 rsb r3, r2, #32 @ r3<- 32 - r2
884 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
885 subs ip, r2, #32 @ ip<- r2 - 32
888 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
889 mov r1, r1, asr r2 @ r1<- r1 >> r2
928 GET_VREG r2, r0 @ r2<- vCC
931 and r2, r2, #63 @ r0<- r0 & 0x3f
933 mov r0, r0, lsr r2 @ r0<- r2 >> r2
934 rsb r3, r2, #32 @ r3<- 32 - r2
935 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
936 subs ip, r2, #32 @ ip<- r2 - 32
938 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
940 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
953 GET_VREG r2, r3 @ r2<- vB
956 and r2, r2, #63 @ r2<- r2 & 0x3f
958 mov r0, r0, lsr r2 @ r0<- r2 >> r2
959 rsb r3, r2, #32 @ r3<- 32 - r2
960 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
961 subs ip, r2, #32 @ ip<- r2 - 32
964 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
965 mov r1, r1, lsr r2 @ r1<- r1 >>> r2