Lines Matching defs:DRMCrtcInfo

482 struct DRMCrtcInfo {  struct
483   bool has_src_split;
484   bool has_hdr;
485   uint32_t max_blend_stages;
486   uint32_t max_solidfill_stages;
487   QSEEDVersion qseed_version;
488   SmartDMARevision smart_dma_rev;
489   float ib_fudge_factor;
490   float clk_fudge_factor;
491   uint32_t dest_scale_prefill_lines;
492   uint32_t undersized_prefill_lines;
493   uint32_t macrotile_prefill_lines;
494   uint32_t nv12_prefill_lines;
495   uint32_t linear_prefill_lines;
496   uint32_t downscale_prefill_lines;
497   uint32_t extra_prefill_lines;
498   uint32_t amortized_threshold;
499   uint64_t max_bandwidth_low;
500   uint64_t max_bandwidth_high;
501   uint32_t max_sde_clk;
502   CompRatioMap comp_ratio_rt_map;
503   CompRatioMap comp_ratio_nrt_map;
504   uint32_t hw_version;
505   uint32_t dest_scaler_count = 0;
506   uint32_t max_dest_scaler_input_width = 0;
507   uint32_t max_dest_scaler_output_width = 0;
508   uint32_t max_dest_scale_up = 1;
509   uint32_t min_prefill_lines = 0;
510   int secure_disp_blend_stage = -1;
511   bool concurrent_writeback = false;
512   uint32_t num_mnocports = 0;
513   uint32_t mnoc_bus_width = 0;
514   bool use_baselayer_for_stage = false;
515   uint32_t vig_limit_index = 0;
516   uint32_t dma_limit_index = 0;
517   uint32_t scaling_limit_index = 0;
518   uint32_t rotation_limit_index = 0;
519   uint32_t line_width_constraints_count = 0;
520   std::vector< std::pair <uint32_t, uint32_t> > line_width_limits;
521   float vbif_cmd_ff = 0.0f;