| /art/compiler/optimizing/ |
| D | code_generator_vector_arm64_sve.cc | 645 __ And(dst.VnB(), p_reg, lhs.VnB(), rhs.VnB()); in VisitVecAnd() local
649 __ And(dst.VnH(), p_reg, lhs.VnH(), rhs.VnH()); in VisitVecAnd() local
653 __ And(dst.VnS(), p_reg, lhs.VnS(), rhs.VnS()); in VisitVecAnd() local
657 __ And(dst.VnD(), p_reg, lhs.VnD(), rhs.VnD()); in VisitVecAnd() local
|
| D | code_generator_arm_vixl.cc | 1102 __ And(out, first, second); in GenerateDataProcInstruction() local
4326 __ And(out, dividend, abs_imm - 1); in DivRemByPowerOfTwo() local
4841 __ And(temp1, temp1, temp2); in GenerateMinMaxFloat() local
5111 __ And(shift_right, RegisterFrom(rhs), 0x1F); in HandleLongRotate() local
5241 __ And(out_reg, second_reg, kMaxIntShiftDistance); in HandleShift() local
5277 __ And(o_l, second_reg, kMaxLongShiftDistance); in HandleShift() local
5296 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
5315 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
8579 __ And(out, first, value); in GenerateAndConst() local
8697 __ And(out_reg, first_reg, second_reg); in HandleBitwiseOperation() local
[all …]
|
| D | intrinsics_arm_vixl.cc | 799 __ And(temp2, temp2, temp3); in GenerateStringCompareToLoop() local
800 __ And(out, out, temp3); in GenerateStringCompareToLoop() local
2197 __ And(out_reg_hi, out_reg_hi, in_reg_hi); in GenLowestOneBit() local
2221 __ And(out, temp, in); in GenLowestOneBit() local
3685 __ And(LowRegisterFrom(new_value), LowRegisterFrom(loaded_value), LowRegisterFrom(arg)); in GenerateGetAndUpdate() local
3686 __ And(HighRegisterFrom(new_value), HighRegisterFrom(loaded_value), HighRegisterFrom(arg)); in GenerateGetAndUpdate() local
3688 __ And(RegisterFrom(new_value), RegisterFrom(loaded_value), RegisterFrom(arg)); in GenerateGetAndUpdate() local
|
| D | code_generator_arm64.cc | 1141 __ And(counter, counter, interpreter::kTieredHotnessMask); in MaybeIncrementHotness() local
2149 __ And(dst, lhs, rhs); in HandleBinaryOp() local
2351 __ And(out, left, right_operand); in VisitDataProcWithShifterOp() local
5856 __ And(out, dividend, abs_imm - 1); in GenerateIntRemForPower2Denom() local
5860 __ And(out, dividend, 1); in GenerateIntRemForPower2Denom() local
5867 __ And(out, dividend, abs_imm - 1); in GenerateIntRemForPower2Denom() local
5868 __ And(temp, temp, abs_imm - 1); in GenerateIntRemForPower2Denom() local
|
| D | code_generator_vector_arm64_neon.cc | 802 __ And(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecAnd() local
|
| D | intrinsics_arm64.cc | 474 __ And(dst, temp, src); in GenLowestOneBit() local
1462 __ And(new_value, old_value_reg, arg.IsX() ? arg.X() : arg.W()); in GenerateGetAndUpdate() local
1862 __ And(temp1, temp, Operand(1)); // Extract compression flag. in VisitStringEquals() local
|
| /art/test/953-invoke-polymorphic-compiler/src/ |
| D | Main.java | 182 private static boolean And(boolean lhs, boolean rhs) { in And() method in Main
|