1 /* 2 * Copyright (C) 2019 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ANDROID_EXYNOS_HWC_MODULE_H_ 18 #define ANDROID_EXYNOS_HWC_MODULE_H_ 19 20 #include <array> 21 22 #include "ExynosHWC.h" 23 #include "DeconHeader.h" 24 25 #define G2D_MAX_SRC_NUM 3 26 27 #define VSYNC_DEV_PREFIX "/sys/devices/platform/" 28 #define PSR_DEV_NAME "1c300000.decon_f/psr_info" 29 #define VSYNC_DEV_NAME_EXT "19050000.decon_t/vsync" 30 #define DP_LINK_NAME "130b0000.displayport" 31 #define DP_UEVENT_NAME "change@/devices/platform/%s/extcon/extcon0" 32 #define DP_CABLE_STATE_NAME "/sys/devices/platform/%s/extcon/extcon0/cable.0/state" 33 #define BRIGHTNESS_NODE_0_BASE "/sys/class/backlight/panel0-backlight/brightness" 34 #define MAX_BRIGHTNESS_NODE_0_BASE "/sys/class/backlight/panel0-backlight/max_brightness" 35 #define BRIGHTNESS_NODE_1_BASE "/sys/class/backlight/panel1-backlight/brightness" 36 #define MAX_BRIGHTNESS_NODE_1_BASE "/sys/class/backlight/panel1-backlight/max_brightness" 37 #define EARLY_WAKUP_NODE_BASE "/sys/devices/platform/1c300000.drmdecon/early_wakeup" 38 39 #define IDMA(x) static_cast<decon_idma_type>(x) 40 41 #define MPP_G2D_CAPACITY 3.5 42 43 enum { 44 HWC_DISPLAY_NONE_BIT = 0 45 }; 46 47 /* 48 * pre_assign_info: all display_descriptors that want to reserve 49 */ 50 struct exynos_mpp_t { 51 int physicalType; 52 int logicalType; 53 char name[16]; 54 uint32_t physical_index; 55 uint32_t logical_index; 56 uint32_t pre_assign_info; 57 }; 58 59 const dpp_channel_map_t IDMA_CHANNEL_MAP[] = { 60 /* GF physical index is switched to change assign order */ 61 /* DECON_IDMA is not used */ 62 {MPP_DPP_GF, 0, IDMA(0), IDMA(0)}, 63 {MPP_DPP_VGRFS, 0, IDMA(1), IDMA(1)}, 64 {MPP_DPP_GF, 1, IDMA(2), IDMA(2)}, 65 {MPP_DPP_VGRFS, 1, IDMA(3), IDMA(3)}, 66 {MPP_DPP_GF, 2, IDMA(4), IDMA(4)}, 67 {MPP_DPP_VGRFS, 2, IDMA(5), IDMA(5)}, 68 {MPP_P_TYPE_MAX, 0, IDMA(6), IDMA(6)}, // not idma but.. 69 {static_cast<mpp_phycal_type_t>(MAX_DECON_DMA_TYPE), 0, MAX_DECON_DMA_TYPE, IDMA(7)} 70 }; 71 72 #define MAX_NAME_SIZE 32 73 struct exynos_display_t { 74 uint32_t type; 75 uint32_t index; 76 std::string display_name; 77 std::string decon_node_name; 78 std::string vsync_node_name; 79 }; 80 81 #define PRIMARY_MAIN_BASE_WIN 2 82 #define EXTERNAL_MAIN_BASE_WIN 4 83 84 /******** Description about display bit ********/ 85 /* DISPLAY BIT = 1 << (DISPLAY_MODE_MASK_LEN * display mode 86 * + SECOND_DISPLAY_START_BIT * display index 87 * + display type); 88 * ex) HWC_DISPLAY_EXTERNAL2_BIT = 1 << (DISPLAY_MODE_MASK_LEN * display mode(0) 89 * + SECOND_DISPLAY_START_BIT * display index(1) 90 * + displayy type(1)) 91 * = 1 << 5 92 * PRIMARY MAIN MODE : 93 * 0 bit : HWC_DISPLAY_PRIMARY_BIT, 94 * 1 bit : HWC_DISPLAY_EXTERNAL_BIT, 95 * 2 bit : HWC_DISPLAY_VIRTUAL_BIT, 96 * 5 bit : HWC_DISPLAY_EXTERNAL2_BIT, 97 * EXTERNAL MAIN MODE : 98 * 8 bit : EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT, 99 * 9 bit : EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT, 100 * 10 bit : EXTERNAL_MAIN_DISPLAY_VIRTUAL_BIT, 101 ***************************************************/ 102 103 #define DISPLAY_MODE_MASK_LEN 8 104 #define DISPLAY_MODE_MASK_BIT 0xff 105 #define SECOND_DISPLAY_START_BIT 4 106 107 enum { 108 DISPLAY_MODE_PRIMARY_MAIN = 0, /* This is default mode */ 109 DISPLAY_MODE_EXTERNAL_MAIN, 110 DISPLAY_MODE_NUM 111 }; 112 113 /* 114 * This is base window index of primary display for each display mode. 115 * External display base window is always 0 116 */ 117 const uint32_t PRIMARY_DISP_BASE_WIN[] = {PRIMARY_MAIN_BASE_WIN, EXTERNAL_MAIN_BASE_WIN}; 118 119 #define EXTERNAL_MAIN_DISPLAY_START_BIT (DISPLAY_MODE_MASK_LEN * DISPLAY_MODE_EXTERNAL_MAIN) 120 enum { 121 EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT = 1 << (EXTERNAL_MAIN_DISPLAY_START_BIT + HWC_DISPLAY_PRIMARY), 122 EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT = 1 << (EXTERNAL_MAIN_DISPLAY_START_BIT + HWC_DISPLAY_EXTERNAL), 123 EXTERNAL_MAIN_DISPLAY_VIRTUAL_BIT = 1 << (EXTERNAL_MAIN_DISPLAY_START_BIT + HWC_DISPLAY_VIRTUAL), 124 }; 125 126 enum { 127 HWC_DISPLAY_SECONDARY_BIT = 1 << (SECOND_DISPLAY_START_BIT + HWC_DISPLAY_PRIMARY), 128 }; 129 130 const exynos_mpp_t AVAILABLE_OTF_MPP_UNITS[] = { 131 {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 0, 0, HWC_DISPLAY_PRIMARY_BIT}, 132 {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 1, 0, HWC_DISPLAY_PRIMARY_BIT}, 133 {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF2", 2, 0, HWC_DISPLAY_SECONDARY_BIT}, 134 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT}, 135 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT}, 136 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT} 137 }; 138 139 const exynos_mpp_t AVAILABLE_M2M_MPP_UNITS[] = { 140 #ifndef DISABLE_M2M_MPPS 141 {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 0, HWC_DISPLAY_PRIMARY_BIT}, 142 {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 1, HWC_DISPLAY_PRIMARY_BIT}, 143 {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_EXT", 0, 2, HWC_DISPLAY_EXTERNAL_BIT}, 144 {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_PRI", 0, 3, HWC_DISPLAY_PRIMARY_BIT}, 145 {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_EXT", 0, 4, HWC_DISPLAY_EXTERNAL_BIT}, 146 {MPP_G2D, MPP_LOGICAL_G2D_COMBO, "G2D0-COMBO_VIR", 0, 5, HWC_DISPLAY_VIRTUAL_BIT} 147 #endif 148 }; 149 150 const std::array<exynos_display_t, 2> AVAILABLE_DISPLAY_UNITS = {{ 151 {HWC_DISPLAY_PRIMARY, 0, "PrimaryDisplay", "/dev/dri/card0", ""}, 152 {HWC_DISPLAY_PRIMARY, 1, "SecondaryDisplay", "/dev/dri/card0", ""} 153 }}; 154 155 #endif 156