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Searched defs:reg (Results 1 – 25 of 102) sorted by relevance

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/art/compiler/debug/
Delf_debug_frame_writer.h49 for (int reg = 0; reg < 13; reg++) { in WriteCIE() local
57 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
72 for (int reg = 0; reg < 30; reg++) { in WriteCIE() local
80 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
98 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
109 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
122 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
132 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
/art/libelffile/dwarf/
Ddebug_frame_opcode_writer.h73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset()
119 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset()
141 void ALWAYS_INLINE Restore(Reg reg) { in Restore()
153 void ALWAYS_INLINE Undefined(Reg reg) { in Undefined()
161 void ALWAYS_INLINE SameValue(Reg reg) { in SameValue()
170 void ALWAYS_INLINE Register(Reg reg, Reg new_reg) { in Register()
193 void ALWAYS_INLINE DefCFA(Reg reg, int offset) { in DefCFA()
210 void ALWAYS_INLINE DefCFARegister(Reg reg) { in DefCFARegister()
236 void ALWAYS_INLINE ValOffset(Reg reg, int offset) { in ValOffset()
263 void ALWAYS_INLINE Expression(Reg reg, uint8_t* expr, int expr_size) { in Expression()
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/art/compiler/utils/x86/
Dmanaged_register_x86_test.cc26 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
32 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
66 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); in TEST() local
92 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); in TEST() local
118 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
256 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
Dassembler_x86.h92 bool IsRegister(Register reg) const { in IsRegister()
145 explicit Operand(Register reg) : disp_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand()
850 void LockCmpxchgb(const Address& address, Register reg) { in LockCmpxchgb()
855 void LockCmpxchgb(const Address& address, ByteRegister reg) { in LockCmpxchgb()
859 void LockCmpxchgw(const Address& address, Register reg) { in LockCmpxchgw()
870 void LockCmpxchgl(const Address& address, Register reg) { in LockCmpxchgl()
878 void LockXaddb(const Address& address, Register reg) { in LockXaddb()
883 void LockXaddb(const Address& address, ByteRegister reg) { in LockXaddb()
887 void LockXaddw(const Address& address, Register reg) { in LockXaddw()
898 void LockXaddl(const Address& address, Register reg) { in LockXaddl()
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Dmanaged_register_x86.cc41 RegisterPair reg; // Used to verify that the enum is in sync. member
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { in operator <<()
Dassembler_x86.cc27 std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { in operator <<()
31 std::ostream& operator<<(std::ostream& os, const X87Register& reg) { in operator <<()
69 void X86Assembler::call(Register reg) { in call()
102 void X86Assembler::pushl(Register reg) { in pushl()
127 void X86Assembler::popl(Register reg) { in popl()
2670 void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) { in psllw()
2681 void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) { in pslld()
2692 void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) { in psllq()
2703 void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) { in psraw()
2714 void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) { in psrad()
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/art/compiler/utils/x86_64/
Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); in TEST() local
91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); in TEST() local
117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
Dassembler_x86_64.h115 bool IsRegister(CpuRegister reg) const { in IsRegister()
174 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand()
902 void LockCmpxchgl(const Address& address, CpuRegister reg) { in LockCmpxchgl()
906 void LockCmpxchgq(const Address& address, CpuRegister reg) { in LockCmpxchgq()
959 void PoisonHeapReference(CpuRegister reg) { negl(reg); } in PoisonHeapReference()
961 void UnpoisonHeapReference(CpuRegister reg) { negl(reg); } in UnpoisonHeapReference()
963 void MaybePoisonHeapReference(CpuRegister reg) { in MaybePoisonHeapReference()
969 void MaybeUnpoisonHeapReference(CpuRegister reg) { in MaybeUnpoisonHeapReference()
1060 inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) { in EmitRegisterOperand()
1066 inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) { in EmitXmmRegisterOperand()
Dmanaged_register_x86_64.cc40 RegisterPair reg; // Used to verify that the enum is in sync. member
52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { in operator <<()
/art/runtime/arch/arm/
Dcontext_arm.h57 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
62 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
67 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
75 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
80 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
Dcontext_arm.cc61 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
68 void ArmContext::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
/art/runtime/arch/x86_64/
Dcontext_x86_64.h56 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
61 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
66 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
74 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
79 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
Dasm_support_x86_64.S76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
78 #define CFI_RESTORE(reg) .cfi_restore reg argument
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
86 #define CFI_RESTORE_STATE_AND_DEF_CFA(reg,off) .cfi_restore_state .cfi_def_cfa reg,off argument
93 #define CFI_DEF_CFA(reg,size) argument
94 #define CFI_DEF_CFA_REGISTER(reg) argument
95 #define CFI_RESTORE(reg) argument
96 #define CFI_REL_OFFSET(reg,size) argument
122 #define CFI_REG(reg) CFI_REG_##reg argument
Dcontext_x86_64.cc89 void X86_64Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
96 void X86_64Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
/art/runtime/arch/arm64/
Dcontext_arm64.h57 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
62 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
67 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
76 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
81 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
Dcontext_arm64.cc67 void Arm64Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
75 void Arm64Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); in TEST() local
126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); in TEST() local
227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); in TEST() local
459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
Dassembler_arm_vixl.cc61 void ArmVIXLAssembler::PoisonHeapReference(vixl::aarch32::Register reg) { in PoisonHeapReference()
66 void ArmVIXLAssembler::UnpoisonHeapReference(vixl::aarch32::Register reg) { in UnpoisonHeapReference()
71 void ArmVIXLAssembler::MaybePoisonHeapReference(vixl32::Register reg) { in MaybePoisonHeapReference()
77 void ArmVIXLAssembler::MaybeUnpoisonHeapReference(vixl32::Register reg) { in MaybeUnpoisonHeapReference()
245 vixl32::Register reg, in StoreToOffset()
368 void ArmVIXLAssembler::LoadSFromOffset(vixl32::SRegister reg, in LoadSFromOffset()
374 void ArmVIXLAssembler::LoadDFromOffset(vixl32::DRegister reg, in LoadDFromOffset()
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc27 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
34 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
107 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); in TEST() local
169 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); in TEST() local
220 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); in TEST() local
376 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
Dassembler_arm64.cc165 void Arm64Assembler::PoisonHeapReference(Register reg) { in PoisonHeapReference()
171 void Arm64Assembler::UnpoisonHeapReference(Register reg) { in UnpoisonHeapReference()
177 void Arm64Assembler::MaybePoisonHeapReference(Register reg) { in MaybePoisonHeapReference()
183 void Arm64Assembler::MaybeUnpoisonHeapReference(Register reg) { in MaybeUnpoisonHeapReference()
/art/runtime/arch/x86/
Dcontext_x86.h52 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
57 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
62 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
70 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
75 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
Dasm_support_x86.S77 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
78 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
79 #define CFI_RESTORE(reg) .cfi_restore reg argument
80 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
87 #define CFI_RESTORE_STATE_AND_DEF_CFA(reg,off) .cfi_restore_state .cfi_def_cfa reg,off argument
94 #define CFI_DEF_CFA(reg,size) argument
95 #define CFI_DEF_CFA_REGISTER(reg) argument
96 #define CFI_RESTORE(reg) argument
97 #define CFI_REL_OFFSET(reg,size) argument
100 #define CFI_RESTORE_STATE_AND_DEF_CFA(reg,off) argument
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Dcontext_x86.cc77 void X86Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
84 void X86Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
/art/runtime/interpreter/
Dcfi_asm_support.h48 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(reg, offset, size) .cfi_escape \ argument
54 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(reg, offset, size) .cfi_escape \ argument
80 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(reg, offset, size) argument
81 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(reg, offset, size) argument
/art/runtime/verifier/
Dregister_line.h373 const uint32_t reg = pair.first; in IterateRegToLockDepths() local
394 bool IsSetLockDepth(size_t reg, size_t depth) { in IsSetLockDepth()
403 bool SetRegToLockDepth(size_t reg, size_t depth) { in SetRegToLockDepth()
419 void ClearAllRegToLockDepths(size_t reg) { in ClearAllRegToLockDepths()

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