1 /* 2 * Copyright (C) 2017-2018 NXP Semiconductors 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef NCILXDEBUGDECODER_H_ 18 #define NCILXDEBUGDECODER_H_ 19 20 #include "phOsal_Adaptation.h" 21 22 #include <string> 23 24 using namespace std; 25 26 #ifdef __cplusplus 27 extern "C" { /* Assume C declarations for C++ */ 28 #endif /* __cplusplus */ 29 30 #define MAX_TLV 15 31 32 /* 33 typedef struct timeStamp { 34 uint16_t timeStampMs; //millisec elapsed after last RF 35 On Event. Tells Raw RSSI values in case of RSSI debug mode uint16_t timeStampUs; 36 //microsec elapsed after last RF On Event. Insignificant values in case of RSSI 37 debug mode } stimeStamp_t, *pstimeStamp_t; 38 39 typedef struct cliffState { 40 uint8_t cliffStateTriggerType; //L1 or L2 or Felica Event Name 41 uint8_t cliffStateTriggerTypeDirection; //Either Tx or Rx 42 uint8_t cliffStateRFTechNMode; //CLIFF RF Technology and Mode 43 } scliffState_t, *pscliffState_t; 44 45 typedef struct rssiValues { 46 uint8_t rawRSSIADC; //When RSSI debug mode is enabled 47 uint8_t rawRSSIAGC; //When RSSI debug mode is enabled 48 uint16_t intrpltdRSSI; //When RSSI debug mode is enabled 49 } srssiValues_t, *psrssiValues_t; 50 51 typedef struct apcValues { 52 uint16_t APC; //In case of Tx event 53 uint8_t residualCarrier; 54 uint8_t numDriver; 55 float vtxAmp; 56 float vtxLDO; 57 uint16_t txVpp; 58 } sapcValues_t, *psapcValues_t; 59 60 typedef struct felicaInfo { 61 string felicaCmdCode; 62 string felicaSysCode; 63 string felicaRspCode; 64 uint8_t felicaRspCodeStatusFlags[2]; 65 string felicaMisc; 66 string eddFelica; 67 } sfelicaInfo_t, *psfelicaInfo_t; 68 69 typedef struct extraDbgData { 70 uint8_t eddL1Error; 71 uint8_t eddL1RxNak; 72 uint8_t eddL1TxErr; 73 uint16_t eddL178164RetCode; 74 uint8_t eddL2WUP; 75 uint8_t eddFelica; 76 } sextraDbgData_t, *psextraDbgData_t; 77 */ 78 79 typedef struct { 80 uint16_t timeStampMs; // millisec elapsed after last RF On Event. Tells Raw 81 // RSSI values in case of RSSI debug mode 82 uint16_t timeStampUs; // microsec elapsed after last RF On Event. 83 // Insignificant values in case of RSSI debug mode 84 uint8_t* pCliffStateTriggerType; // L1 or L2 or Felica Event Name 85 uint8_t* pCliffStateTriggerTypeDirection; // Either Tx or Rx 86 uint8_t* pCliffStateRFTechNMode; // CLIFF RF Technology and Mode 87 uint8_t rawRSSIADC; // When RSSI debug mode is enabled 88 uint8_t rawRSSIAGC; // When RSSI debug mode is enabled 89 uint8_t intrpltdRSSI[2]; // When RSSI debug mode is enabled 90 uint8_t APC[2]; // In case of Tx event 91 uint8_t* pEddL1Error; 92 uint8_t* pEddL1RxNak; 93 uint8_t* pEddL1TxErr; 94 uint8_t eddL178164RetCode[2]; 95 uint8_t* pEddL2WUP; 96 uint8_t felicaCmdCode; 97 uint8_t felicaSysCode[2]; 98 uint8_t felicaRspCode; 99 uint8_t felicaRspCodeStatusFlags[2]; 100 uint8_t* pFelicaMisc; 101 uint8_t eddFelica; 102 uint8_t residualCarrier; 103 uint8_t numDriver; 104 int16_t vtxAmp; 105 float vtxLDO; 106 uint16_t txVpp; 107 } sDecodedInfo_t, *psDecodedInfo_t; 108 109 typedef struct { 110 uint8_t* pLxNtf; 111 uint16_t LxNtfLen; 112 } sLxNtfCoded_t, *psLxNtfCoded_t; 113 114 typedef struct { 115 uint8_t baseIndex; 116 uint8_t milliSecOffset; 117 uint8_t microSecOffset; // Not significant in case of RSSI debug mode 118 uint8_t rawRSSIOffset; // In case of RSSI debug enabled 119 uint8_t intrpltdRSSIOffset; 120 uint8_t apcOffset; 121 uint8_t cliffStateTriggerTypeOffset; 122 uint8_t cliffStateRFTechModeOffset; 123 uint8_t retCode78164Offset; 124 uint8_t felicaCmdOffset; 125 uint8_t felicaSysCodeOffset; 126 uint8_t felicaRspCodeOffset; 127 uint8_t felicaRspStatusFlagsOffset; 128 uint8_t felicaMiscOffset; 129 uint8_t eddOffset; 130 uint8_t eddFelicaOffset; 131 } sLxNtfDecodingInfo_t, *psLxNtfDecodingInfo_t; 132 133 typedef struct { 134 sDecodedInfo_t sInfo; 135 } sL1NtfDecoded_t, *psL1NtfDecoded_t; 136 137 typedef struct { 138 uint8_t tlvCount; 139 sDecodedInfo_t sTlvInfo[MAX_TLV]; 140 } sL2NtfDecoded_t, *psL2NtfDecoded_t; 141 142 typedef struct { 143 uint8_t level; 144 psL1NtfDecoded_t psL1NtfDecoded; 145 psL2NtfDecoded_t psL2NtfDecoded; 146 } sLxNtfDecoded_t, *psLxNtfDecoded_t; 147 148 class NCI_LxDebug_Decoder { 149 private: 150 static NCI_LxDebug_Decoder* mLxDbgDecoder; 151 152 uint8_t mL2DebugMode; // bit:0 Byte0 153 uint8_t mFelicaRFDebugMode; // bit:1 Byte0 154 uint8_t mFelicaSCDebugMode; // bit:2 Byte0 155 uint8_t mL1DebugMode; // bit:4 Byte0 156 uint8_t m7816DebugMode; // bit:6 Byte0 157 uint8_t mRssiDebugMode; // bit:0 Byte1 158 159 float mLOOKUP_VTXLDO[5] = {3.0, 3.3, 3.6, 4.5, 4.7}; // in Volts 160 int16_t mLOOKUP_VTXAMP[4] = {-150, -250, -500, -1000}; // in mVolts 161 uint8_t mLOOKUP_NUMDRIVER[2] = {1, 2}; 162 uint8_t mLOOKUP_RESCARRIER[32] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 163 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 164 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; 165 166 uint16_t mLOOKUP_VTXLDO_BITMASK = 0x0700; 167 uint16_t mLOOKUP_VTXAMP_BITMASK = 0x00C0; 168 uint16_t mLOOKUP_NUMDRIVER_BITMASK = 0x0020; 169 uint16_t mLOOKUP_RESCARRIER_BITMASK = 0x001F; 170 171 uint8_t mCLF_EVT_DIRECTION[2][11] = {"CLF_EVT_RX", "CLF_EVT_TX"}; 172 173 uint8_t mCLF_STAT_L1_TRIG_TYPE[15][27] = { 174 "CLF_L1_EVT_RFU", "CLF_L1_EVT_ACTIVATED", 175 "CLF_L1_EVT_DATA_RX", "CLF_L1_EVT_RX_DESELECT", 176 "CLF_L1_EVT_RX_WTX", "CLF_L1_EVT_ERROR", 177 "CLF_L1_EVT_RX_ACK", "CLF_L1_EVT_RX_NACK", 178 "CLF_L1_EVT_DATA_TX", "CLF_L1_EVT_WTX_AND_DATA_TX", 179 "CLF_L1_EVT_TX_DESELECT", "CLF_L1_EVT_TX_WTX", 180 "CLF_L1_EVT_TX_ACK", "CLF_L1_EVT_TX_NAK", 181 "CLF_L1_EVT_EXTENDED"}; 182 183 uint8_t mCLF_STAT_L2_TRIG_TYPE[12][31] = { 184 "CLF_L2_EVT_RFU", "CLF_L2_EVT_MODULATION_DETECTED", "CLF_L2_EVT_DATA_RX", 185 "CLF_L2_EVT_TIMEOUT", 186 "CLF_L2_EVT_ACTIVE_ISO14443_3", // Internal to card Layer3 activation 187 "CLF_L2_EVT_ERROR", "CLF_L2_EVT_SENSING", 188 "CLF_L2_EVT_ACTIVE_ISO14443_4", // APC, Because Layer4 activation sent to 189 // reader as Tx 190 "CLF_L2_EVT_RFON", "CLF_L2_EVT_RFOFF", "CLF_L2_EVT_DATA_TX", 191 "CLF_L2_EVT_WUP_IOT_RECONFIG" // APC 192 }; 193 194 uint8_t mCLF_STAT_RF_TECH_MODE[14][42] = { 195 "CLF_STATE_TECH_RFU", 196 "CLF_STATE_TECH_CE_A", 197 "CLF_STATE_TECH_CE_B", 198 "CLF_STATE_TECH_CE_F", 199 "CLF_STATE_TECH_NFCIP1_TARGET_PASSIVE_A", 200 "CLF_STATE_TECH_NFCIP1_TARGET_PASSIVE_F", 201 "CLF_STATE_TECH_NFCIP1_TARGET_ACTIVE_A", 202 "CLF_STATE_TECH_NFCIP1_TARGET_ACTIVE_F", 203 "CLF_STATE_TECH_RM_A", 204 "CLF_STATE_TECH_RM_B", 205 "CLF_STATE_TECH_RM_F", 206 "CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_A", 207 "CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_B", 208 "CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_F"}; 209 210 uint8_t mEDD_L1_ERROR[8][34] = { 211 "L1_ERROR_EDD_RF_TIMEOUT", "L1_ERROR_EDD_RF_CRC_ERROR", 212 "L1_ERROR_EDD_RF_COLLISION", "L1_ERROR_EDD_RX_DATA_OVERFLOW", 213 "L1_ERROR_EDD_RX_PROTOCOL_ERROR", "L1_ERROR_EDD_TX_NO_DATA_ERROR", 214 "L1_ERROR_EDD_EXTERNAL_FIELD_ERROR", "L1_ERROR_EDD_RXDATA_LENGTH_ERROR"}; 215 216 uint8_t mEDD_L1_TX_ERROR[28] = "L1_TX_EVT_EDD_DPLL_UNLOCKED"; 217 218 uint8_t mEDD_L1_RX_NAK[5][26] = { 219 "L1_RX_NACK_EDD_IOT_STAGE1", "L1_RX_NACK_EDD_IOT_STAGE2", 220 "L1_RX_NACK_EDD_IOT_STAGE3", "L1_RX_NACK_EDD_IOT_STAGE4", 221 "L1_RX_NACK_EDD_IOT_STAGE5"}; 222 223 uint8_t mEDD_L2_WUP[5][22] = { 224 "L2_EDD_WUP_IOT_STAGE1", "L2_EDD_WUP_IOT_STAGE2", "L2_EDD_WUP_IOT_STAGE3", 225 "L2_EDD_WUP_IOT_STAGE4", "L2_EDD_WUP_IOT_STAGE5"}; 226 227 uint8_t mFELICA_MISC_EVT[5][34] = { 228 "FLC_MISC_EVT_RFU", "FLC_MISC_EVT_GENERIC_ERROR", 229 "FLC_MISC_EVT_EMPTY_FRAME_FROM_ESE", "FLC_MISC_EVT_BUFFER_OVERFLOW", 230 "FLC_MISC_EVT_RF_ERROR"}; 231 232 typedef enum { 233 CLF_L1_EVT_RFU = 0x00, 234 CLF_L1_EVT_ACTIVATED = 0x01, // APC 235 CLF_L1_EVT_DATA_RX = 0x02, 236 CLF_L1_EVT_RX_DESLECT = 0x03, 237 CLF_L1_EVT_RX_WTX = 0x04, 238 CLF_L1_EVT_ERROR = 0x05, 239 CLF_L1_EVT_RX_ACK = 0x06, 240 CLF_L1_EVT_RX_NACK = 0x07, 241 CLF_L1_EVT_DATA_TX = 0x08, // APC 242 CLF_L1_EVT_WTX_AND_DATA_TX = 0x09, // APC 243 CLF_L1_EVT_TX_DESELECT = 0x0A, // APC 244 CLF_L1_EVT_TX_WTX = 0x0B, // APC 245 CLF_L1_EVT_TX_ACK = 0x0C, // APC 246 CLF_L1_EVT_TX_NAK = 0x0D, // APC 247 CLF_L1_EVT_EXTENDED = 0x0E // APC 248 } CliffStateL1EventType_t; 249 250 typedef enum { 251 CLF_L2_EVT_RFU = 0x00, 252 CLF_L2_EVT_MODULATION_DETECTED = 0x01, 253 CLF_L2_EVT_DATA_RX = 0x02, 254 CLF_L2_EVT_TIMEOUT = 0x03, 255 CLF_L2_EVT_ACTIVE_ISO14443_3 = 0x04, // Internal to card Layer3 activation 256 CLF_L2_EVT_ERROR = 0x05, 257 CLF_L2_EVT_SENSING = 0x06, 258 CLF_L2_EVT_ACTIVE_ISO14443_4 = 259 0x07, // APC, Because Layer4 activation sent to reader as Tx 260 CLF_L2_EVT_RFON = 0x08, 261 CLF_L2_EVT_RFOFF = 0x09, 262 CLF_L2_EVT_DATA_TX = 0x0A, // APC 263 CLF_L2_EVT_WUP_IOT_RECONFIG = 0x0B 264 } CliffStateL2EventType_t; 265 266 typedef enum { 267 SYSTEM_DEBUG_STATE_L1_MESSAGE = 268 0x35, // RF Exchanges & Events after Activation of NFC-DEP/ISO-DEP 269 SYSTEM_DEBUG_STATE_L2_MESSAGE = 270 0x36 // RF Exchanges & Events before Activation 271 } LxDebugNtfType_t; 272 273 typedef enum { 274 L1_EVT_LEN = 0x07, 275 L1_EVT_EXTRA_DBG_LEN = 0x08, 276 L1_EVT_7816_RET_CODE_LEN = 0x0A 277 } L1DebugNtfLen_t; 278 279 typedef enum { 280 L2_EVT_TAG_ID = 0x10, 281 L2_EVT_FELICA_CMD_TAG_ID = 0x20, 282 L2_EVT_FELICA_SYS_CODE_TAG_ID = 0x30, 283 L2_EVT_FELICA_RSP_CODE_TAG_ID = 0x40, 284 L2_EVT_FELICA_MISC_TAG_ID = 0x50 285 } L2DebugNtfTLVTagId_t; 286 287 typedef enum { 288 L2_EVT_TAG_ID_LEN = 0x07, 289 L2_EVT_TAG_ID_EXTRA_DBG_LEN = 0x08, 290 L2_EVT_FELICA_CMD_TAG_ID_LEN = 0x07, 291 L2_EVT_FELICA_CMD_TAG_ID_EXTRA_DBG_LEN = 0x08, 292 L2_EVT_FELICA_SYS_CODE_TAG_ID_LEN = 0x06, 293 L2_EVT_FELICA_RSP_CODE_TAG_ID_LEN = 0x09, 294 L2_EVT_FELICA_RSP_CODE_TAG_ID_EXTRA_DBG_LEN = 0x0A, 295 L2_EVT_FELICA_MISC_TAG_ID_LEN = 0x05, 296 L2_EVT_FELICA_MISC_TAG_ID_EXTRA_DBG_LEN = 0x06 297 } L2DebugNtfTLVLength_t; 298 299 typedef enum { 300 FLC_RM_EVT_RFU = 0x00, 301 FLC_RM_EVT_ACTIVATED = 0x01, 302 FLC_RM_EVT_DATA_RX, 303 FLC_RM_EVT_RX_READ, 304 FLC_RM_EVT_RX_WRITE, 305 FLC_RM_EVT_ERROR, 306 FLC_RM_EVT_DATA_TX, 307 FLC_RM_EVT_TX_READ, 308 FLC_RM_EVT_TX_WRITE 309 } FelicaRMEvents_t; 310 311 typedef enum { 312 CLF_STATE_TECH_RFU = 0x00, 313 CLF_STATE_TECH_CE_A = 0x10, 314 CLF_STATE_TECH_CE_B = 0x20, 315 CLF_STATE_TECH_CE_F = 0x30, 316 CLF_STATE_TECH_NFCIP1_TARGET_PASSIVE_A = 0x40, 317 CLF_STATE_TECH_NFCIP1_TARGET_PASSIVE_F = 0x50, 318 CLF_STATE_TECH_NFCIP1_TARGET_ACTIVE_A = 0x60, 319 CLF_STATE_TECH_NFCIP1_TARGET_ACTIVE_F = 0x70, 320 CLF_STATE_TECH_RM_A = 0x80, 321 CLF_STATE_TECH_RM_B = 0x90, 322 CLF_STATE_TECH_RM_F = 0xA0, 323 CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_A = 0xC0, 324 CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_B = 0xD0, 325 CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_F = 0xE0 326 } CliffStateTechType_t; 327 328 typedef enum { 329 L1_ERROR_EDD_RF_TIMEOUT = 0x01, 330 L1_ERROR_EDD_RF_CRC_ERROR = 0x02, 331 L1_ERROR_EDD_RF_COLLISION = 0x04, 332 L1_ERROR_EDD_RX_DATA_OVERFLOW = 0x05, 333 L1_ERROR_EDD_RX_PROTOCOL_ERROR = 0x06, 334 L1_ERROR_EDD_TX_NO_DATA_ERROR = 0x07, 335 L1_ERROR_EDD_EXTERNAL_FIELD_ERROR = 0x0A, 336 L1_ERROR_EDD_RXDATA_LENGTH_ERROR = 0x80 337 } ExtraDebugDataforL1_ERROR_t; 338 339 typedef enum { 340 L1_TX_EVT_EDD_DPLL_UNLOCKED = 0x84 341 } ExtraDebugData_L1_ALL_TX_EVENTS_t; 342 343 typedef enum { 344 L1_RX_NACK_EDD_IOT_STAGE1 = 0x85, 345 L1_RX_NACK_EDD_IOT_STAGE2 = 0x86, 346 L1_RX_NACK_EDD_IOT_STAGE3 = 0x87, 347 L1_RX_NACK_EDD_IOT_STAGE4 = 0x88, 348 L1_RX_NACK_EDD_IOT_STAGE5 = 0x89 349 } ExtraDebugData_L1_RX_NACK_t; 350 351 typedef enum { 352 L2_EDD_WUP_IOT_STAGE1 = 0x01, 353 L2_EDD_WUP_IOT_STAGE2 = 0x02, 354 L2_EDD_WUP_IOT_STAGE3 = 0x03, 355 L2_EDD_WUP_IOT_STAGE4 = 0x04, 356 L2_EDD_WUP_IOT_STAGE5 = 0x05, 357 } ExtraDebugData_CLF_L2_EVT_WUP_IOT_RECONFIG_t; 358 359 typedef enum { 360 L2_EDD_FLC_CMD_CODE = 0x01, 361 L2_EDD_FLC_RSP_CODE = 0x02, 362 L2_EDD_FLC_MISC = 0x03 363 } ExtraDebugData_Felica_t; 364 365 typedef enum { 366 FLC_MISC_EVT_RFU = 0x00, 367 FLC_MISC_EVT_GENERIC_ERROR = 0x01, 368 FLC_MISC_EVT_EMPTY_FRAME_FROM_ESE, 369 FLC_MISC_EVT_BUFFER_OVERFLOW, 370 FLC_MISC_EVT_RF_ERROR = 0x05 371 } FelicaMiscEventType_t; 372 373 NCI_LxDebug_Decoder(); 374 void setLxDebugModes(uint8_t* pNciPkt, uint16_t pktLen); 375 void parseL1DbgNtf(psLxNtfCoded_t psLxNtfCoded, 376 psLxNtfDecoded_t psLxNtfDecoded); 377 void parseL2DbgNtf(psLxNtfCoded_t psLxNtfCoded, 378 psLxNtfDecoded_t psLxNtfDecoded); 379 void decodeTimeStamp(psLxNtfCoded_t psLxNtfCoded, 380 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 381 psLxNtfDecoded_t psLxNtfDecoded); 382 void decodeAPCTable(psLxNtfCoded_t psLxNtfCoded, 383 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 384 psLxNtfDecoded_t psLxNtfDecoded); 385 void decodeRSSIValues(psLxNtfCoded_t psLxNtfCoded, 386 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 387 psLxNtfDecoded_t psLxNtfDecoded); 388 void decodeCLIFFState(psLxNtfCoded_t psLxNtfCoded, 389 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 390 psLxNtfDecoded_t psLxNtfDecoded); 391 void decodeRFTechMode(psLxNtfCoded_t psLxNtfCoded, 392 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 393 psLxNtfDecoded_t psLxNtfDecoded); 394 void decodeTriggerType(psLxNtfCoded_t psLxNtfCoded, 395 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 396 psLxNtfDecoded_t psLxNtfDecoded); 397 void decode78164RetCode(psLxNtfCoded_t psLxNtfCoded, 398 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 399 psLxNtfDecoded_t psLxNtfDecoded); 400 void decodeFelicaCmdCode(psLxNtfCoded_t psLxNtfCoded, 401 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 402 psLxNtfDecoded_t psLxNtfDecoded); 403 void decodeFelicaSystemCode(psLxNtfCoded_t psLxNtfCoded, 404 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 405 psLxNtfDecoded_t psLxNtfDecoded); 406 void decodeFelicaRspCode(psLxNtfCoded_t psLxNtfCoded, 407 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 408 psLxNtfDecoded_t psLxNtfDecoded); 409 void decodeFelicaMiscCode(psLxNtfCoded_t psLxNtfCoded, 410 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 411 psLxNtfDecoded_t psLxNtfDecoded); 412 void decodeExtraDbgData(psLxNtfCoded_t psLxNtfCoded, 413 psLxNtfDecodingInfo_t psLxNtfDecodingInfo, 414 psLxNtfDecoded_t psLxNtfDecoded); 415 void calculateTxVpp(psLxNtfDecoded_t psLxNtfDecoded); 416 void printLxDebugInfo(psLxNtfDecoded_t psLxNtfDecoded); 417 418 public: 419 ~NCI_LxDebug_Decoder(); 420 static NCI_LxDebug_Decoder& getInstance(); 421 void processLxDbgNciPkt(uint8_t* pNciPkt, uint16_t pktLen); 422 }; 423 #ifdef __cplusplus 424 } /* Assume C declarations for C++ */ 425 #endif /* __cplusplus */ 426 427 #endif /* NCILXDEBUGDECODER_H_ */ 428