1 /*
2  * Copyright (C) 2015 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #include "linker/arm64/relative_patcher_arm64.h"
18 
19 #include "arch/arm64/asm_support_arm64.h"
20 #include "arch/arm64/instruction_set_features_arm64.h"
21 #include "art_method.h"
22 #include "base/bit_utils.h"
23 #include "base/malloc_arena_pool.h"
24 #include "compiled_method-inl.h"
25 #include "driver/compiler_driver.h"
26 #include "entrypoints/quick/quick_entrypoints_enum.h"
27 #include "heap_poisoning.h"
28 #include "linker/linker_patch.h"
29 #include "lock_word.h"
30 #include "mirror/array-inl.h"
31 #include "mirror/object.h"
32 #include "oat.h"
33 #include "oat_quick_method_header.h"
34 #include "read_barrier.h"
35 #include "stream/output_stream.h"
36 
37 namespace art {
38 namespace linker {
39 
40 namespace {
41 
42 // Maximum positive and negative displacement for method call measured from the patch location.
43 // (Signed 28 bit displacement with the last two bits 0 has range [-2^27, 2^27-4] measured from
44 // the ARM64 PC pointing to the BL.)
45 constexpr uint32_t kMaxMethodCallPositiveDisplacement = (1u << 27) - 4u;
46 constexpr uint32_t kMaxMethodCallNegativeDisplacement = (1u << 27);
47 
48 // Maximum positive and negative displacement for a conditional branch measured from the patch
49 // location. (Signed 21 bit displacement with the last two bits 0 has range [-2^20, 2^20-4]
50 // measured from the ARM64 PC pointing to the B.cond.)
51 constexpr uint32_t kMaxBcondPositiveDisplacement = (1u << 20) - 4u;
52 constexpr uint32_t kMaxBcondNegativeDisplacement = (1u << 20);
53 
54 // The ADRP thunk for erratum 843419 is 2 instructions, i.e. 8 bytes.
55 constexpr uint32_t kAdrpThunkSize = 8u;
56 
IsAdrpPatch(const LinkerPatch & patch)57 inline bool IsAdrpPatch(const LinkerPatch& patch) {
58   switch (patch.GetType()) {
59     case LinkerPatch::Type::kCallRelative:
60     case LinkerPatch::Type::kCallEntrypoint:
61     case LinkerPatch::Type::kBakerReadBarrierBranch:
62       return false;
63     case LinkerPatch::Type::kIntrinsicReference:
64     case LinkerPatch::Type::kDataBimgRelRo:
65     case LinkerPatch::Type::kMethodRelative:
66     case LinkerPatch::Type::kMethodBssEntry:
67     case LinkerPatch::Type::kJniEntrypointRelative:
68     case LinkerPatch::Type::kTypeRelative:
69     case LinkerPatch::Type::kTypeBssEntry:
70     case LinkerPatch::Type::kPublicTypeBssEntry:
71     case LinkerPatch::Type::kPackageTypeBssEntry:
72     case LinkerPatch::Type::kStringRelative:
73     case LinkerPatch::Type::kStringBssEntry:
74       return patch.LiteralOffset() == patch.PcInsnOffset();
75   }
76 }
77 
MaxExtraSpace(size_t num_adrp,size_t code_size)78 inline uint32_t MaxExtraSpace(size_t num_adrp, size_t code_size) {
79   if (num_adrp == 0u) {
80     return 0u;
81   }
82   uint32_t alignment_bytes =
83       CompiledMethod::AlignCode(code_size, InstructionSet::kArm64) - code_size;
84   return kAdrpThunkSize * num_adrp + alignment_bytes;
85 }
86 
87 }  // anonymous namespace
88 
Arm64RelativePatcher(RelativePatcherThunkProvider * thunk_provider,RelativePatcherTargetProvider * target_provider,const Arm64InstructionSetFeatures * features)89 Arm64RelativePatcher::Arm64RelativePatcher(RelativePatcherThunkProvider* thunk_provider,
90                                            RelativePatcherTargetProvider* target_provider,
91                                            const Arm64InstructionSetFeatures* features)
92     : ArmBaseRelativePatcher(thunk_provider, target_provider, InstructionSet::kArm64),
93       fix_cortex_a53_843419_(features->NeedFixCortexA53_843419()),
94       reserved_adrp_thunks_(0u),
95       processed_adrp_thunks_(0u) {
96   if (fix_cortex_a53_843419_) {
97     adrp_thunk_locations_.reserve(16u);
98     current_method_thunks_.reserve(16u * kAdrpThunkSize);
99   }
100 }
101 
ReserveSpace(uint32_t offset,const CompiledMethod * compiled_method,MethodReference method_ref)102 uint32_t Arm64RelativePatcher::ReserveSpace(uint32_t offset,
103                                             const CompiledMethod* compiled_method,
104                                             MethodReference method_ref) {
105   if (!fix_cortex_a53_843419_) {
106     DCHECK(adrp_thunk_locations_.empty());
107     return ReserveSpaceInternal(offset, compiled_method, method_ref, 0u);
108   }
109 
110   // Add thunks for previous method if any.
111   if (reserved_adrp_thunks_ != adrp_thunk_locations_.size()) {
112     size_t num_adrp_thunks = adrp_thunk_locations_.size() - reserved_adrp_thunks_;
113     offset = CompiledMethod::AlignCode(offset, InstructionSet::kArm64) +
114              kAdrpThunkSize * num_adrp_thunks;
115     reserved_adrp_thunks_ = adrp_thunk_locations_.size();
116   }
117 
118   // Count the number of ADRP insns as the upper bound on the number of thunks needed
119   // and use it to reserve space for other linker patches.
120   size_t num_adrp = 0u;
121   DCHECK(compiled_method != nullptr);
122   for (const LinkerPatch& patch : compiled_method->GetPatches()) {
123     if (IsAdrpPatch(patch)) {
124       ++num_adrp;
125     }
126   }
127   ArrayRef<const uint8_t> code = compiled_method->GetQuickCode();
128   uint32_t max_extra_space = MaxExtraSpace(num_adrp, code.size());
129   offset = ReserveSpaceInternal(offset, compiled_method, method_ref, max_extra_space);
130   if (num_adrp == 0u) {
131     return offset;
132   }
133 
134   // Now that we have the actual offset where the code will be placed, locate the ADRP insns
135   // that actually require the thunk.
136   uint32_t quick_code_offset = compiled_method->AlignCode(offset + sizeof(OatQuickMethodHeader));
137   uint32_t thunk_offset = compiled_method->AlignCode(quick_code_offset + code.size());
138   DCHECK(compiled_method != nullptr);
139   for (const LinkerPatch& patch : compiled_method->GetPatches()) {
140     if (IsAdrpPatch(patch)) {
141       uint32_t patch_offset = quick_code_offset + patch.LiteralOffset();
142       if (NeedsErratum843419Thunk(code, patch.LiteralOffset(), patch_offset)) {
143         adrp_thunk_locations_.emplace_back(patch_offset, thunk_offset);
144         thunk_offset += kAdrpThunkSize;
145       }
146     }
147   }
148   return offset;
149 }
150 
ReserveSpaceEnd(uint32_t offset)151 uint32_t Arm64RelativePatcher::ReserveSpaceEnd(uint32_t offset) {
152   if (!fix_cortex_a53_843419_) {
153     DCHECK(adrp_thunk_locations_.empty());
154   } else {
155     // Add thunks for the last method if any.
156     if (reserved_adrp_thunks_ != adrp_thunk_locations_.size()) {
157       size_t num_adrp_thunks = adrp_thunk_locations_.size() - reserved_adrp_thunks_;
158       offset = CompiledMethod::AlignCode(offset, InstructionSet::kArm64) +
159                kAdrpThunkSize * num_adrp_thunks;
160       reserved_adrp_thunks_ = adrp_thunk_locations_.size();
161     }
162   }
163   return ArmBaseRelativePatcher::ReserveSpaceEnd(offset);
164 }
165 
WriteThunks(OutputStream * out,uint32_t offset)166 uint32_t Arm64RelativePatcher::WriteThunks(OutputStream* out, uint32_t offset) {
167   if (fix_cortex_a53_843419_) {
168     if (!current_method_thunks_.empty()) {
169       uint32_t aligned_offset = CompiledMethod::AlignCode(offset, InstructionSet::kArm64);
170       if (kIsDebugBuild) {
171         CHECK_ALIGNED(current_method_thunks_.size(), kAdrpThunkSize);
172         size_t num_thunks = current_method_thunks_.size() / kAdrpThunkSize;
173         CHECK_LE(num_thunks, processed_adrp_thunks_);
174         for (size_t i = 0u; i != num_thunks; ++i) {
175           const auto& entry = adrp_thunk_locations_[processed_adrp_thunks_ - num_thunks + i];
176           CHECK_EQ(entry.second, aligned_offset + i * kAdrpThunkSize);
177         }
178       }
179       uint32_t aligned_code_delta = aligned_offset - offset;
180       if (aligned_code_delta != 0u && !WriteCodeAlignment(out, aligned_code_delta)) {
181         return 0u;
182       }
183       if (!WriteMiscThunk(out, ArrayRef<const uint8_t>(current_method_thunks_))) {
184         return 0u;
185       }
186       offset = aligned_offset + current_method_thunks_.size();
187       current_method_thunks_.clear();
188     }
189   }
190   return ArmBaseRelativePatcher::WriteThunks(out, offset);
191 }
192 
PatchCall(std::vector<uint8_t> * code,uint32_t literal_offset,uint32_t patch_offset,uint32_t target_offset)193 void Arm64RelativePatcher::PatchCall(std::vector<uint8_t>* code,
194                                      uint32_t literal_offset,
195                                      uint32_t patch_offset,
196                                      uint32_t target_offset) {
197   DCHECK_ALIGNED(literal_offset, 4u);
198   DCHECK_ALIGNED(patch_offset, 4u);
199   DCHECK_ALIGNED(target_offset, 4u);
200   uint32_t displacement = CalculateMethodCallDisplacement(patch_offset, target_offset & ~1u);
201   PatchBl(code, literal_offset, displacement);
202 }
203 
PatchPcRelativeReference(std::vector<uint8_t> * code,const LinkerPatch & patch,uint32_t patch_offset,uint32_t target_offset)204 void Arm64RelativePatcher::PatchPcRelativeReference(std::vector<uint8_t>* code,
205                                                     const LinkerPatch& patch,
206                                                     uint32_t patch_offset,
207                                                     uint32_t target_offset) {
208   DCHECK_ALIGNED(patch_offset, 4u);
209   DCHECK_ALIGNED(target_offset, 4u);
210   uint32_t literal_offset = patch.LiteralOffset();
211   uint32_t insn = GetInsn(code, literal_offset);
212   uint32_t pc_insn_offset = patch.PcInsnOffset();
213   uint32_t disp = target_offset - ((patch_offset - literal_offset + pc_insn_offset) & ~0xfffu);
214   bool wide = (insn & 0x40000000) != 0;
215   uint32_t shift = wide ? 3u : 2u;
216   if (literal_offset == pc_insn_offset) {
217     // Check it's an ADRP with imm == 0 (unset).
218     DCHECK_EQ((insn & 0xffffffe0u), 0x90000000u)
219         << literal_offset << ", " << pc_insn_offset << ", 0x" << std::hex << insn;
220     if (fix_cortex_a53_843419_ && processed_adrp_thunks_ != adrp_thunk_locations_.size() &&
221         adrp_thunk_locations_[processed_adrp_thunks_].first == patch_offset) {
222       DCHECK(NeedsErratum843419Thunk(ArrayRef<const uint8_t>(*code),
223                                      literal_offset, patch_offset));
224       uint32_t thunk_offset = adrp_thunk_locations_[processed_adrp_thunks_].second;
225       uint32_t adrp_disp = target_offset - (thunk_offset & ~0xfffu);
226       uint32_t adrp = PatchAdrp(insn, adrp_disp);
227 
228       uint32_t out_disp = thunk_offset - patch_offset;
229       DCHECK_EQ(out_disp & 3u, 0u);
230       DCHECK((out_disp >> 27) == 0u || (out_disp >> 27) == 31u);  // 28-bit signed.
231       insn = (out_disp & 0x0fffffffu) >> shift;
232       insn |= 0x14000000;  // B <thunk>
233 
234       uint32_t back_disp = -out_disp;
235       DCHECK_EQ(back_disp & 3u, 0u);
236       DCHECK((back_disp >> 27) == 0u || (back_disp >> 27) == 31u);  // 28-bit signed.
237       uint32_t b_back = (back_disp & 0x0fffffffu) >> 2;
238       b_back |= 0x14000000;  // B <back>
239       size_t thunks_code_offset = current_method_thunks_.size();
240       current_method_thunks_.resize(thunks_code_offset + kAdrpThunkSize);
241       SetInsn(&current_method_thunks_, thunks_code_offset, adrp);
242       SetInsn(&current_method_thunks_, thunks_code_offset + 4u, b_back);
243       static_assert(kAdrpThunkSize == 2 * 4u, "thunk has 2 instructions");
244 
245       processed_adrp_thunks_ += 1u;
246     } else {
247       insn = PatchAdrp(insn, disp);
248     }
249     // Write the new ADRP (or B to the erratum 843419 thunk).
250     SetInsn(code, literal_offset, insn);
251   } else {
252     if ((insn & 0xfffffc00) == 0x91000000) {
253       // ADD immediate, 64-bit with imm12 == 0 (unset).
254       if (!kEmitCompilerReadBarrier) {
255         DCHECK(patch.GetType() == LinkerPatch::Type::kIntrinsicReference ||
256                patch.GetType() == LinkerPatch::Type::kMethodRelative ||
257                patch.GetType() == LinkerPatch::Type::kTypeRelative ||
258                patch.GetType() == LinkerPatch::Type::kStringRelative) << patch.GetType();
259       } else {
260         // With the read barrier (non-Baker) enabled, it could be kStringBssEntry or kTypeBssEntry.
261         DCHECK(patch.GetType() == LinkerPatch::Type::kIntrinsicReference ||
262                patch.GetType() == LinkerPatch::Type::kMethodRelative ||
263                patch.GetType() == LinkerPatch::Type::kTypeRelative ||
264                patch.GetType() == LinkerPatch::Type::kStringRelative ||
265                patch.GetType() == LinkerPatch::Type::kTypeBssEntry ||
266                patch.GetType() == LinkerPatch::Type::kPublicTypeBssEntry ||
267                patch.GetType() == LinkerPatch::Type::kPackageTypeBssEntry ||
268                patch.GetType() == LinkerPatch::Type::kStringBssEntry) << patch.GetType();
269       }
270       shift = 0u;  // No shift for ADD.
271     } else {
272       // LDR/STR 32-bit or 64-bit with imm12 == 0 (unset).
273       DCHECK(patch.GetType() == LinkerPatch::Type::kDataBimgRelRo ||
274              patch.GetType() == LinkerPatch::Type::kMethodBssEntry ||
275              patch.GetType() == LinkerPatch::Type::kJniEntrypointRelative ||
276              patch.GetType() == LinkerPatch::Type::kTypeBssEntry ||
277              patch.GetType() == LinkerPatch::Type::kPublicTypeBssEntry ||
278              patch.GetType() == LinkerPatch::Type::kPackageTypeBssEntry ||
279              patch.GetType() == LinkerPatch::Type::kStringBssEntry) << patch.GetType();
280       DCHECK_EQ(insn & 0xbfbffc00, 0xb9000000) << std::hex << insn;
281     }
282     if (kIsDebugBuild) {
283       uint32_t adrp = GetInsn(code, pc_insn_offset);
284       if ((adrp & 0x9f000000u) != 0x90000000u) {
285         CHECK(fix_cortex_a53_843419_);
286         CHECK_EQ(adrp & 0xfc000000u, 0x14000000u);  // B <thunk>
287         CHECK_ALIGNED(current_method_thunks_.size(), kAdrpThunkSize);
288         size_t num_thunks = current_method_thunks_.size() / kAdrpThunkSize;
289         CHECK_LE(num_thunks, processed_adrp_thunks_);
290         uint32_t b_offset = patch_offset - literal_offset + pc_insn_offset;
291         for (size_t i = processed_adrp_thunks_ - num_thunks; ; ++i) {
292           CHECK_NE(i, processed_adrp_thunks_);
293           if (adrp_thunk_locations_[i].first == b_offset) {
294             size_t idx = num_thunks - (processed_adrp_thunks_ - i);
295             adrp = GetInsn(&current_method_thunks_, idx * kAdrpThunkSize);
296             break;
297           }
298         }
299       }
300       CHECK_EQ(adrp & 0x9f00001fu,                    // Check that pc_insn_offset points
301                0x90000000 | ((insn >> 5) & 0x1fu));   // to ADRP with matching register.
302     }
303     uint32_t imm12 = (disp & 0xfffu) >> shift;
304     insn = (insn & ~(0xfffu << 10)) | (imm12 << 10);
305     SetInsn(code, literal_offset, insn);
306   }
307 }
308 
PatchEntrypointCall(std::vector<uint8_t> * code,const LinkerPatch & patch,uint32_t patch_offset)309 void Arm64RelativePatcher::PatchEntrypointCall(std::vector<uint8_t>* code,
310                                                const LinkerPatch& patch,
311                                                uint32_t patch_offset) {
312   DCHECK_ALIGNED(patch_offset, 4u);
313   ThunkKey key = GetEntrypointCallKey(patch);
314   uint32_t target_offset = GetThunkTargetOffset(key, patch_offset);
315   uint32_t displacement = target_offset - patch_offset;
316   PatchBl(code, patch.LiteralOffset(), displacement);
317 }
318 
PatchBakerReadBarrierBranch(std::vector<uint8_t> * code,const LinkerPatch & patch,uint32_t patch_offset)319 void Arm64RelativePatcher::PatchBakerReadBarrierBranch(std::vector<uint8_t>* code,
320                                                        const LinkerPatch& patch,
321                                                        uint32_t patch_offset) {
322   DCHECK_ALIGNED(patch_offset, 4u);
323   uint32_t literal_offset = patch.LiteralOffset();
324   uint32_t insn = GetInsn(code, literal_offset);
325   DCHECK_EQ(insn & 0xffffffe0u, 0xb5000000);  // CBNZ Xt, +0 (unpatched)
326   ThunkKey key = GetBakerThunkKey(patch);
327   uint32_t target_offset = GetThunkTargetOffset(key, patch_offset);
328   DCHECK_ALIGNED(target_offset, 4u);
329   uint32_t disp = target_offset - patch_offset;
330   DCHECK((disp >> 20) == 0u || (disp >> 20) == 4095u);  // 21-bit signed.
331   insn |= (disp << (5 - 2)) & 0x00ffffe0u;              // Shift bits 2-20 to 5-23.
332   SetInsn(code, literal_offset, insn);
333 }
334 
MaxPositiveDisplacement(const ThunkKey & key)335 uint32_t Arm64RelativePatcher::MaxPositiveDisplacement(const ThunkKey& key) {
336   switch (key.GetType()) {
337     case ThunkType::kMethodCall:
338     case ThunkType::kEntrypointCall:
339       return kMaxMethodCallPositiveDisplacement;
340     case ThunkType::kBakerReadBarrier:
341       return kMaxBcondPositiveDisplacement;
342   }
343 }
344 
MaxNegativeDisplacement(const ThunkKey & key)345 uint32_t Arm64RelativePatcher::MaxNegativeDisplacement(const ThunkKey& key) {
346   switch (key.GetType()) {
347     case ThunkType::kMethodCall:
348     case ThunkType::kEntrypointCall:
349       return kMaxMethodCallNegativeDisplacement;
350     case ThunkType::kBakerReadBarrier:
351       return kMaxBcondNegativeDisplacement;
352   }
353 }
354 
PatchAdrp(uint32_t adrp,uint32_t disp)355 uint32_t Arm64RelativePatcher::PatchAdrp(uint32_t adrp, uint32_t disp) {
356   return (adrp & 0x9f00001fu) |  // Clear offset bits, keep ADRP with destination reg.
357       // Bottom 12 bits are ignored, the next 2 lowest bits are encoded in bits 29-30.
358       ((disp & 0x00003000u) << (29 - 12)) |
359       // The next 16 bits are encoded in bits 5-22.
360       ((disp & 0xffffc000u) >> (12 + 2 - 5)) |
361       // Since the target_offset is based on the beginning of the oat file and the
362       // image space precedes the oat file, the target_offset into image space will
363       // be negative yet passed as uint32_t. Therefore we limit the displacement
364       // to +-2GiB (rather than the maximim +-4GiB) and determine the sign bit from
365       // the highest bit of the displacement. This is encoded in bit 23.
366       ((disp & 0x80000000u) >> (31 - 23));
367 }
368 
PatchBl(std::vector<uint8_t> * code,uint32_t literal_offset,uint32_t displacement)369 void Arm64RelativePatcher::PatchBl(std::vector<uint8_t>* code,
370                                    uint32_t literal_offset,
371                                    uint32_t displacement) {
372   DCHECK_ALIGNED(displacement, 4u);
373   DCHECK((displacement >> 27) == 0u || (displacement >> 27) == 31u);  // 28-bit signed.
374   uint32_t insn = (displacement & 0x0fffffffu) >> 2;
375   insn |= 0x94000000;  // BL
376 
377   // Check that we're just overwriting an existing BL.
378   DCHECK_EQ(GetInsn(code, literal_offset) & 0xfc000000u, 0x94000000u);
379   // Write the new BL.
380   SetInsn(code, literal_offset, insn);
381 }
382 
NeedsErratum843419Thunk(ArrayRef<const uint8_t> code,uint32_t literal_offset,uint32_t patch_offset)383 bool Arm64RelativePatcher::NeedsErratum843419Thunk(ArrayRef<const uint8_t> code,
384                                                    uint32_t literal_offset,
385                                                    uint32_t patch_offset) {
386   DCHECK_EQ(patch_offset & 0x3u, 0u);
387   if ((patch_offset & 0xff8) == 0xff8) {  // ...ff8 or ...ffc
388     uint32_t adrp = GetInsn(code, literal_offset);
389     DCHECK_EQ(adrp & 0x9f000000, 0x90000000);
390     uint32_t next_offset = patch_offset + 4u;
391     uint32_t next_insn = GetInsn(code, literal_offset + 4u);
392 
393     // Below we avoid patching sequences where the adrp is followed by a load which can easily
394     // be proved to be aligned.
395 
396     // First check if the next insn is the LDR using the result of the ADRP.
397     // LDR <Wt>, [<Xn>, #pimm], where <Xn> == ADRP destination reg.
398     if ((next_insn & 0xffc00000) == 0xb9400000 &&
399         (((next_insn >> 5) ^ adrp) & 0x1f) == 0) {
400       return false;
401     }
402 
403     // And since LinkerPatch::Type::k{Method,Type,String}Relative is using the result
404     // of the ADRP for an ADD immediate, check for that as well. We generalize a bit
405     // to include ADD/ADDS/SUB/SUBS immediate that either uses the ADRP destination
406     // or stores the result to a different register.
407     if ((next_insn & 0x1f000000) == 0x11000000 &&
408         ((((next_insn >> 5) ^ adrp) & 0x1f) == 0 || ((next_insn ^ adrp) & 0x1f) != 0)) {
409       return false;
410     }
411 
412     // LDR <Wt>, <label> is always aligned and thus it doesn't cause boundary crossing.
413     if ((next_insn & 0xff000000) == 0x18000000) {
414       return false;
415     }
416 
417     // LDR <Xt>, <label> is aligned iff the pc + displacement is a multiple of 8.
418     if ((next_insn & 0xff000000) == 0x58000000) {
419       bool is_aligned_load = (((next_offset >> 2) ^ (next_insn >> 5)) & 1) == 0;
420       return !is_aligned_load;
421     }
422 
423     // LDR <Wt>, [SP, #<pimm>] and LDR <Xt>, [SP, #<pimm>] are always aligned loads, as SP is
424     // guaranteed to be 128-bits aligned and <pimm> is multiple of the load size.
425     if ((next_insn & 0xbfc003e0) == 0xb94003e0) {
426       return false;
427     }
428     return true;
429   }
430   return false;
431 }
432 
SetInsn(std::vector<uint8_t> * code,uint32_t offset,uint32_t value)433 void Arm64RelativePatcher::SetInsn(std::vector<uint8_t>* code, uint32_t offset, uint32_t value) {
434   DCHECK_LE(offset + 4u, code->size());
435   DCHECK_ALIGNED(offset, 4u);
436   uint8_t* addr = &(*code)[offset];
437   addr[0] = (value >> 0) & 0xff;
438   addr[1] = (value >> 8) & 0xff;
439   addr[2] = (value >> 16) & 0xff;
440   addr[3] = (value >> 24) & 0xff;
441 }
442 
GetInsn(ArrayRef<const uint8_t> code,uint32_t offset)443 uint32_t Arm64RelativePatcher::GetInsn(ArrayRef<const uint8_t> code, uint32_t offset) {
444   DCHECK_LE(offset + 4u, code.size());
445   DCHECK_ALIGNED(offset, 4u);
446   const uint8_t* addr = &code[offset];
447   return
448       (static_cast<uint32_t>(addr[0]) << 0) +
449       (static_cast<uint32_t>(addr[1]) << 8) +
450       (static_cast<uint32_t>(addr[2]) << 16)+
451       (static_cast<uint32_t>(addr[3]) << 24);
452 }
453 
454 template <typename Alloc>
GetInsn(std::vector<uint8_t,Alloc> * code,uint32_t offset)455 uint32_t Arm64RelativePatcher::GetInsn(std::vector<uint8_t, Alloc>* code, uint32_t offset) {
456   return GetInsn(ArrayRef<const uint8_t>(*code), offset);
457 }
458 
459 }  // namespace linker
460 }  // namespace art
461