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Searched refs:AsRegisterPairLow (Results 1 – 18 of 18) sorted by relevance

/art/compiler/utils/arm/
Dmanaged_register_arm.cc29 Register low = AsRegisterPairLow(); in Overlaps()
81 os << "Pair: " << static_cast<int>(AsRegisterPairLow()) << ", " in Print()
Dmanaged_register_arm.h117 Register reg_low = AsRegisterPairLow(); in AsRegisterPair()
125 constexpr Register AsRegisterPairLow() const { in AsRegisterPairLow() function
Dmanaged_register_arm_test.cc235 EXPECT_EQ(R0, reg.AsRegisterPairLow()); in TEST()
247 EXPECT_EQ(R1, reg.AsRegisterPairLow()); in TEST()
259 EXPECT_EQ(R2, reg.AsRegisterPairLow()); in TEST()
271 EXPECT_EQ(R4, reg.AsRegisterPairLow()); in TEST()
283 EXPECT_EQ(R6, reg.AsRegisterPairLow()); in TEST()
Djni_macro_assembler_arm_vixl.cc63 return vixl::aarch32::Register(reg.AsRegisterPairLow()); in AsVIXLRegisterPairLow()
500 DCHECK_LT(reg.AsRegisterPairLow(), reg.AsRegisterPairHigh()); in GetCoreRegisterMask()
501 return (1u << static_cast<size_t>(reg.AsRegisterPairLow())) | in GetCoreRegisterMask()
776 if (src.AsRegisterPairHigh() != dst.AsRegisterPairLow()) { in Move()
/art/compiler/utils/x86/
Dmanaged_register_x86.cc68 Register low = AsRegisterPairLow(); in Overlaps()
108 os << "Pair: " << AsRegisterPairLow() << ", " << AsRegisterPairHigh(); in Print()
Dmanaged_register_x86_test.cc124 EXPECT_EQ(EAX, reg.AsRegisterPairLow()); in TEST()
133 EXPECT_EQ(EAX, reg.AsRegisterPairLow()); in TEST()
142 EXPECT_EQ(EAX, reg.AsRegisterPairLow()); in TEST()
151 EXPECT_EQ(EAX, reg.AsRegisterPairLow()); in TEST()
160 EXPECT_EQ(EDX, reg.AsRegisterPairLow()); in TEST()
169 EXPECT_EQ(EDX, reg.AsRegisterPairLow()); in TEST()
178 EXPECT_EQ(EDX, reg.AsRegisterPairLow()); in TEST()
187 EXPECT_EQ(ECX, reg.AsRegisterPairLow()); in TEST()
196 EXPECT_EQ(ECX, reg.AsRegisterPairLow()); in TEST()
205 EXPECT_EQ(EBX, reg.AsRegisterPairLow()); in TEST()
Dmanaged_register_x86.h113 constexpr Register AsRegisterPairLow() const { in AsRegisterPairLow() function
Djni_macro_assembler_x86.cc143 __ movl(Address(ESP, offs), src.AsRegisterPairLow()); in Store()
202 __ movl(dest.AsRegisterPairLow(), Address(ESP, src)); in Load()
233 __ fs()->movl(dest.AsRegisterPairLow(), Address::Absolute(src)); in LoadFromThread()
/art/compiler/utils/x86_64/
Dmanaged_register_x86_64.cc63 Register low = AsRegisterPairLow().AsRegister(); in Overlaps()
103 os << "Pair: " << AsRegisterPairLow() << ", " << AsRegisterPairHigh(); in Print()
Dmanaged_register_x86_64_test.cc123 EXPECT_EQ(RAX, reg.AsRegisterPairLow()); in TEST()
132 EXPECT_EQ(RAX, reg.AsRegisterPairLow()); in TEST()
141 EXPECT_EQ(RAX, reg.AsRegisterPairLow()); in TEST()
150 EXPECT_EQ(RAX, reg.AsRegisterPairLow()); in TEST()
159 EXPECT_EQ(RDX, reg.AsRegisterPairLow()); in TEST()
168 EXPECT_EQ(RDX, reg.AsRegisterPairLow()); in TEST()
177 EXPECT_EQ(RDX, reg.AsRegisterPairLow()); in TEST()
186 EXPECT_EQ(RCX, reg.AsRegisterPairLow()); in TEST()
195 EXPECT_EQ(RCX, reg.AsRegisterPairLow()); in TEST()
204 EXPECT_EQ(RBX, reg.AsRegisterPairLow()); in TEST()
Dmanaged_register_x86_64.h106 constexpr CpuRegister AsRegisterPairLow() const { in AsRegisterPairLow() function
Djni_macro_assembler_x86_64.cc168 __ movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow()); in Store()
234 __ movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src)); in Load()
266 __ gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true)); in LoadFromThread()
/art/compiler/optimizing/
Dcode_generator_x86.cc1290 return Location::RegisterPairLocation(pair.AsRegisterPairLow(), pair.AsRegisterPairHigh()); in GetNextLocation()
1406 Location::RegisterLocation(source.AsRegisterPairLow<Register>()), in Move64()
1407 Location::RegisterLocation(destination.AsRegisterPairLow<Register>()), in Move64()
1411 __ movd(destination.AsRegisterPairLow<Register>(), src_reg); in Move64()
1417 __ movl(destination.AsRegisterPairLow<Register>(), Address(ESP, source.GetStackIndex())); in Move64()
1431 __ pushl(source.AsRegisterPairLow<Register>()); in Move64()
1443 __ movl(Address(ESP, destination.GetStackIndex()), source.AsRegisterPairLow<Register>()); in Move64()
1504 __ movd(dst.AsRegisterPairLow<Register>(), temp); in LoadFromMemoryNoBarrier()
1508 DCHECK_NE(src.GetBaseRegister(), dst.AsRegisterPairLow<Register>()); in LoadFromMemoryNoBarrier()
1510 __ movl(dst.AsRegisterPairLow<Register>(), src); in LoadFromMemoryNoBarrier()
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Dintrinsics_x86.cc198 __ movd(output.AsRegisterPairLow<Register>(), temp); in MoveFPToInt()
213 __ movd(temp1, input.AsRegisterPairLow<Register>()); in MoveIntToFP()
306 Register input_lo = input.AsRegisterPairLow<Register>(); in VisitLongReverseBytes()
309 Register output_lo = output.AsRegisterPairLow<Register>(); in VisitLongReverseBytes()
529 __ xorl(out_loc.AsRegisterPairLow<Register>(), out_loc.AsRegisterPairLow<Register>()); in GenLowestOneBit()
542 codegen->Load32BitValue(out_loc.AsRegisterPairLow<Register>(), 0); in GenLowestOneBit()
545 codegen->Load32BitValue(out_loc.AsRegisterPairLow<Register>(), 1 << value); in GenLowestOneBit()
556 Register src_lo = src.AsRegisterPairLow<Register>(); in GenLowestOneBit()
559 Register out_lo = out_loc.AsRegisterPairLow<Register>(); in GenLowestOneBit()
1475 Register address = locations->InAt(0).AsRegisterPairLow<Register>(); in GenPeek()
[all …]
Dcommon_arm.h52 return vixl::aarch32::Register(location.AsRegisterPairLow<vixl::aarch32::Register>()); in LowRegisterFrom()
Dlocations.h193 T AsRegisterPairLow() const { in AsRegisterPairLow() function
Dcode_generator_vector_x86.cc98 __ movd(dst, locations->InAt(0).AsRegisterPairLow<Register>()); in VisitVecReplicateScalar()
166 __ movd(locations->Out().AsRegisterPairLow<Register>(), src); in VisitVecExtractScalar()
1145 __ movd(dst, locations->InAt(0).AsRegisterPairLow<Register>()); in VisitVecSetScalars()
Dcode_generator.cc968 DCHECK(is_out || !blocked_core_registers_[location.AsRegisterPairLow<int>()]); in BlockIfInRegister()
969 blocked_core_registers_[location.AsRegisterPairLow<int>()] = true; in BlockIfInRegister()