1 /* 2 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer in the documentation and/or other materials provided 12 * with the distribution. 13 * * Neither the name of The Linux Foundation nor the names of its 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef __DRM_INTERFACE_H__ 31 #define __DRM_INTERFACE_H__ 32 33 #include <map> 34 #include <string> 35 #include <utility> 36 #include <vector> 37 #include <bitset> 38 39 #include "xf86drm.h" 40 #include "xf86drmMode.h" 41 #include <drm/msm_drm.h> 42 #include <drm/msm_drm_pp.h> 43 #include <drm/sde_drm.h> 44 45 namespace sde_drm { 46 47 typedef std::map<std::pair<uint32_t, uint64_t>, float> CompRatioMap; 48 49 /* 50 * Drm Atomic Operation Codes 51 */ 52 enum struct DRMOps { 53 /* 54 * Op: Sets plane source crop 55 * Arg: uint32_t - Plane ID 56 * DRMRect - Source Rectangle 57 */ 58 PLANE_SET_SRC_RECT, 59 /* 60 * Op: Sets plane destination rect 61 * Arg: uint32_t - Plane ID 62 * DRMRect - Dst Rectangle 63 */ 64 PLANE_SET_DST_RECT, 65 /* 66 * Op: Sets plane exclusion rect 67 * Arg: uint32_t - Plane ID 68 * drm_clip_rect - Exclusion Rectangle 69 */ 70 PLANE_SET_EXCL_RECT, 71 /* 72 * Op: Sets plane zorder 73 * Arg: uint32_t - Plane ID 74 * uint32_t - zorder 75 */ 76 PLANE_SET_ZORDER, 77 /* 78 * Op: Sets plane rotation flags 79 * Arg: uint32_t - Plane ID 80 * uint32_t - bit mask of rotation flags (See drm_mode.h for enums) 81 */ 82 PLANE_SET_ROTATION, 83 /* 84 * Op: Sets plane alpha 85 * Arg: uint32_t - Plane ID 86 * uint32_t - alpha value 87 */ 88 PLANE_SET_ALPHA, 89 /* 90 * Op: Sets the blend type 91 * Arg: uint32_t - Plane ID 92 * uint32_t - blend type (see DRMBlendType) 93 */ 94 PLANE_SET_BLEND_TYPE, 95 /* 96 * Op: Sets horizontal decimation 97 * Arg: uint32_t - Plane ID 98 * uint32_t - decimation factor 99 */ 100 PLANE_SET_H_DECIMATION, 101 /* 102 * Op: Sets vertical decimation 103 * Arg: uint32_t - Plane ID 104 * uint32_t - decimation factor 105 */ 106 PLANE_SET_V_DECIMATION, 107 /* 108 * Op: Sets source config flags 109 * Arg: uint32_t - Plane ID 110 * uint32_t - flags to enable or disable a specific op. E.g. deinterlacing 111 */ 112 PLANE_SET_SRC_CONFIG, 113 /* 114 * Op: Sets frame buffer ID for plane. Set together with CRTC. 115 * Arg: uint32_t - Plane ID 116 * uint32_t - Framebuffer ID 117 */ 118 PLANE_SET_FB_ID, 119 /* 120 * Op: Sets the crtc for this plane. Set together with FB_ID. 121 * Arg: uint32_t - Plane ID 122 * uint32_t - CRTC ID 123 */ 124 PLANE_SET_CRTC, 125 /* 126 * Op: Sets acquire fence for this plane's buffer. Set together with FB_ID, CRTC. 127 * Arg: uint32_t - Plane ID 128 * uint32_t - Input fence 129 */ 130 PLANE_SET_INPUT_FENCE, 131 /* 132 * Op: Sets scaler config on this plane. 133 * Arg: uint32_t - Plane ID 134 * uint64_t - Address of the scaler config object (version based) 135 */ 136 PLANE_SET_SCALER_CONFIG, 137 /* 138 * Op: Sets plane rotation destination rect 139 * Arg: uint32_t - Plane ID 140 * DRMRect - rotator dst Rectangle 141 */ 142 PLANE_SET_ROTATION_DST_RECT, 143 /* 144 * Op: Sets FB Secure mode for this plane. 145 * Arg: uint32_t - Plane ID 146 * uint32_t - Value of the FB Secure mode. 147 */ 148 PLANE_SET_FB_SECURE_MODE, 149 /* 150 * Op: Sets csc config on this plane. 151 * Arg: uint32_t - Plane ID 152 * uint32_t* - pointer to csc type 153 */ 154 PLANE_SET_CSC_CONFIG, 155 /* 156 * Op: Sets multirect mode on this plane. 157 * Arg: uint32_t - Plane ID 158 * uint32_t - multirect mode 159 */ 160 PLANE_SET_MULTIRECT_MODE, 161 /* 162 * Op: Sets rotator output frame buffer ID for plane. 163 * Arg: uint32_t - Plane ID 164 * uint32_t - Framebuffer ID 165 */ 166 PLANE_SET_ROT_FB_ID, 167 /* 168 * Op: Sets inverse pma mode on this plane. 169 * Arg: uint32_t - Plane ID 170 * uint32_t - enable/disable inverse pma. 171 */ 172 PLANE_SET_INVERSE_PMA, 173 /* 174 * Op: Sets csc config on this plane. 175 * Arg: uint32_t - Plane ID 176 * uint64_t - Address of the csc config object(version based) 177 */ 178 PLANE_SET_DGM_CSC_CONFIG, 179 /* 180 * Op: Sets SSPP Feature 181 * Arg: uint32_t - Plane ID 182 * DRMPPFeatureInfo * - PP feature data pointer 183 */ 184 PLANE_SET_POST_PROC, 185 /* 186 * Op: Activate or deactivate a CRTC 187 * Arg: uint32_t - CRTC ID 188 * uint32_t - 1 to enable, 0 to disable 189 */ 190 CRTC_SET_ACTIVE, 191 /* 192 * Op: Sets display mode 193 * Arg: uint32_t - CRTC ID 194 * drmModeModeInfo* - Pointer to display mode 195 */ 196 CRTC_SET_MODE, 197 /* 198 * Op: Sets an offset indicating when a release fence should be signalled. 199 * Arg: uint32_t - offset 200 * 0: non-speculative, default 201 * 1: speculative 202 */ 203 CRTC_SET_OUTPUT_FENCE_OFFSET, 204 /* 205 * Op: Sets overall SDE core clock 206 * Arg: uint32_t - CRTC ID 207 * uint32_t - core_clk 208 */ 209 CRTC_SET_CORE_CLK, 210 /* 211 * Op: Sets MNOC bus average bandwidth 212 * Arg: uint32_t - CRTC ID 213 * uint32_t - core_ab 214 */ 215 CRTC_SET_CORE_AB, 216 /* 217 * Op: Sets MNOC bus instantaneous bandwidth 218 * Arg: uint32_t - CRTC ID 219 * uint32_t - core_ib 220 */ 221 CRTC_SET_CORE_IB, 222 /* 223 * Op: Sets LLCC Bus average bandwidth 224 * Arg: uint32_t - CRTC ID 225 * uint32_t - llcc_ab 226 */ 227 CRTC_SET_LLCC_AB, 228 /* 229 * Op: Sets LLCC Bus instantaneous bandwidth 230 * Arg: uint32_t - CRTC ID 231 * uint32_t - llcc_ib 232 */ 233 CRTC_SET_LLCC_IB, 234 /* 235 * Op: Sets DRAM bus average bandwidth 236 * Arg: uint32_t - CRTC ID 237 * uint32_t - dram_ab 238 */ 239 CRTC_SET_DRAM_AB, 240 /* 241 * Op: Sets DRAM bus instantaneous bandwidth 242 * Arg: uint32_t - CRTC ID 243 * uint32_t - dram_ib 244 */ 245 CRTC_SET_DRAM_IB, 246 /* 247 * Op: Sets Rotator BW for inline rotation 248 * Arg: uint32_t - CRTC ID 249 * uint32_t - rot_bw 250 */ 251 CRTC_SET_ROT_PREFILL_BW, 252 /* 253 * Op: Sets rotator clock for inline rotation 254 * Arg: uint32_t - CRTC ID 255 * uint32_t - rot_clk 256 */ 257 CRTC_SET_ROT_CLK, 258 /* 259 * Op: Sets destination scalar data 260 * Arg: uint32_t - CRTC ID 261 * uint64_t - Pointer to destination scalar data 262 */ 263 CRTC_SET_DEST_SCALER_CONFIG, 264 /* 265 * Op: Returns release fence for this frame. Should be called after Commit() on 266 * DRMAtomicReqInterface. 267 * Arg: uint32_t - CRTC ID 268 * int * - Pointer to an integer that will hold the returned fence 269 */ 270 CRTC_GET_RELEASE_FENCE, 271 /* 272 * Op: Sets PP feature 273 * Arg: uint32_t - CRTC ID 274 * DRMPPFeatureInfo * - PP feature data pointer 275 */ 276 CRTC_SET_POST_PROC, 277 /* 278 * Op: Sets CRTC ROIs. 279 * Arg: uint32_t - CRTC ID 280 * uint32_t - number of ROIs 281 * DRMRect * - Array of CRTC ROIs 282 */ 283 CRTC_SET_ROI, 284 /* 285 * Op: Sets Security level for CRTC. 286 * Arg: uint32_t - CRTC ID 287 * uint32_t - Security level 288 */ 289 CRTC_SET_SECURITY_LEVEL, 290 /* 291 * Op: sets solid fill stages 292 * Arg: uint32_t - CRTC ID 293 * Vector of DRMSolidfillStage 294 */ 295 CRTC_SET_SOLIDFILL_STAGES, 296 /* 297 * Op: Sets idle timeout. 298 * Arg: uint32_t - CRTC ID 299 * uint32_t - idle timeout in ms 300 */ 301 CRTC_SET_IDLE_TIMEOUT, 302 /* 303 * Op: Sets Capture mode for Concurrent Writeback feature. 304 * Arg: uint32_t - CRTC ID 305 * uint32_t - Capture mode 306 */ 307 CRTC_SET_CAPTURE_MODE, 308 /* 309 * Op: Sets Idle PC state for CRTC. 310 * Arg: uint32_t - CRTC ID 311 * uint32_t - idle pc state 312 */ 313 CRTC_SET_IDLE_PC_STATE, 314 /* 315 * Op: Returns retire fence for this commit. Should be called after Commit() on 316 * DRMAtomicReqInterface. 317 * Arg: uint32_t - Connector ID 318 * int * - Pointer to an integer that will hold the returned fence 319 */ 320 CONNECTOR_GET_RETIRE_FENCE, 321 /* 322 * Op: Sets writeback connector destination rect 323 * Arg: uint32_t - Connector ID 324 * DRMRect - Dst Rectangle 325 */ 326 CONNECTOR_SET_OUTPUT_RECT, 327 /* 328 * Op: Sets frame buffer ID for writeback connector. 329 * Arg: uint32_t - Connector ID 330 * uint32_t - Framebuffer ID 331 */ 332 CONNECTOR_SET_OUTPUT_FB_ID, 333 /* 334 * Op: Sets power mode for connector. 335 * Arg: uint32_t - Connector ID 336 * uint32_t - Power Mode 337 */ 338 CONNECTOR_SET_POWER_MODE, 339 /* 340 * Op: Sets panel ROIs. 341 * Arg: uint32_t - Connector ID 342 * uint32_t - number of ROIs 343 * DRMRect * - Array of Connector ROIs 344 */ 345 CONNECTOR_SET_ROI, 346 /* 347 * Op: Sets the connector to autorefresh mode. 348 * Arg: uint32_t - Connector ID 349 * uint32_t - Enable-1, Disable-0 350 */ 351 CONNECTOR_SET_AUTOREFRESH, 352 /* 353 * Op: Set FB secure mode for Writeback connector. 354 * Arg: uint32_t - Connector ID 355 * uint32_t - FB Secure mode 356 */ 357 CONNECTOR_SET_FB_SECURE_MODE, 358 /* 359 * Op: Sets a crtc id to this connector 360 * Arg: uint32_t - Connector ID 361 * uint32_t - CRTC ID 362 */ 363 CONNECTOR_SET_CRTC, 364 /* 365 * Op: Sets PP feature 366 * Arg: uint32_t - Connector ID 367 * DRMPPFeatureInfo * - PP feature data pointer 368 */ 369 CONNECTOR_SET_POST_PROC, 370 /* 371 * Op: Sets connector hdr metadata 372 * Arg: uint32_t - Connector ID 373 * drm_msm_ext_hdr_metadata - hdr_metadata 374 */ 375 CONNECTOR_SET_HDR_METADATA, 376 /* 377 * Op: Cache Dpps features. 378 * Arg: uint32_t - Object ID 379 uint32_t - Feature ID 380 * uint64_t - Pointer to feature config data 381 */ 382 DPPS_CACHE_FEATURE, 383 /* 384 * Op: Commit Dpps features. 385 * Arg: drmModeAtomicReq - Atomic request 386 */ 387 DPPS_COMMIT_FEATURE, 388 /* 389 * Op: Sets qsync mode on connector 390 * Arg: uint32_t - Connector ID 391 * uint32_t - qsync mode 392 */ 393 CONNECTOR_SET_QSYNC_MODE, 394 /* 395 * Op: Sets topology control on this connector 396 * Arg: uint32_t - Connector ID 397 * uint32_t - Topology control bit-mask 398 */ 399 CONNECTOR_SET_TOPOLOGY_CONTROL, 400 }; 401 402 enum struct DRMRotation { 403 FLIP_H = 0x1, 404 FLIP_V = 0x2, 405 ROT_180 = FLIP_H | FLIP_V, 406 ROT_90 = 0x4, 407 }; 408 409 enum struct DRMPowerMode { 410 ON, 411 DOZE, 412 DOZE_SUSPEND, 413 OFF, 414 }; 415 416 enum struct DRMBlendType { 417 UNDEFINED = 0, 418 OPAQUE = 1, 419 PREMULTIPLIED = 2, 420 COVERAGE = 3, 421 }; 422 423 enum struct DRMSrcConfig { 424 DEINTERLACE = 0, 425 }; 426 427 enum struct DRMIdlePCState { 428 NONE, 429 ENABLE, 430 DISABLE, 431 }; 432 433 434 /* Display type to identify a suitable connector */ 435 enum struct DRMDisplayType { 436 PERIPHERAL, 437 TV, 438 VIRTUAL, 439 }; 440 441 struct DRMRect { 442 uint32_t left; // Left-most pixel coordinate. 443 uint32_t top; // Top-most pixel coordinate. 444 uint32_t right; // Right-most pixel coordinate. 445 uint32_t bottom; // Bottom-most pixel coordinate. 446 }; 447 448 //------------------------------------------------------------------------ 449 // DRM Info Query Types 450 //------------------------------------------------------------------------ 451 452 enum struct QSEEDVersion { 453 V1, 454 V2, 455 V3, 456 V3LITE, 457 }; 458 459 /* QSEED3 Step version */ 460 enum struct QSEEDStepVersion { 461 V2, 462 V3, 463 V4, 464 V3LITE_V4, 465 V3LITE_V5, 466 }; 467 468 enum struct SmartDMARevision { 469 V1, 470 V2, 471 V2p5 472 }; 473 474 /* Inline Rotation version */ 475 enum struct InlineRotationVersion { 476 UNKNOWN, 477 V1, 478 V1p1, // Rotator FB ID needs to be set 479 }; 480 481 /* Per CRTC Resource Info*/ 482 struct DRMCrtcInfo { 483 bool has_src_split; 484 bool has_hdr; 485 uint32_t max_blend_stages; 486 uint32_t max_solidfill_stages; 487 QSEEDVersion qseed_version; 488 SmartDMARevision smart_dma_rev; 489 float ib_fudge_factor; 490 float clk_fudge_factor; 491 uint32_t dest_scale_prefill_lines; 492 uint32_t undersized_prefill_lines; 493 uint32_t macrotile_prefill_lines; 494 uint32_t nv12_prefill_lines; 495 uint32_t linear_prefill_lines; 496 uint32_t downscale_prefill_lines; 497 uint32_t extra_prefill_lines; 498 uint32_t amortized_threshold; 499 uint64_t max_bandwidth_low; 500 uint64_t max_bandwidth_high; 501 uint32_t max_sde_clk; 502 CompRatioMap comp_ratio_rt_map; 503 CompRatioMap comp_ratio_nrt_map; 504 uint32_t hw_version; 505 uint32_t dest_scaler_count = 0; 506 uint32_t max_dest_scaler_input_width = 0; 507 uint32_t max_dest_scaler_output_width = 0; 508 uint32_t max_dest_scale_up = 1; 509 uint32_t min_prefill_lines = 0; 510 int secure_disp_blend_stage = -1; 511 bool concurrent_writeback = false; 512 uint32_t num_mnocports = 0; 513 uint32_t mnoc_bus_width = 0; 514 bool use_baselayer_for_stage = false; 515 uint32_t vig_limit_index = 0; 516 uint32_t dma_limit_index = 0; 517 uint32_t scaling_limit_index = 0; 518 uint32_t rotation_limit_index = 0; 519 uint32_t line_width_constraints_count = 0; 520 std::vector< std::pair <uint32_t, uint32_t> > line_width_limits; 521 float vbif_cmd_ff = 0.0f; 522 }; 523 524 enum struct DRMPlaneType { 525 // Has CSC and scaling capability 526 VIG = 0, 527 // Has scaling capability but no CSC 528 RGB, 529 // No scaling support 530 DMA, 531 // Supports a small dimension and doesn't use a CRTC stage 532 CURSOR, 533 MAX, 534 }; 535 536 enum struct DRMTonemapLutType { 537 DMA_1D_GC, 538 DMA_1D_IGC, 539 VIG_1D_IGC, 540 VIG_3D_GAMUT, 541 }; 542 543 struct DRMPlaneTypeInfo { 544 DRMPlaneType type; 545 uint32_t master_plane_id; 546 // FourCC format enum and modifier 547 std::vector<std::pair<uint32_t, uint64_t>> formats_supported; 548 uint32_t max_linewidth; 549 uint32_t max_scaler_linewidth; 550 uint32_t max_upscale; 551 uint32_t max_downscale; 552 uint32_t max_horizontal_deci; 553 uint32_t max_vertical_deci; 554 uint64_t max_pipe_bandwidth; 555 uint32_t cache_size; // cache size in bytes for inline rotation support. 556 bool has_excl_rect = false; 557 QSEEDStepVersion qseed3_version; 558 bool multirect_prop_present = false; 559 InlineRotationVersion inrot_version; // inline rotation version 560 bool inverse_pma = false; 561 uint32_t dgm_csc_version = 0; // csc used with DMA 562 std::map<DRMTonemapLutType, uint32_t> tonemap_lut_version_map = {}; 563 bool block_sec_ui = false; 564 // Allow all planes to be usable on all displays by default 565 std::bitset<32> hw_block_mask = std::bitset<32>().set(); 566 }; 567 568 // All DRM Planes as map<Plane_id , plane_type_info> listed from highest to lowest priority 569 typedef std::vector<std::pair<uint32_t, DRMPlaneTypeInfo>> DRMPlanesInfo; 570 571 enum struct DRMTopology { 572 UNKNOWN, // To be compat with driver defs in sde_rm.h 573 SINGLE_LM, 574 SINGLE_LM_DSC, 575 DUAL_LM, 576 DUAL_LM_DSC, 577 DUAL_LM_MERGE, 578 DUAL_LM_MERGE_DSC, 579 DUAL_LM_DSCMERGE, 580 PPSPLIT, 581 }; 582 583 enum struct DRMPanelMode { 584 VIDEO, 585 COMMAND, 586 }; 587 588 /* Per mode info */ 589 struct DRMModeInfo { 590 drmModeModeInfo mode; 591 DRMTopology topology; 592 // Valid only if mode is command 593 int num_roi; 594 int xstart; 595 int ystart; 596 int walign; 597 int halign; 598 int wmin; 599 int hmin; 600 bool roi_merge; 601 uint64_t bit_clk_rate; 602 uint32_t transfer_time_us; 603 }; 604 605 /* Per Connector Info*/ 606 struct DRMConnectorInfo { 607 uint32_t mmWidth; 608 uint32_t mmHeight; 609 uint32_t type; 610 uint32_t type_id; 611 std::vector<DRMModeInfo> modes; 612 std::string panel_name; 613 DRMPanelMode panel_mode; 614 bool is_primary; 615 // Valid only if DRMPanelMode is VIDEO 616 bool dynamic_fps; 617 // FourCC format enum and modifier 618 std::vector<std::pair<uint32_t, uint64_t>> formats_supported; 619 // Valid only if type is DRM_MODE_CONNECTOR_VIRTUAL 620 uint32_t max_linewidth; 621 DRMRotation panel_orientation; 622 drm_panel_hdr_properties panel_hdr_prop; 623 drm_msm_ext_hdr_properties ext_hdr_prop; 624 bool qsync_support; 625 // Connection status of this connector 626 bool is_connected; 627 bool is_wb_ubwc_supported; 628 uint32_t topology_control; 629 bool dyn_bitclk_support; 630 std::vector<uint8_t> edid; 631 }; 632 633 // All DRM Connectors as map<Connector_id , connector_info> 634 typedef std::map<uint32_t, DRMConnectorInfo> DRMConnectorsInfo; 635 636 /* Per Encoder Info */ 637 struct DRMEncoderInfo { 638 uint32_t type; 639 }; 640 641 // All DRM Encoders as map<Encoder_id , encoder_info> 642 typedef std::map<uint32_t, DRMEncoderInfo> DRMEncodersInfo; 643 644 /* Identifier token for a display */ 645 struct DRMDisplayToken { 646 uint32_t conn_id; 647 uint32_t crtc_id; 648 uint32_t crtc_index; 649 uint32_t encoder_id; 650 uint8_t hw_port; 651 }; 652 653 enum DRMPPFeatureID { 654 kFeaturePcc, 655 kFeatureIgc, 656 kFeaturePgc, 657 kFeatureMixerGc, 658 kFeaturePaV2, 659 kFeatureDither, 660 kFeatureGamut, 661 kFeaturePADither, 662 kFeaturePAHsic, 663 kFeaturePASixZone, 664 kFeaturePAMemColSkin, 665 kFeaturePAMemColSky, 666 kFeaturePAMemColFoliage, 667 kFeaturePAMemColProt, 668 kFeatureDgmIgc, 669 kFeatureDgmGc, 670 kFeatureVigIgc, 671 kFeatureVigGamut, 672 kPPFeaturesMax, 673 }; 674 675 enum DRMPPPropType { 676 kPropEnum, 677 kPropRange, 678 kPropBlob, 679 kPropTypeMax, 680 }; 681 682 struct DRMPPFeatureInfo { 683 DRMPPFeatureID id; 684 DRMPPPropType type; 685 uint32_t version; 686 uint32_t payload_size; 687 void *payload; 688 uint32_t object_type; 689 }; 690 691 enum DRMDPPSFeatureID { 692 // Ad4 properties 693 kFeatureAd4Mode, 694 kFeatureAd4Init, 695 kFeatureAd4Cfg, 696 kFeatureAd4Input, 697 kFeatureAd4Roi, 698 kFeatureAd4Backlight, 699 kFeatureAd4Assertiveness, 700 kFeatureAd4ManualStrength, 701 // ABA properties 702 kFeatureAbaHistCtrl, 703 kFeatureAbaHistIRQ, 704 kFeatureAbaLut, 705 // BL scale properties 706 kFeatureAd4BlScale, 707 kFeatureBacklightScale, 708 // Events 709 kFeaturePowerEvent, 710 kFeatureAbaHistEvent, 711 kFeatureBackLightEvent, 712 kFeatureAdAttBlEvent, 713 // Insert features above 714 kDppsFeaturesMax, 715 }; 716 717 struct DppsFeaturePayload { 718 uint32_t object_type; 719 uint32_t feature_id; 720 uint64_t value; 721 }; 722 723 struct DRMDppsFeatureInfo { 724 DRMDPPSFeatureID id; 725 uint32_t version; 726 }; 727 728 enum AD4Modes { 729 kAd4Off, 730 kAd4AutoStrength, 731 kAd4Calibration, 732 kAd4Manual, 733 kAd4ModeMax, 734 }; 735 736 enum HistModes { 737 kHistDisabled, 738 kHistEnabled, 739 }; 740 741 struct DRMDppsEventInfo { 742 uint32_t object_type; 743 uint32_t event_type; 744 int drm_fd; 745 bool enable; 746 }; 747 748 enum DRMCscType { 749 kCscYuv2Rgb601L, 750 kCscYuv2Rgb601FR, 751 kCscYuv2Rgb709L, 752 kCscYuv2Rgb2020L, 753 kCscYuv2Rgb2020FR, 754 kCscTypeMax, 755 }; 756 757 struct DRMScalerLUTInfo { 758 uint32_t dir_lut_size = 0; 759 uint32_t cir_lut_size = 0; 760 uint32_t sep_lut_size = 0; 761 uint64_t dir_lut = 0; 762 uint64_t cir_lut = 0; 763 uint64_t sep_lut = 0; 764 }; 765 766 enum struct DRMSecureMode { 767 NON_SECURE, 768 SECURE, 769 NON_SECURE_DIR_TRANSLATION, 770 SECURE_DIR_TRANSLATION, 771 }; 772 773 enum struct DRMSecurityLevel { 774 SECURE_NON_SECURE, 775 SECURE_ONLY, 776 }; 777 778 enum struct DRMMultiRectMode { 779 NONE = 0, 780 PARALLEL = 1, 781 SERIAL = 2, 782 }; 783 784 enum struct DRMCWbCaptureMode { 785 MIXER_OUT = 0, 786 DSPP_OUT = 1, 787 }; 788 789 enum struct DRMQsyncMode { 790 NONE = 0, 791 CONTINUOUS, 792 ONESHOT, 793 }; 794 795 enum struct DRMTopologyControl { 796 NONE = 0, 797 RESERVE_LOCK = 1 << 0, 798 RESERVE_CLEAR = 1 << 1, 799 DSPP = 1 << 2, 800 DEST_SCALER = 1 << 3, 801 }; 802 803 struct DRMSolidfillStage { 804 DRMRect bounding_rect {}; 805 bool is_exclusion_rect = false; 806 uint32_t color = 0xff000000; // in 8bit argb 807 uint32_t red = 0; 808 uint32_t blue = 0; 809 uint32_t green = 0; 810 uint32_t alpha = 0xff; 811 uint32_t color_bit_depth = 0; 812 uint32_t z_order = 0; 813 uint32_t plane_alpha = 0xff; 814 }; 815 816 /* DRM Atomic Request Property Set. 817 * 818 * Helper class to create and populate atomic properties of DRM components 819 * when rendered in DRM atomic mode */ 820 class DRMAtomicReqInterface { 821 public: ~DRMAtomicReqInterface()822 virtual ~DRMAtomicReqInterface() {} 823 /* Perform request operation. 824 * 825 * [input]: opcode: operation code from DRMOps list. 826 * obj_id: Relevant crtc, connector, plane id 827 * var_arg: arguments for DRMOps's can differ in number and 828 * data type. Refer above DRMOps to details. 829 * [return]: Error code if the API fails, 0 on success. 830 */ 831 virtual int Perform(DRMOps opcode, uint32_t obj_id, ...) = 0; 832 833 /* 834 * Commit the params set via Perform(). Also resets the properties after commit. Needs to be 835 * called every frame. 836 * [input]: synchronous: Determines if the call should block until a h/w flip 837 * [input]: retain_planes: Retains already staged planes. Useful when not explicitly programming 838 * planes but still need the previously staged ones to not be unstaged 839 * [return]: Error code if the API fails, 0 on success. 840 */ 841 virtual int Commit(bool synchronous, bool retain_planes) = 0; 842 843 /* 844 * Validate the params set via Perform(). 845 * [return]: Error code if the API fails, 0 on success. 846 */ 847 virtual int Validate() = 0; 848 }; 849 850 class DRMManagerInterface; 851 852 /* Populates a singleton instance of DRMManager */ 853 typedef int (*GetDRMManager)(int fd, DRMManagerInterface **intf); 854 855 /* Destroy DRMManager instance */ 856 typedef int (*DestroyDRMManager)(); 857 858 /* 859 * DRM Manager Interface - Any class which plans to implement helper function for vendor 860 * specific DRM driver implementation must implement the below interface routines to work 861 * with SDM. 862 */ 863 864 class DRMManagerInterface { 865 public: ~DRMManagerInterface()866 virtual ~DRMManagerInterface() {} 867 868 /* 869 * Since SDM completely manages the planes. GetPlanesInfo will provide all 870 * the plane information. 871 * [output]: DRMPlanesInfo: Resource Info for planes. 872 */ 873 virtual void GetPlanesInfo(DRMPlanesInfo *info) = 0; 874 875 /* 876 * Will provide all the information of a selected crtc. 877 * [input]: Use crtc id 0 to obtain system wide info 878 * [output]: DRMCrtcInfo: Resource Info for the given CRTC id. 879 * [return]: 0 on success, a negative error value otherwise. 880 */ 881 virtual int GetCrtcInfo(uint32_t crtc_id, DRMCrtcInfo *info) = 0; 882 883 /* 884 * Will provide all the information of a selected connector. 885 * [output]: DRMConnectorInfo: Resource Info for the given connector id 886 * [return]: 0 on success, a negative error value otherwise. 887 */ 888 virtual int GetConnectorInfo(uint32_t conn_id, DRMConnectorInfo *info) = 0; 889 890 /* 891 * Provides information on all connectors. 892 * [output]: DRMConnectorsInfo: Resource info for connectors. 893 * [return]: 0 on success, a negative error value otherwise. 894 */ 895 virtual int GetConnectorsInfo(DRMConnectorsInfo *info) = 0; 896 897 /* 898 * Provides information on a selected encoder. 899 * [output]: DRMEncoderInfo: Resource info for the given encoder id. 900 * [return]: 0 on success, a negative error value otherwise. 901 */ 902 virtual int GetEncoderInfo(uint32_t encoder_id, DRMEncoderInfo *info) = 0; 903 904 /* 905 * Provides information on all encoders. 906 * [output]: DRMEncodersInfo: Resource info for encoders. 907 * [return]: 0 on success, a negative error value otherwise. 908 */ 909 virtual int GetEncodersInfo(DRMEncodersInfo *info) = 0; 910 911 /* 912 * Will query post propcessing feature info of a CRTC. 913 * [output]: DRMPPFeatureInfo: CRTC post processing feature info 914 */ 915 virtual void GetCrtcPPInfo(uint32_t crtc_id, DRMPPFeatureInfo *info) = 0; 916 917 /* 918 * Register a logical display to receive a token. 919 * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect 920 * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the 921 * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here 922 * onwards, Client should use this token to represent the display for any Perform operations if 923 * needed. 924 * 925 * [input]: disp_type - Peripheral / TV / Virtual 926 * [output]: DRMDisplayToken - CRTC and Connector IDs for the display. 927 * [return]: 0 on success, a negative error value otherwise. 928 */ 929 virtual int RegisterDisplay(DRMDisplayType disp_type, DRMDisplayToken *tok) = 0; 930 931 /* 932 * Register a logical display to receive a token. 933 * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect 934 * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the 935 * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here 936 * onwards, Client should use this token to represent the display for any Perform operations if 937 * needed. 938 * 939 * [input]: display_id - Connector ID 940 * [output]: DRMDisplayToken - CRTC and Connector id's for the display. 941 * [return]: 0 on success, a negative error value otherwise. 942 */ 943 virtual int RegisterDisplay(int32_t display_id, DRMDisplayToken *token) = 0; 944 945 /* Client should invoke this interface on display disconnect. 946 * [input]: DRMDisplayToken - identifier for the display. 947 */ 948 virtual void UnregisterDisplay(DRMDisplayToken *token) = 0; 949 950 /* 951 * Creates and returns an instance of DRMAtomicReqInterface corresponding to a display token 952 * returned as part of RegisterDisplay API. Needs to be called per display. 953 * [input]: DRMDisplayToken that identifies a display pipeline 954 * [output]: Pointer to an instance of DRMAtomicReqInterface. 955 * [return]: Error code if the API fails, 0 on success. 956 */ 957 virtual int CreateAtomicReq(const DRMDisplayToken &token, DRMAtomicReqInterface **intf) = 0; 958 959 /* 960 * Destroys the instance of DRMAtomicReqInterface 961 * [input]: Pointer to a DRMAtomicReqInterface 962 * [return]: Error code if the API fails, 0 on success. 963 */ 964 virtual int DestroyAtomicReq(DRMAtomicReqInterface *intf) = 0; 965 966 /* 967 * Sets the global scaler LUT 968 * [input]: LUT Info 969 * [return]: Error code if the API fails, 0 on success. 970 */ 971 virtual int SetScalerLUT(const DRMScalerLUTInfo &lut_info) = 0; 972 973 /* 974 * Unsets the global scaler LUT 975 * [input]: None 976 * [return]: Error code if the API fails, 0 on success. 977 */ 978 virtual int UnsetScalerLUT() = 0; 979 980 /* 981 * Get the DPPS feature info 982 * [input]: Dpps feature id, info->id 983 * [output]: Dpps feature version, info->version 984 */ 985 virtual void GetDppsFeatureInfo(DRMDppsFeatureInfo *info) = 0; 986 }; 987 988 } // namespace sde_drm 989 #endif // __DRM_INTERFACE_H__ 990