Lines Matching refs:Zero
73 if (rd != Zero && rd != SP && IsImmCLuiEncodable(imm20)) { in Lui()
90 if (rd == Zero && IsInt<12>(offset)) { in Jal()
102 if (rd == RA && rs1 != Zero && offset == 0) { in Jalr()
105 } else if (rd == Zero && rs1 != Zero && offset == 0) { in Jalr()
118 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Beq()
121 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Beq()
132 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Bne()
135 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Bne()
184 if (rd != Zero && rs1 == SP && IsUint<8>(offset) && IsAligned<4>(offset)) { in Lw()
200 if (rd != Zero && rs1 == SP && IsUint<9>(offset) && IsAligned<8>(offset)) { in Ld()
307 if (rd != Zero) { in Addi()
308 if (rs1 == Zero && IsInt<6>(imm12)) { in Addi()
326 } else if (rs1 != Zero) { in Addi()
378 if (rd == rs1 && rd != Zero && shamt != 0) { in Slli()
419 if (rd != Zero) { in Add()
420 if (rs1 != Zero || rs2 != Zero) { in Add()
421 if (rs1 == Zero) { in Add()
422 DCHECK_NE(rs2, Zero); in Add()
425 } else if (rs2 == Zero) { in Add()
426 DCHECK_NE(rs1, Zero); in Add()
430 DCHECK_NE(rs2, Zero); in Add()
434 DCHECK_NE(rs1, Zero); in Add()
535 if (rd != Zero && IsInt<6>(imm12)) { in Addiw()
539 } else if (rs1 == Zero) { in Addiw()
1249 DCHECK_NE(rd, Zero); in CLwsp()
1255 DCHECK_NE(rd, Zero); in CLdsp()
1315 DCHECK_NE(rd, Zero); in CLi()
1322 DCHECK_NE(rd, Zero); in CLui()
1330 DCHECK_NE(rd, Zero); in CAddi()
1337 DCHECK_NE(rd, Zero); in CAddiw()
1378 DCHECK_NE(rd, Zero); in CSlli()
1404 DCHECK_NE(rd, Zero); in CMv()
1405 DCHECK_NE(rs2, Zero); in CMv()
1411 DCHECK_NE(rd, Zero); in CAdd()
1412 DCHECK_NE(rs2, Zero); in CAdd()
1521 DCHECK_NE(rs1, Zero); in CJr()
1522 EmitCR(0b1000u, rs1, Zero, 0b10u); in CJr()
1527 DCHECK_NE(rs1, Zero); in CJalr()
1528 EmitCR(0b1001u, rs1, Zero, 0b10u); in CJalr()
1543 EmitCR(0b1001u, Zero, Zero, 0b10u); in CEbreak()
1548 EmitCI(0b000u, Zero, 0u, 0b01u); in CNop()
3841 void Riscv64Assembler::VNeg_v(VRegister vd, VRegister vs2) { VRsub_vx(vd, vs2, Zero); } in VNeg_v()
4584 VNsrl_wx(vd, vs2, Zero, vm); in VNcvt_x_x_w()
5033 VWaddu_vx(vd, vs, Zero, vm); in VWcvtu_x_x_v()
5054 VWadd_vx(vd, vs, Zero, vm); in VWcvt_x_x_v()
6113 void Riscv64Assembler::Nop() { Addi(Zero, Zero, 0); } in Nop()
6123 void Riscv64Assembler::Neg(XRegister rd, XRegister rs) { Sub(rd, Zero, rs); } in Neg()
6125 void Riscv64Assembler::NegW(XRegister rd, XRegister rs) { Subw(rd, Zero, rs); } in NegW()
6154 if (IsExtensionEnabled(Riscv64Extension::kZca) && rd != Zero && (rd == rs || rs == Zero)) { in SextW()
6191 AddUw(rd, rs, Zero); in ZextW()
6201 void Riscv64Assembler::Snez(XRegister rd, XRegister rs) { Sltu(rd, Zero, rs); } in Snez()
6203 void Riscv64Assembler::Sltz(XRegister rd, XRegister rs) { Slt(rd, rs, Zero); } in Sltz()
6205 void Riscv64Assembler::Sgtz(XRegister rd, XRegister rs) { Slt(rd, Zero, rs); } in Sgtz()
6220 Beq(rs, Zero, offset); in Beqz()
6224 Bne(rs, Zero, offset); in Bnez()
6228 Bge(Zero, rt, offset); in Blez()
6232 Bge(rt, Zero, offset); in Bgez()
6236 Blt(rt, Zero, offset); in Bltz()
6240 Blt(Zero, rt, offset); in Bgtz()
6259 void Riscv64Assembler::J(int32_t offset) { Jal(Zero, offset); } in J()
6263 void Riscv64Assembler::Jr(XRegister rs) { Jalr(Zero, rs, 0); } in Jr()
6269 void Riscv64Assembler::Ret() { Jalr(Zero, RA, 0); } in Ret()
6272 Csrrs(rd, 0xc00, Zero); in RdCycle()
6276 Csrrs(rd, 0xc01, Zero); in RdTime()
6280 Csrrs(rd, 0xc02, Zero); in RdInstret()
6284 Csrrs(rd, csr, Zero); in Csrr()
6288 Csrrw(Zero, csr, rs); in Csrw()
6292 Csrrs(Zero, csr, rs); in Csrs()
6296 Csrrc(Zero, csr, rs); in Csrc()
6300 Csrrwi(Zero, csr, uimm5); in Csrwi()
6304 Csrrsi(Zero, csr, uimm5); in Csrsi()
6308 Csrrci(Zero, csr, uimm5); in Csrci()
6445 Beq(rs, Zero, label, is_bare); in Beqz()
6449 Bne(rs, Zero, label, is_bare); in Bnez()
6453 Ble(rs, Zero, label, is_bare); in Blez()
6457 Bge(rs, Zero, label, is_bare); in Bgez()
6461 Blt(rs, Zero, label, is_bare); in Bltz()
6465 Bgt(rs, Zero, label, is_bare); in Bgtz()
6513 Jal(Zero, label, is_bare); in J()
6743 rhs_reg_(Zero), in Branch()
6748 InitializeType((rd != Zero ? in Branch()
6788 rhs_reg_(Zero), in Branch()
6793 CHECK_NE(rd , Zero); in Branch()
6804 lhs_reg_(Zero), in Branch()
6805 rhs_reg_(Zero), in Branch()
6855 DCHECK(GetLeftRegister() == Zero || GetRightRegister() == Zero) in GetNonZeroRegister()
6857 DCHECK(GetLeftRegister() != Zero || GetRightRegister() != Zero) in GetNonZeroRegister()
6859 return GetLeftRegister() == Zero ? GetRightRegister() : GetLeftRegister(); in GetNonZeroRegister()
6897 ((lhs_reg_ == Zero && IsShortReg(rhs_reg_)) || (rhs_reg_ == Zero && IsShortReg(lhs_reg_))); in IsCompressableCondition()
7123 DCHECK(lhs != Zero); in EmitBranch()
7154 emit_auipc_and_next(TMP, [&](int32_t short_offset) { Jalr(Zero, TMP, short_offset); }); in EmitBranch()
7157 DCHECK(lhs != Zero); in EmitBranch()
7234 Buncond(label, Zero, is_bare); in Bcond()
7303 DCHECK_NE(rd, Zero); in LoadLabelAddress()
7657 addi(rd, Zero, value); in LoadImmediate()
7660 addi(rd, Zero, value >> CTZ(value)); in LoadImmediate()
7689 emit_simple_li_helper(Zero, value, count_rri, count_rri, count_rri, count_ru); in LoadImmediate()
7743 emit_with_slli_addi_helper(Zero, value, count_rri, count_rri, count_rri, count_ru); in LoadImmediate()
7766 Addi(rd, Zero, -1); in LoadImmediate()
7793 Addi(rd, Zero, value >> ctz); in LoadImmediate()