305 void Riscv64Assembler::Addi(XRegister rd, XRegister rs1, int32_t imm12) {  in Addi()  argument
308       if (rs1 == Zero && IsInt<6>(imm12)) {  in Addi()
309         CLi(rd, imm12);  in Addi()
311       } else if (imm12 != 0) {  in Addi()
315           if (IsInt<6>(imm12)) {  in Addi()
316             CAddi(rd, imm12);  in Addi()
318           } else if (rd == SP && IsInt<10>(imm12) && IsAligned<16>(imm12)) {  in Addi()
319             CAddi16Sp(imm12);  in Addi()
322         } else if (IsShortReg(rd) && rs1 == SP && IsUint<10>(imm12) && IsAligned<4>(imm12)) {  in Addi()
323           CAddi4Spn(rd, imm12);  in Addi()
330     } else if (rd == rs1 && imm12 == 0) {  in Addi()
336   EmitI(imm12, rs1, 0x0, rd, 0x13);  in Addi()
339 void Riscv64Assembler::Slti(XRegister rd, XRegister rs1, int32_t imm12) {  in Slti()  argument
340   EmitI(imm12, rs1, 0x2, rd, 0x13);  in Slti()
343 void Riscv64Assembler::Sltiu(XRegister rd, XRegister rs1, int32_t imm12) {  in Sltiu()  argument
344   EmitI(imm12, rs1, 0x3, rd, 0x13);  in Sltiu()
347 void Riscv64Assembler::Xori(XRegister rd, XRegister rs1, int32_t imm12) {  in Xori()  argument
349     if (rd == rs1 && IsShortReg(rd) && imm12 == -1) {  in Xori()
355   EmitI(imm12, rs1, 0x4, rd, 0x13);  in Xori()
358 void Riscv64Assembler::Ori(XRegister rd, XRegister rs1, int32_t imm12) {  in Ori()  argument
359   EmitI(imm12, rs1, 0x6, rd, 0x13);  in Ori()
362 void Riscv64Assembler::Andi(XRegister rd, XRegister rs1, int32_t imm12) {  in Andi()  argument
364     if (rd == rs1 && IsShortReg(rd) && IsInt<6>(imm12)) {  in Andi()
365       CAndi(rd, imm12);  in Andi()
370   EmitI(imm12, rs1, 0x7, rd, 0x13);  in Andi()
533 void Riscv64Assembler::Addiw(XRegister rd, XRegister rs1, int32_t imm12) {  in Addiw()  argument
535     if (rd != Zero && IsInt<6>(imm12)) {  in Addiw()
537         CAddiw(rd, imm12);  in Addiw()
540         CLi(rd, imm12);  in Addiw()
546   EmitI(imm12, rs1, 0x0, rd, 0x1b);  in Addiw()