Lines Matching refs:imm12
289 void Addi(XRegister rd, XRegister rs1, int32_t imm12);
290 void Slti(XRegister rd, XRegister rs1, int32_t imm12);
291 void Sltiu(XRegister rd, XRegister rs1, int32_t imm12);
292 void Xori(XRegister rd, XRegister rs1, int32_t imm12);
293 void Ori(XRegister rd, XRegister rs1, int32_t imm12);
294 void Andi(XRegister rd, XRegister rs1, int32_t imm12);
312 void Addiw(XRegister rd, XRegister rs1, int32_t imm12);
2332 void EmitI(int32_t imm12, Reg1 rs1, uint32_t funct3, Reg2 rd, uint32_t opcode) { in EmitI() argument
2333 DCHECK(IsInt<12>(imm12)) << imm12; in EmitI()
2338 uint32_t encoding = static_cast<uint32_t>(imm12) << 20 | static_cast<uint32_t>(rs1) << 15 | in EmitI()
2396 void EmitS(int32_t imm12, Reg1 rs2, Reg2 rs1, uint32_t funct3, uint32_t opcode) { in EmitS() argument
2397 DCHECK(IsInt<12>(imm12)) << imm12; in EmitS()
2402 uint32_t encoding = (static_cast<uint32_t>(imm12) & 0xFE0) << 20 | in EmitS()
2405 (static_cast<uint32_t>(imm12) & 0x1F) << 7 | opcode; in EmitS()
2448 uint32_t imm12 = (static_cast<uint32_t>(offset) >> 1) & 0xfffu; in EmitB() local
2449 uint32_t encoding = (imm12 & 0x800u) << (31 - 11) | (imm12 & 0x03f0u) << (25 - 4) | in EmitB()
2452 (imm12 & 0xfu) << 8 | (imm12 & 0x400u) >> (10 - 7) | opcode; in EmitB()