Lines Matching refs:Beq
539 __ Beq(rs, rt, label, is_bare); in EmitBcondForAllConditions() local
670 __ Beq(A0, A1, &labels[i]); in TestBeqA0A1MaybeCascade() local
2335 &Riscv64Assembler::Beq, /*imm_bits=*/-12, /*shift=*/1, "beq {reg1}, {reg2}, {imm}\n"), in TEST_F()
2343 &Riscv64Assembler::Beq, /*imm_bits=*/-11, /*shift=*/2, "beq {reg1}, {reg2}, {imm}\n"), in TEST_F()
8562 &Riscv64Assembler::Beq, in TEST_F()
8571 &Riscv64Assembler::Beq, in TEST_F()
8599 &Riscv64Assembler::Beq, in TEST_F()
8609 &Riscv64Assembler::Beq, in TEST_F()
8619 &Riscv64Assembler::Beq, in TEST_F()
8628 &Riscv64Assembler::Beq, in TEST_F()
8656 &Riscv64Assembler::Beq, in TEST_F()
8666 &Riscv64Assembler::Beq, in TEST_F()
8676 &Riscv64Assembler::Beq, in TEST_F()
8685 &Riscv64Assembler::Beq, in TEST_F()
8695 &Riscv64Assembler::Beq, in TEST_F()
8705 &Riscv64Assembler::Beq, in TEST_F()
8715 &Riscv64Assembler::Beq, in TEST_F()
8725 &Riscv64Assembler::Beq, in TEST_F()
8734 &Riscv64Assembler::Beq, in TEST_F()
8753 &Riscv64Assembler::Beq, in TEST_F()
8763 &Riscv64Assembler::Beq, in TEST_F()
8772 &Riscv64Assembler::Beq, in TEST_F()
8837 __ Beq(reg, reg, &label); in TEST_F() local