Lines Matching refs:lsl

177     add     \reg, xIBASE, \reg, lsl #${handler_size_bits}
211     and     \scaled_vreg, \scaled_mask_reg, \src_reg, lsl #(2 - \lsb)
220     lsl     wip2, \vreg, #2
228     lsl     wip2, \vreg, #2
399     lsl x14, x14, #2
408     add \refs, x14, ip2, lsl #2
411     add \fp, \refs, ip, lsl #2
647    add ip2, xREFS, x3, lsl #2  // pointer to first argument in reference array
648    add ip2, ip2, x2, lsl #2    // pointer to last argument in reference array
649    add x5, xFP, x3, lsl #2     // pointer to first argument in register array
650    add x6, x5, x2, lsl #2      // pointer to last argument in register array
776     add ip, ip, ip2, lsl #32
835     add \gpr_reg64, ip, ip2, lsl #32
1256      ldr wip, [x8, ip2, lsl #2]
1257      str wip, [x9, ip2, lsl #2]
1654     lsl x27, ip2, #2 // x27 is now the offset for inputs into the registers array.
1740    add      ip, ip, ip2, lsl #4            // entry address within the cache