Lines Matching refs:t1
15 FETCH t1, count=1 // t1 := CC|BB
17 srliw t2, t1, 8 // t2 := CC
18 andi t1, t1, 0xFF // t1 := BB
23 fle.${precision} t1, ft2, ft1
25 addi t1, t1, -1
26 add t2, t2, t1
36 FETCH t1, count=1 // t1 := CC|BB
38 srliw t2, t1, 8 // t2 := CC
39 andi t1, t1, 0xFF // t1 := BB
44 fle.${precision} t1, ft1, ft2
46 xori t1, t1, 1
47 sub t2, t1, t2
174 % get_vreg("t1", "t0") # t1 := fp[B]
176 GET_VREG_WIDE t1, t0 // t1 := fp[B]
188 fclass.${src} t1, ft0 // fclass.s or fclass.d on the source register ft0
189 sltiu t1, t1, 0x100 // t1 := 0 if NaN, per dex spec. Skip the conversion.
190 beqz t1, 1f
197 % set_vreg("t1", "t2", z0="t0") # fp[A] := t1
199 SET_VREG_WIDE t1, t2, z0=t0 // fp[A] := t1
283 srliw t1, t0, 8 // t1 := CC
368 srliw t1, xINST, 12 // t1 := B
378 GET_INST_OPCODE t1 // t1 holds next opcode
381 GOTO_OPCODE t1 // continue to next