Lines Matching refs:reg
147 .macro TEST_IF_MARKING reg, label
148 lb \reg, THREAD_IS_GC_MARKING_OFFSET(xSELF)
149 bnez \reg, \label
172 .macro FETCH reg, count, signed=0, width=16, byte=0
175 lb \reg, (\count*2 + \byte)(xPC)
177 lbu \reg, (\count*2 + \byte)(xPC)
181 lh \reg, (\count*2)(xPC)
183 lhu \reg, (\count*2)(xPC)
187 lw \reg, (\count*2)(xPC)
189 lwu \reg, (\count*2)(xPC)
192 ld \reg, (\count*2)(xPC)
216 .macro GET_INST_OPCODE reg argument
217 and \reg, xINST, 0xFF
221 .macro GOTO_OPCODE reg argument
222 slliw \reg, \reg, ${handler_size_bits}
223 add \reg, xIBASE, \reg
224 jr \reg
227 .macro FETCH_FROM_THREAD_CACHE reg, miss_label, z0, z1
248 ld \reg, 8(\z0) // value: depends on context; see call site
323 .macro GET_VREG_WIDE reg, vreg
324 sh2add \reg, \vreg, xFP // vreg addr in register array
325 ld \reg, (\reg) // reg := fp[vreg](lo) | fp[vreg+1](hi)
330 .macro SET_VREG_WIDE reg, vreg, z0
332 sd \reg, (\z0) // fp[vreg] := reg(lo) ; fp[vreg+1] := reg(hi)
340 .macro GET_VREG_OBJECT reg, vreg
341 sh2add \reg, \vreg, xREFS // vreg addr in reference array
342 lwu \reg, (\reg) // reg := refs[vreg]
347 .macro SET_VREG_OBJECT reg, vreg, z0
349 sw \reg, (\z0) // fp[vreg] := reg
351 sw \reg, (\z0) // refs[vreg] := reg
356 .macro GET_VREG_DOUBLE reg, vreg
358 fld \reg, (\vreg) // reg := fp[vreg](lo) | fp[vreg+1](hi)
363 .macro SET_VREG_DOUBLE reg, vreg, z0
365 fsd \reg, (\z0) // fp[vreg] := reg(lo) ; fp[vreg+1] := reg(hi)
376 %def get_vreg(reg, vreg, width=32, is_wide=False, is_unsigned=False):
378 GET_VREG_WIDE $reg, $vreg
380 sh2add $reg, $vreg, xFP // vreg addr in register array
381 lwu $reg, ($reg) // reg := fp[vreg], zext
383 sh2add $reg, $vreg, xFP // vreg addr in register array
384 lw $reg, ($reg) // reg := fp[vreg]
390 %def set_vreg(reg, vreg, z0, width=32, is_wide=False):
392 SET_VREG_WIDE $reg, $vreg, $z0
395 sw $reg, ($z0) // fp[vreg] := reg
402 %def get_vreg_float(reg, vreg, is_double=False):
404 GET_VREG_DOUBLE $reg, $vreg
407 flw $reg, ($vreg) // reg := fp[vreg]
412 %def set_vreg_float(reg, vreg, z0, is_double=False):
414 SET_VREG_DOUBLE $reg, $vreg, $z0
417 fsw $reg, ($z0) // fp[vreg] := reg