Lines Matching refs:frm
1488 return OpVectorWidenv<[](int8_t frm, SIMD128Register src) { in OpVector()
1489 return intrinsics::Vfcvtv<WideElementType, UnsignedType>(FPFlags::DYN, frm, src); in OpVector()
1497 return OpVectorWidenv<[](int8_t frm, SIMD128Register src) { in OpVector()
1498 return intrinsics::Vfcvtv<WideElementType, SignedType>(FPFlags::DYN, frm, src); in OpVector()
1506 return OpVectorNarroww<[](int8_t frm, SIMD128Register src) { in OpVector()
1507 return intrinsics::Vfcvtv<UnsignedType, WideElementType>(FPFlags::DYN, frm, src); in OpVector()
1515 return OpVectorNarroww<[](int8_t frm, SIMD128Register src) { in OpVector()
1516 return intrinsics::Vfcvtv<SignedType, WideElementType>(FPFlags::DYN, frm, src); in OpVector()
1524 return OpVectorNarroww<[](int8_t frm, SIMD128Register src) { in OpVector()
1525 return intrinsics::Vfcvtv<UnsignedType, WideElementType>(FPFlags::RTZ, frm, src); in OpVector()
1533 return OpVectorNarroww<[](int8_t frm, SIMD128Register src) { in OpVector()
1534 return intrinsics::Vfcvtv<SignedType, WideElementType>(FPFlags::RTZ, frm, src); in OpVector()
1624 return OpVectorWidenv<[](int8_t frm, SIMD128Register src) { in OpVector()
1625 return intrinsics::Vfcvtv<WideUnsignedType, ElementType>(FPFlags::DYN, frm, src); in OpVector()
1633 return OpVectorWidenv<[](int8_t frm, SIMD128Register src) { in OpVector()
1634 return intrinsics::Vfcvtv<WideSignedType, ElementType>(FPFlags::DYN, frm, src); in OpVector()
1642 return OpVectorWidenv<[](int8_t frm, SIMD128Register src) { in OpVector()
1643 return intrinsics::Vfcvtv<WideElementType, ElementType>(FPFlags::DYN, frm, src); in OpVector()
1651 return OpVectorWidenv<[](int8_t frm, SIMD128Register src) { in OpVector()
1652 return intrinsics::Vfcvtv<WideUnsignedType, ElementType>(FPFlags::RTZ, frm, src); in OpVector()
1660 return OpVectorWidenv<[](int8_t frm, SIMD128Register src) { in OpVector()
1661 return intrinsics::Vfcvtv<WideSignedType, ElementType>(FPFlags::RTZ, frm, src); in OpVector()
1669 return OpVectorNarroww<[](int8_t frm, SIMD128Register src) { in OpVector()
1670 return intrinsics::Vfcvtv<ElementType, WideUnsignedType>(FPFlags::DYN, frm, src); in OpVector()
1678 return OpVectorNarroww<[](int8_t frm, SIMD128Register src) { in OpVector()
1679 return intrinsics::Vfcvtv<ElementType, WideElementType>(FPFlags::DYN, frm, src); in OpVector()
1687 return OpVectorNarroww<[](int8_t frm, SIMD128Register src) { in OpVector()
1688 return intrinsics::Vfcvtv<ElementType, WideSignedType>(FPFlags::DYN, frm, src); in OpVector()
1787 return OpVectorv<[](int8_t frm, SIMD128Register src) { in OpVector()
1788 return intrinsics::Vfcvtv<UnsignedType, ElementType>(FPFlags::DYN, frm, src); in OpVector()
1796 return OpVectorv<[](int8_t frm, SIMD128Register src) { in OpVector()
1797 return intrinsics::Vfcvtv<SignedType, ElementType>(FPFlags::DYN, frm, src); in OpVector()
1805 return OpVectorv<[](int8_t frm, SIMD128Register src) { in OpVector()
1806 return intrinsics::Vfcvtv<ElementType, UnsignedType>(FPFlags::DYN, frm, src); in OpVector()
1814 return OpVectorv<[](int8_t frm, SIMD128Register src) { in OpVector()
1815 return intrinsics::Vfcvtv<ElementType, SignedType>(FPFlags::DYN, frm, src); in OpVector()
1823 return OpVectorv<[](int8_t frm, SIMD128Register src) { in OpVector()
1824 return intrinsics::Vfcvtv<UnsignedType, ElementType>(FPFlags::RTZ, frm, src); in OpVector()
1832 return OpVectorv<[](int8_t frm, SIMD128Register src) { in OpVector()
1833 return intrinsics::Vfcvtv<SignedType, ElementType>(FPFlags::RTZ, frm, src); in OpVector()
4422 return FeGetExceptions() | (state_->cpu.frm << 5);
4464 state_->cpu.frm = arg;