Lines Matching refs:AddProperty
557 AddProperty(DRMProperty::MODE_ID, blob_id, true); in Perform()
564 AddProperty(DRMProperty::OUTPUT_FENCE_OFFSET, offset); in Perform()
569 AddProperty(DRMProperty::CORE_CLK, core_clk); in Perform()
574 AddProperty(DRMProperty::CORE_AB, core_ab); in Perform()
579 AddProperty(DRMProperty::CORE_IB, core_ib); in Perform()
584 AddProperty(DRMProperty::LLCC_AB, llcc_ab); in Perform()
589 AddProperty(DRMProperty::LLCC_IB, llcc_ib); in Perform()
594 AddProperty(DRMProperty::DRAM_AB, dram_ab); in Perform()
599 AddProperty(DRMProperty::DRAM_IB, dram_ib); in Perform()
604 AddProperty(DRMProperty::ROT_PREFILL_BW, rot_bw); in Perform()
609 AddProperty(DRMProperty::ROT_CLK, rot_clk); in Perform()
615 AddProperty(DRMProperty::OUTPUT_FENCE, in Perform()
621 AddProperty(DRMProperty::ACTIVE, enable); in Perform()
647 AddProperty(DRMProperty::SECURITY_LEVEL, crtc_security_level); in Perform()
659 AddProperty(DRMProperty::IDLE_TIME, timeout_ms); in Perform()
668 AddProperty(DRMProperty::DEST_SCALER, in Perform()
678 AddProperty(DRMProperty::CAPTURE_MODE, cwb_capture_mode); in Perform()
698 AddProperty(DRMProperty::IDLE_PC_STATE, idle_pc_state); in Perform()
714 AddProperty(DRMProperty::ROI_V1, 0, true); in SetROI()
730 AddProperty(DRMProperty::ROI_V1, reinterpret_cast<uint64_t>(&roi_v1_), true); in SetROI()
762 AddProperty(DRMProperty::DIM_STAGES_V1, in SetSolidfillStages()
778 AddProperty(DRMProperty::DS_LUT_ED, dir_lut_blob_id, true); in ConfigureScalerLUT()
781 AddProperty(DRMProperty::DS_LUT_CIR, cir_lut_blob_id, true); in ConfigureScalerLUT()
784 AddProperty(DRMProperty::DS_LUT_SEP, sep_lut_blob_id, true); in ConfigureScalerLUT()