Lines Matching refs:set
22 .set .SZ_1K, 1024
23 .set .SZ_4K, 4 * .SZ_1K
24 .set .SZ_1M, 1024 * .SZ_1K
25 .set .SZ_2M, 2 * .SZ_1M
26 .set .SZ_1G, 1024 * .SZ_1M
28 .set .PAGE_SIZE, .SZ_4K
30 .set .ORIGIN_ADDR, 2 * .SZ_1G
31 .set .DTB_ADDR, .ORIGIN_ADDR + (0 * .SZ_2M)
32 .set .TEXT_ADDR, .ORIGIN_ADDR + (1 * .SZ_2M)
33 .set .DATA_ADDR, .ORIGIN_ADDR + (2 * .SZ_2M)
35 .set .L_TT_TYPE_BLOCK, 0x1
36 .set .L_TT_TYPE_PAGE, 0x3
37 .set .L_TT_TYPE_TABLE, 0x3
39 .set .L_TT_AF, 0x1 << 10 // Access flag
40 .set .L_TT_NG, 0x1 << 11 // Not global
41 .set .L_TT_RO, 0x2 << 6
42 .set .L_TT_XN, 0x3 << 53
44 .set .L_TT_MT_DEV, 0x0 << 2 // MAIR #0 (DEV_nGnRE)
45 .set .L_TT_MT_MEM, (0x1 << 2) | (0x3 << 8) // MAIR #1 (MEM_WBWA), inner shareable
47 .set .L_BLOCK_RO, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_RO | .L_TT_XN
48 .set .L_BLOCK_DEV, .L_TT_TYPE_BLOCK | .L_TT_MT_DEV | .L_TT_AF | .L_TT_XN
49 .set .L_BLOCK_MEM, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_XN | .L_TT_NG
50 .set .L_BLOCK_MEM_XIP, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_NG | .L_TT_RO