ELF>@@*(FFFFFF""""FFFw  2(3(4(5(6(7(8(9(deo,^{Z]&'`()*^+,-_./@1F2G3H4I5JXYZ][Y\Z^[_\uzy{vx~ !LMLMN ~:;@,*mnopqrl.kxy~z{|}~stf-jhigl0~6, 7- 8* 9. :/ C-;=$!}"NOq;< =!>"?/@5A6B70; 1: 2< 36 47 58 64 99 A B C = @ D E    MUX_APM_FUNCGATE_DFTMUX_CMU_CIS_CLK2GATE_DFTMUX_CMU_CIS_CLK5UMUX_CLKCMU_NOCL2AA_NOCUMUX_CLKCMU_G2D_JPEGGATE_PCIE_GEN3A_1_PCS_APBUMUX_CLKCMU_RGBP_MCFPzuma_clock0x%08llx 3error writing to pad_clkout0 err=%lu 3Failed to register clock %s GATE_PCIE_GEN3A_1_APBGATE_PCIE_GEN3B_1_DBGGATE_PCIE_GEN3B_1_AXIUMUX_MIF_DDRPHY2XDOUT_CLK_DPUF0_NOCPMUX_NOCL1B_NOC_OPTION1UMUX_CLKCMU_DPUF1_NOCMUX_HSI0_USB32DRDUMUX_CLKCMU_HSI1_NOCGATE_UFS_EMBDUMUX_CLKCMU_YUVPGATE_PERIC1_TOP0_USI15_USIDOUT_CLK_NOCL1B_NOCPCLKOUT0UMUX_CLKCMU_EH_NOCGATE_MMC_CARDGATE_WDT_CL1GATE_PERIC0_TOP0_USI4_USIDOUT_CLK_APM_BOOSTVDOUT_CLK_PERIC0_USI0_UARTVDOUT_CLK_PERIC1_USI13_USIVDOUT_CLK_PERIC1_USI15_USI%s: failed to map registers 6ZUMA: Clock setup completed 3[CAL] vclk enable failed %d %d GATE_PDMA1ATCLKUMUX_CLKCMU_PERIC0_NOCDOUT_CLK_G2D_NOCPVDOUT_CLK_HSI0_USI3_USIzuma_clock_probeGATE_DFTMUX_CMU_CIS_CLK6UMUX_CLKCMU_NOCL1B_NOCUMUX_CLKCMU_NOCL2AB_NOCGATE_HSI0_USI2_USIUMUX_CLKCMU_TNR_MERGEUMUX_CLKCMU_GDC_GDC0DOUT_CLK_APM_USI0_USIVDOUT_CLK_HSI0_USI2_USIVDOUT_CLK_TOP_HSI0_NOCDOUT_CLK_RGBP_NOCPDOUT_CLK_GDC_NOCPVDOUT_CLK_PERIC1_USI0_USIGATE_HSI0_USI0_USIGATE_PERIC0_TOP0_USI2_USIclock-frequency3Failed to disable clock %s UMUX_CLKCMU_HSI0_TCXOMUX_HSI0_USB20_REFUMUX_CLKCMU_HSI0_ALTMUX_HSI0_NOCUMUX_CLKCMU_TPU_TPUVDOUT_CLK_HSI0_USI0_USIVDOUT_CLK_HSI0_USI4_USIVDOUT_CLK_PERIC1_USI9_USI3[CAL] Failed to set vclk rate %d %lu %d GATE_DFTMUX_CMU_CIS_CLK1UMUX_CLKCMU_RGBP_RGBPUMUX_CLKCMU_TNR_ALIGN0x%16llx UMUX_CLKCMU_HSI2_NOCUMUX_CLKCMU_MCSCMUX_TPU_TPUDOUT_CLK_DPUB_NOCPVDOUT_CLK_PERIC0_USI4_USIUMUX_CLKCMU_HSI0_NOCGATE_HSI0_USI1_USIGATE_PCIE_GEN3A_1_AXIDOUT_CLK_GSE_NOCPDOUT_CLK_MFC_NOCP3Failed to allocate for gate_clk fin_pllGATE_MFCGATE_PERIC0_TOP0_USI5_USIGATE_PERIC0_TOP0_USI6_USIUMUX_CLKCMU_HSI0_DPOSC_USERDOUT_CLK_MCSC_NOCPCIS_CLK1CIS_CLK7VDOUT_CLK_PERIC0_USI14_USIVDOUT_CLK_PERIC1_USI10_USIDOUT_CLK_TPU_NOCPcould not register clk provider GATE_HSI0_USI3_USIGATE_PERIC0_TOP0_USI1_USIDOUT_CLK_NOCL2AB_NOCPUMUX_CLKCMU_HSI2_PCIEGATE_PCIE_GEN3B_1_APBUMUX_CLKCMU_MFC_MFCUMUX_CLKCMU_MISC_SCVDOUT_CLK_PERIC0_USI3_USIpwm-clockpad_clkout0pad_clkout1clkout_addr3Failed to enable clock %s 3Failed to allocate vclk struct UMUX_CLKCMU_NOCL1_NOCGATE_PCIE_GEN3_0_PMA_APBGATE_PCIE_GEN3A_1_PMA_APBGATE_PCIE_GEN3B_1_PCS_APBUMUX_CLKCMU_TPU_NOCDOUT_CLK_TPU_TPUcould not allocate clock lookup table 3Failed to get clk by register offset GATE_DFTMUX_CMU_CIS_CLK0UMUX_CLKCMU_DPUF0_NOCUMUX_CLKCMU_HSI1_PCIEGATE_PCIE_GEN3_0_APBGATE_PCIE_GEN3_0_PCS_APBUMUX_CLKCMU_GSEDOUT_CLK_MISC_NOCPGATE_PERIC1_TOP0_USI9_USIDOUT_CLK_EH_NOCPDOUT_CLK_DPUF1_NOCPCIS_CLK0GATE_G2DGATE_JPEGGATE_PCIE_GEN3_0_AXIGATE_PCIE_GEN3A_1_DBGDOUT_CLK_NOCL2AA_NOCPDOUT_CLKCMU_HSI2_MMC_CARDUMUX_CLKCMU_G2D_G2DUMUX_CLKCMU_HSI0_USB32DRDUMUX_CLKCMU_HSI2_UFS_EMBDGATE_UFS_EMBD_FMPUMUX_CLKCMU_GDC_LMEGATE_MCTVDOUT_CLK_HSI0_USI1_USI3Failed to register lookup %s GATE_DPUBGATE_USB32DRD_LINKGATE_PDMA0DOUT_CLK_HSI0_USB32DRDVDOUT_CLK_PERIC1_USI11_USIDOUT_CLK_BW_NOCPxclkoutcould not allocate clock provider context. 3[CAL] vclk disable failed %d %d GATE_DFTMUX_CMU_CIS_CLK7UMUX_CLKCMU_PERIC0_USI0_UARTCLKOUT1GATE_DFTMUX_CMU_CIS_CLK3UMUX_CLKCMU_NOCL0_NOCCIS_CLK5VDOUT_CLK_PERIC0_USI5_USI3error writing to pad_clkout1 err=%lu UMUX_CLKCMU_HSI0_USB20GATE_PERIC1_TOP0_USI12_USICIS_CLK2CIS_CLK3VDOUT_CLK_PERIC1_USI12_USIGATE_PERIC0_TOP0_USI14_USIMUX_TPU_TPUCTLDOUT_CLK_ISPFE_NOCP3Failed to register clock lookup for %sGATE_PCIE_GEN3_0_UDBGUMUX_CLKCMU_TPU_TPUCTLCIS_CLK4VDOUT_CLK_PERIC0_USI6_USIclkout_valUMUX_CLKCMU_HSI2_MMC_CARDUMUX_CLKCMU_ISPFEGATE_PERIC0_TOP0_USI3_USIGATE_PERIC0_TOP1_USI0_UARTGATE_PERIC1_TOP0_USI10_USIDOUT_CLK_APM_USI0_UARTVDOUT_CLK_PERIC0_USI2_USIGATE_DFTMUX_CMU_CIS_CLK4GATE_GPUGATE_PCIE_GEN3B_1_PMA_APBDOUT_CLK_NOCL1A_NOCP3error address not found 3Failed to register virtual clock %s MUX_APM_FUNCSRCDOUT_CLK_TNR_NOCPVDOUT_CLK_PERIC0_USI1_USI%s: unable to determine soc 3can not alloc for gate clock list UMUX_CLKCMU_MISC_NOCGATE_WDT_CL0GATE_PERIC1_TOP0_USI13_USI3can not alloc for enable gate clock list 3[CAL] Failed to set vclk dfs %d %lu %d 3[CAL] Failed to set vclk dfs rate switch UMUX_CLKCMU_DPUB_NOCUMUX_CLKCMU_HSI0_DPGTCUMUX_CLKCMU_PERIC1_NOCGATE_PERIC1_TOP0_USI11_USIUMUX_CLKCMU_BW_NOCCIS_CLK6DOUT_CLK_TPU_TPUCTL3could not allocate usermux clk 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