ELF( @@42 ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;;; ;;;;; ;;;;;; ;;;;; ;;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;;    ; ;;;;; ;;;;;; ;;;;; ;;;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;;; ;;;;; ;;;;; ;;;;; ;;;;;;; ;;;;; ;;;;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;; ;;;;;; ;;;;; ;;;;;;;;;;;***;*****  ***;*****  ;;;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;  g    5 a G       $ ($$,((\XX`\\d``hddlhhplltppxttxx||   $(  ,$$p 00   @  @@  "$$ $$$((<@@@DDDHHHLL  00 088,<<0@@4DD8HH<LL@PPD``T xxxx "%s", REC->dw_name "%s, return: %d", REC->dw_name, REC->ret "%s, return: %d, value: 0x%x", REC->dw_name, REC->ret, REC->val "%s, return: %d, value: 0x%llx", REC->dw_name, REC->ret, REC->val "%s, flags: %s, skb->len: %d", REC->dw_name, __print_flags(REC->flags, "|", { MCPS802154_TX_FRAME_CONFIG_TIMESTAMP_DTU, "TIMESTAMP_DTU" }, { MCPS802154_TX_FRAME_CONFIG_CCA, "CCA" }, { MCPS802154_TX_FRAME_CONFIG_RANGING, "RANGING" }, { MCPS802154_TX_FRAME_CONFIG_KEEP_RANGING_CLOCK, "KEEP_RANGING_CLOCK" }, { MCPS802154_TX_FRAME_CONFIG_SP3, "SP3" }, { MCPS802154_TX_FRAME_CONFIG_SP2, "SP2" }, { MCPS802154_TX_FRAME_CONFIG_SP1, "SP1" }, { MCPS802154_TX_FRAME_CONFIG_STS_MODE_MASK, "STS_MODE_MASK" }),REC->len "%s, cannot program delayed, tx_date_dtu: 0x%x, cur_time_dtu: 0x%x", REC->dw_name, REC->tx_date_dtu, REC->cur_time_dtu "%s, flags: %s, timeout: %d", REC->dw_name, __print_flags(REC->flags, "|", { MCPS802154_RX_FRAME_CONFIG_TIMESTAMP_DTU, "TIMESTAMP_DTU" }, { MCPS802154_RX_FRAME_CONFIG_AACK, "AACK" }, { MCPS802154_RX_FRAME_CONFIG_RANGING, "RANGING" }, { MCPS802154_RX_FRAME_CONFIG_KEEP_RANGING_CLOCK, "KEEP_RANGING_CLOCK" }, { MCPS802154_RX_FRAME_CONFIG_RANGING_PDOA, "RANGING_PDOA" }, { MCPS802154_RX_FRAME_CONFIG_SP3, "SP3" }, { MCPS802154_RX_FRAME_CONFIG_SP2, "SP2" }, { MCPS802154_RX_FRAME_CONFIG_SP1, "SP1" }, { MCPS802154_RX_FRAME_CONFIG_STS_MODE_MASK, "STS_MODE_MASK" }), REC->timeout "%s, too late to program delayed, rx_date_dtu: 0x%x, current_dtu: 0x%x", REC->dw_name, REC->rx_date_dtu, REC->cur_time_dtu "%s, flags: %s", REC->dw_name, __print_flags(REC->flags, "|", { MCPS802154_RX_FRAME_INFO_TIMESTAMP_DTU, "TIMESTAMP_DTU" }, { MCPS802154_RX_FRAME_INFO_TIMESTAMP_RCTU, "TIMESTAMP_RCTU" }, { MCPS802154_RX_FRAME_INFO_LQI, "LQI" }, { MCPS802154_RX_FRAME_INFO_RSSI, "RSSI" }, { MCPS802154_RX_FRAME_INFO_RANGING_FOM, "RANGING_FOM" }, { MCPS802154_RX_FRAME_INFO_RANGING_OFFSET, "RANGING_OFFSET" }, { MCPS802154_RX_FRAME_INFO_RANGING_PDOA, "RANGING_PDOA" }, { MCPS802154_RX_FRAME_INFO_RANGING_PDOA_FOM, "RANGING_PDOA_FOM" }, { MCPS802154_RX_FRAME_INFO_RANGING_STS_TIMESTAMP_RCTU, "RANGING_STS_TIMESTAMP_RCTU" }, { MCPS802154_RX_FRAME_INFO_RANGING_STS_FOM, "RANGING_STS_FOM" }, { MCPS802154_RX_FRAME_INFO_AACK, "AACK" }) "%s, flags: %s", REC->dw_name, __print_flags(REC->flags, "|", { MCPS802154_RX_FRAME_INFO_TIMESTAMP_DTU, "TIMESTAMP_DTU" }, { MCPS802154_RX_FRAME_INFO_TIMESTAMP_RCTU, "TIMESTAMP_RCTU" }, { MCPS802154_RX_FRAME_INFO_LQI, "LQI" }, { MCPS802154_RX_FRAME_INFO_RSSI, "RSSI" }, { MCPS802154_RX_FRAME_INFO_RANGING_FOM, "RANGING_FOM" }, { MCPS802154_RX_FRAME_INFO_RANGING_OFFSET, "RANGING_OFFSET" }, { MCPS802154_RX_FRAME_INFO_RANGING_PDOA, "RANGING_PDOA" }, { MCPS802154_RX_FRAME_INFO_RANGING_PDOA_FOM, "RANGING_PDOA_FOM" }, { MCPS802154_RX_FRAME_INFO_RANGING_STS_TIMESTAMP_RCTU, "RANGING_STS_TIMESTAMP_RCTU" }, { MCPS802154_RX_FRAME_INFO_RANGING_STS_FOM, "RANGING_STS_FOM" }, { MCPS802154_RX_FRAME_INFO_AACK, "AACK" }) "%s, timeout: %s, timeout_dtu: 0x%0x, next_operational_state: %s", REC->dw_name, REC->timeout ? "true" : "false", REC->timeout_dtu, __print_symbolic(REC->next_operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, page: %u, channel: %u, preamble_code: %u", REC->dw_name, REC->page, REC->channel, REC->pcode "%s, changed: 0x%x", REC->dw_name, REC->changed "%s, n_segs: %u", REC->dw_name, REC->n_segs "%s, rmarker_dtu: 0x%x", REC->dw_name, REC->rmarker_dtu "%s, rmarker_rctu: 0x%llx", REC->dw_name, REC->rmarker_rctu "%s, rmarker_dtu: 0x%x, ts_rctu: 0x%llx, rmarker_rctu: 0x%llx", REC->dw_name, REC->rmarker_dtu, REC->ts_rctu, REC->rmarker_rctu "%s, ts_dtu: 0x%x, ant_offset: 0x%x, rmarker_rctu: 0x%llx", REC->dw_name, REC->ts_dtu, REC->ant_offset, REC->rmarker_rctu "%s, status: %s", REC->dw_name, __print_flags(REC->status, "|", { (u64)(0x20000UL) << 32, "RXSTS" }, { (u64)(0x10000UL) << 32, "TXSTS" }, { (u64)(0x8000U) << 32, "SEMA_ERR" }, { (u64)(0x4000U) << 32, "COEX_CLR" }, { (u64)(0x2000U) << 32, "COEX_ERR" }, { (u64)(0x1000U) << 32, "CCA_FAIL" }, { (u64)(0x800U) << 32, "SPIERR" }, { (u64)(0x400U) << 32, "SPI_UNF" }, { (u64)(0x200U) << 32, "SPI_OVF" }, { (u64)(0x100U) << 32, "CMD_ERR" }, { (u64)(0x80U) << 32, "AES_ERR" }, { (u64)(0x40U) << 32, "AES_DONE" }, { (u64)(0x20U) << 32, "GPIO_IRQ" }, { (u64)(0x10U) << 32, "VT_DET" }, { (u64)(0x4U) << 32, "PGFCAL_ERR" }, { (u64)(0x2U) << 32, "RXPREJ" }, { 0x80000000UL, "TIMER1" }, { 0x40000000UL, "TIMER0" }, { 0x20000000UL, "ARFE" }, { 0x10000000UL, "CPERR" }, { 0x8000000UL, "HPDWARN" }, { 0x4000000UL, "RXSTO" }, { 0x2000000UL, "PLL_HILO" }, { 0x1000000UL, "RCINIT" }, { 0x800000UL, "SPIRDY" }, { 0x400000UL, "LCSSERR" }, { 0x200000UL, "RXPTO" }, { 0x100000UL, "RXOVRR" }, { 0x80000UL, "VWARN" }, { 0x40000UL, "CIAERR" }, { 0x20000UL, "RXFTO" }, { 0x10000UL, "RXFSL" }, { 0x8000U, "RXFCE" }, { 0x4000U, "RXFCG" }, { 0x2000U, "RXFR" }, { 0x1000U, "RXPHE" }, { 0x800U, "RXPHD" }, { 0x400U, "CIA_DONE" }, { 0x200U, "RXSFDD" }, { 0x100U, "RXPRD" }, { 0x80U, "TXFRS" }, { 0x40U, "TXPHS" }, { 0x20U, "TXPRS" }, { 0x10U, "TXFRB" }, { 0x8U, "AAT" }, { 0x4U, "SPICRCERR" }, { 0x2U, "CLK_PLL_LOCK" }, { 0x1U, "IRQS" }) "%s, low_sys_status: 0x%08x", REC->dw_name, REC->low_sys_status "%s, operational_state: %s", REC->dw_name, __print_symbolic(REC->operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, operational_state: %s", REC->dw_name, __print_symbolic(REC->operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, delay_dtu: %d, current_operational_state: %s, next_operational_state: %s", REC->dw_name, REC->delay_dtu, __print_symbolic(REC->current_operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }), __print_symbolic(REC->next_operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, sys_time_sync: 0x%08x, dtu_sync: 0x%08x", REC->dw_name, REC->sys_time_sync, REC->dtu_sync "%s, result: %d", REC->dw_name, REC->result "%s, time_ns: %lld", REC->dw_name, REC->time_before "%s, delay: %dus", REC->dw_name, REC->delay_us "%s, sleep_us: %lld, sleep_enter_dtu: 0x%x, next_op_date: 0x%x, next_op: %s", REC->dw_name, REC->sleep_time_us, REC->sleep_enter_dtu, REC->dtu_next_op, __print_symbolic(REC->next_op, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, state: %s, boot_time_ns: %llu, len_or_date: %u", REC->dw_name, __print_symbolic(REC->state, { DW3000_PWR_OFF, "OFF" }, { DW3000_PWR_DEEPSLEEP, "DEEPSLEEP" }, { DW3000_PWR_RUN, "RUN" }, { DW3000_PWR_IDLE, "IDLE" }, { DW3000_PWR_RX, "RX" }, { DW3000_PWR_TX, "TX" }), REC->boot_time_ns, (unsigned)REC->len_or_date "%s, res: %d, xtrim: %d, bias: %d", REC->dw_name, REC->res, REC->value, REC->bias "%s, res: %d, gpio: %u, value: %u", REC->dw_name, REC->res, REC->gpio, REC->value "%s, utime: %llu, prf: %u, sts: %u", REC->dw_name, REC->utime, REC->prf, REC->stsMode "%s, ts: %llu, f1: %u, f2: %u, f3: %u, acc: %hu, fpidx: %hu, offset: %d, filter: 0x%x", REC->dw_name, REC->ts, REC->f1, REC->f2, REC->f3, REC->acc, REC->fpidx, REC->off, REC->filter "%s, current state: %s, new state: %s, delay_us: %d, expire: %u", REC->dw_name, REC->status ? "ON" : "OFF", REC->state ? "ON" : "OFF", REC->delay_us, (unsigned)REC->expire "%s, delay_us: %d, status: %s, coex_interval_us: %d", REC->dw_name, REC->delay_us, REC->status ? "ON" : "OFF", REC->coex_interval_us "%s, status: %s", REC->dw_name, REC->status ? "ON" : "OFF" "%s base pwr: 0x%08x, adjusted: 0x%08x (chan: %u,frm_dur: %u, PL_len: %u, th. boost: %u, applied boost: %u)", REC->dw_name, REC->base_power, REC->adjusted_power, REC->chan, REC->frm_dur, REC->pl_len, REC->th_boost, REC->app_boost "%s, chip: %s, sts: %u, cir_pwr: %u, pacc_cnt: %u, prf_64mhz: %u, dgc_dec: %u", REC->dw_name, REC->chip_name, REC->sts, REC->cir_pwr, REC->pacc_cnt, REC->prf_64mhz, REC->dgc_dec "%s, dss_stat: %s", REC->dw_name, __print_flags(REC->dss_stat, "|", { 0x1U, "SPI1_AVAIL" }, { 0x2U, "SPI2_AVAIL" }) "%s, ver_id: %u, seq_num: %u", REC->dw_name, REC->ver_id, REC->seq_num "%s, session_time0_sys_time: 0x%08x", REC->dw_name, REC->session_time0_sys_time "%s, clock_offset_sys_time: 0x%08x", REC->dw_name, REC->clock_offset_sys_time "%s, session_id %d", REC->dw_name, REC->session_id "%s, next_timestamp_dtu: 0x%08x, next_duration_dtu: 0x%08x", REC->dw_name, REC->next_timestamp_dtu, REC->next_duration_dtu "%s, signature: %s, ver_id: %u, seq_num: %u, nb_tlv: %u", REC->dw_name, __print_hex(REC->signature, 5), REC->ver_id, REC->seq_num, REC->nb_tlv "%s, type: %s, data: %s", REC->dw_name, __print_symbolic(REC->type, { DW3000_NFCC_COEX_TLV_TYPE_UNSPEC, "UNSPEC" }, { DW3000_NFCC_COEX_TLV_TYPE_SESSION_TIME0, "SESSION_TIME0" }, { DW3000_NFCC_COEX_TLV_TYPE_SLOT_LIST, "SLOT_LIST" }, { DW3000_NFCC_COEX_TLV_TYPE_TLV_UWBCNT_OFFS, "TLV_UWBCNT_OFFS" }, { DW3000_NFCC_COEX_TLV_TYPE_ERROR, "ERROR" }, { DW3000_NFCC_COEX_TLV_TYPE_SLOT_LIST_UUS, "SLOT_LIST_UUS" }), __print_hex(__get_dynamic_array(data), __get_dynamic_array_len(data)) "%s, start: %s, idle_duration_dtu: 0x%08x, timestamp_dtu: 0x%08x, duration_dtu: 0x%08x, chan: %d", REC->dw_name, REC->start ? "true" : "false", REC->idle_duration_dtu, REC->timestamp_dtu, REC->duration_dtu, REC->chan "%s, send: %s, idle_duration_dtu: %d, send_timestamp_dtu: 0x%08x", REC->dw_name, __print_symbolic(REC->send, { DW3000_NFCC_COEX_SEND_CLK_SYNC, "CLK_SYNC" }, { DW3000_NFCC_COEX_SEND_CLK_OFFSET, "CLK_OFFSET" }, { DW3000_NFCC_COEX_SEND_STOP, "STOP" }), REC->idle_duration_dtu, REC->send_timestamp_dtu "%s, err: "%s"", REC->dw_name, __get_str(err) "%s, warn: "%s"", REC->dw_name, __get_str(warn) "%s, channel: %d", REC->dw_name, REC->channel "%s, mode: %d", REC->dw_name, REC->mode "%s, pdoa: 0x%08x", REC->dw_name, REC->pdoa "%s, chan: %d, len: %d, rate: %d", REC->dw_name, REC->chan, REC->len, REC->rate "%s", REC->dw_name "%s, clockoffset: %d", REC->dw_name, REC->cfo "%s", REC->dw_name "%s", REC->dw_name  ))))))))))))))  dqq%ant0.ch9.prf16.pg_delayant0.ant1.ch5.pdoa_lutch9.wifi_coex-enabledAES RAMrx_sfdtypecould not request the IRQ %d: %d wificoex_gpiodevice configuration has failed (%d) regulator failed to set voltage :%d Allocation failed. Cannot open file. u32SP3%s, page: %u, channel: %u, preamble_code: %u statusTXFRSfpidx%s, session_id %d ant0.ant1.ch9.pdoa_lutsmart_tx_powerdigi_diag_clrdisableDW3000_NFCC_COEX_TLV_TYPE_TLV_UWBCNT_OFFSDW3000_DSS_STAT_SPI2_AVAIL_BIT_MASK%s, return: %d, value: 0x%llx SPI_OVFCMD_ERRvalueerrant3.ch9.prf16.pg_delayant1.ant3.ch9.pdoa_lutdw3000_pidTX_CALtx_pream_lendevice not in IDLE_RC state &stm->work_wqdbgfs: impossible to alloc buffers mem mask defined but modify not supported for this size DW3000_OP_STATE_IDLE_PLLTXsleep_enter_dtugpioprff2pl_lenstsu8[5]__data_loc u8[]ant2.ch5.prf64.ant_delaydevice LDO & bias tune setup has failed (%d) dw3000_isr_handle_spi_errorCOEX_CLRTIMER1CIAERRcoex_interval_us%s, delay_us: %d, status: %s, coex_interval_us: %d %s base pwr: 0x%08x, adjusted: 0x%08x (chan: %u,frm_dur: %u, PL_len: %u, th. boost: %u, applied boost: %u) cir_pwrant0.ch5.prf16.pg_countant1.selector_gpioant2.selector_gpioGEN_CFG1AONdevice XTRIM setup has failed (%d) cache missesantennas set id %d is out of range, max is %d A timer cmd is already queued, this cmd will be ignored unable to dump registers: device not ready buffer too smallinput format error (%d) DW3000_OP_STATE_INIT_RCDW3000_NFCC_COEX_TLV_TYPE_UNSPECflagsCCA%s, sys_time_sync: 0x%08x, dtu_sync: 0x%08x modeant0.ch5.prf64.ant_delayant0.ch5.prf64.pg_delayant0.selector_gpio_valueant1.ch5.prf64.pg_countant1.ch5.prf64.pg_delayant1.portant0.ant3.ch9.pdoa_lutGEN_CFG0frame_filter_cfgtx_pream_chuwbhal,reset-gpioLoading driver uwbm-4.5.0...wait device power on failed: %d device present using debug min clamp=%d valSP1%s, rmarker_dtu: 0x%x, ts_rctu: 0x%llx, rmarker_rctu: 0x%llx len_or_datestsModeidle_duration_dtuant0.ant2.ch5.pdoa_lutchan_pll_cfgCould not enable regulator device CIA DIAG setup has failed (%d) instructions&dw->operational_state_wqDW3000_PWR_TX%s, return: %d AACKRANGING_PDOA_FOMTX_WAIT%s, rmarker_rctu: 0x%llx ts_rctuSPICRCERRconst char *CLK_OFFSETant1.ch9.prf16.tx_powerant0.ant3.ch5.pdoa_offsettemperature_referenceOTP_IF %s: %llu test mode: counter overflow for event %x:%llx false%s, n_segs: %u %s, rmarker_dtu: 0x%x %s, pdoa: 0x%08x Error while reading NFCC scratch RAMant0.ch9.prf16.ant_delayant2.ch9.prf64.pg_delayant1.ant2.ch5.pdoa_lutch9.pll_locking_codeCIA_2fail to get 'regulator_delay_us' %s test mode: start test %d registers%u intRANGINGLQInext_operational_stateSPI_UNFnext_optimestamp_dtu%s, err: "%s" cfoant3.ch5.prf64.ant_delayant3.ch9.prf64.pg_delayant3.portant1.ant2.ch9.pdoa_offsetNo regulators, assuming always on invalid reset gpio Failure to allocate message for reg 0x%x (index %u, len %d, mode %d) &stm->mtxunable to reach registers: device not ready DW3000_OP_STATE_DEEP_SLEEPDW3000_NFCC_COEX_TLV_TYPE_SLOT_LIST_UUSDW3000_DSS_STAT_SPI1_AVAIL_BIT_MASKu16%s, flags: %s, skb->len: %d timeout%s, flags: %s, timeout: %d %s, changed: 0x%x CPERRRXPRDfilter%s, current state: %s, new state: %s, delay_us: %d, expire: %u frm_durdss_stat%s, start: %s, idle_duration_dtu: 0x%08x, timestamp_dtu: 0x%08x, duration_dtu: 0x%08x, chan: %d warn%s, channel: %d s16include/linux/thread_info.hwatchdog timer is pendingant2.ch5.prf16.pg_countant3.ch9.prf16.pg_countant3.ch9.prf64.tx_powerSTS_CFGFS_CTRLrx_phrmoderolethread cpu %d cannot set CIA diagnostic option while the double buffering is disabled Failed to power device: %d state machine initialisation failed: %d DW3000_OP_STATE_SLEEPchannelTXPHSlow_sys_statusdelay_usstatepdoa%s, clockoffset: %d ../google-modules/uwb/qorvo/dw3000/kernel/drivers/net/ieee802154/dw3000_core.cant2.ch9.prf16.pg_delayant2.capsant3.ch5.prf16.ant_delayant3.ch5.prf64.pg_delaydataratetx_pwrdw3000-resetdevice coarse code setup has failed (%d) Could not set reset gpio as input RX buffer allocation failed device checking failed: %d poweron returns %d RANGING_PDOARX_WAITTIMER0%s, delay_dtu: %d, current_operational_state: %s, next_operational_state: %s time_beforeant1.ant2.ch5.pdoa_offsetDIG_DIAGchan_pg_delaytoo late to program delayed tx date_dtu=%x current_dtu=%x n_segsHPDWARNRXPHE%s, result: %d sleep_time_usboot_time_nsexpireSLOT_LISTsendant1.ch9.prf16.pg_countant1.ant2.ch9.pdoa_luttxrf_pwrfinC0Timeout waiting poweron event. regulator %s failed for 2p5 (%d) restricted_channels.pdoa_lutSPI pid: %u, dw3000 pid: %u checking device presence min_clamppoweroff returns %d DW3000_OP_STATE_TX_WAITDEEP_SLEEPpcode%s, ts_dtu: 0x%x, ant_offset: 0x%x, rmarker_rctu: 0x%llx ARFEVWARNAATCLK_PLL_LOCKresUNSPECenum dw3000_nfcc_coex_sendCLK_SYNCant0.ch9.prf16.tx_powerant1.ch5.prf16.tx_powercoex_margin_usgpiodirxtal_trimfail to get 'qos_latency' %s char[32]OFFINIT_RCrmarker_rctuSPIERRRXFR%s, sleep_us: %lld, sleep_enter_dtu: 0x%x, next_op_date: 0x%x, next_op: %s tschip_nameenum dw3000_nfcc_coex_tlv_typeduration_dtuSPIxMAVAIL interrupts enable failedspi available without timer pendingant0.ch9.prf16.pg_countant3.ch9.prf64.ant_delayant3.capsant0.ant3.ch5.pdoa_lutauto_sleep_marginspi_pidRX_TUNEPMSCeuidregulator_delay_usbranch instssetup mode: %d, %u bits/w, %u Hz max work enqueuing interrupted by signalimpossible to copy data to userlandDW3000_OP_STATE_RX_WAITtrueVT_DETPLL_HILORXFSLdelay_dtu%s, delay: %dus pacc_cntdgc_decant0.ch9.prf64.pg_countant0.selector_gpioant1.ch9.prf64.ant_delayant1.ch9.prf64.tx_powerant3.selector_gpio_valueant0.ant2.ch9.pdoa_offsetRF_CONFrx_antdlywificoex_delay_usqos latency %d uwberror when init of virtual registers DW3000_NFCC_COEX_TLV_TYPE_SLOT_LISTDW3000_NFCC_COEX_TLV_TYPE_ERRORCCA_FAILsignaturesend_timestamp_dtu../google-modules/uwb/qorvo/dw3000/kernel/drivers/net/ieee802154/dw3000_mcps.cwriting to nfcc exceed SCRATCH_AP_SIZEant0.ch5.prf16.tx_powerant0.ch5.prf16.pg_delayant2.ch5.prf64.tx_powerant1.ant3.ch9.pdoa_offsetalternate_pulse_shapegpiooutwificoex_margin_usFail to get %s regulator (%d) error when init of chip's registers no valid value provided DW3000_PWR_RUNDW3000_NFCC_COEX_SEND_CLK_OFFSETretu64u8TIMESTAMP_RCTUenum operational_stateAES_DONEGPIO_IRQRXOVRRDEEPSLEEPacc%s, session_time0_sys_time: 0x%08x %s, signature: %s, ver_id: %u, seq_num: %u, nb_tlv: %u %s, chan: %d, len: %d, rate: %d bad rssi value. Forced to 0 CIA_3RX_BUFFER1ext_clkdly_enpower_reg_1p8wificoex_interval_us&dw->cir_data->mutexregulator %s failed for 1p8 (%d) Bad antenna number (%d) can_dma: %d DW3000_PWR_OFFDW3000_NFCC_COEX_TLV_TYPE_SESSION_TIME0boolTXPRS%s, dss_stat: %s session_time0_sys_timeERRORQORVOant0.capsant1.ch9.prf64.pg_delayant2.ch9.prf64.ant_delayant3.ch5.prf64.tx_powercoex_gpioDRX_CONFRX_BUFFERext_clkdlydigi_diag_enD0Device already powered on fail to get 'wificoex_interval_us' %s regulator delay %d us Fail to read registers in fileId %d (%d) changedrmarker_dtu%s, utime: %llu, prf: %u, sts: %u %s, warn: "%s" configure channel failsprepare the configuration failsant1.ch5.prf16.ant_delayant1.ch9.prf64.pg_countant1.selector_gpio_valueant2.ch5.prf16.ant_delaySCRATCH_RAMframe_filterrx_sfd_toE0&dw->msg_mutexmrxlut configuration has failed (%d) unable to create parent dir %ld register %s is protected. Write refused because device is active %s, cannot program delayed, tx_date_dtu: 0x%x, cur_time_dtu: 0x%x RXSFDDdtu_next_opONTLV_UWBCNT_OFFSant0.ch5.prf64.pg_countant2.ch9.prf16.pg_countant3.ch9.prf16.tx_powerch5.pll_locking_codephr_modepdoa_modecannot program delayed rx date_dtu=%x current_dtu=%x power_reg_2p5irq-gpiocpucannot write frame data to DW IC regulator %s failed for vdd (%d) no support for callback %scir_data%u value not handled DW3000_NFCC_COEX_SEND_CLK_SYNC%s, too late to program delayed, rx_date_dtu: 0x%x, current_dtu: 0x%x WAKE_UP%s, status: %s RXPREJRCINITSPIRDYSPI2_AVAILver_id%s, ver_id: %u, seq_num: %u rateant0.ch9.prf64.pg_delayant2.ch5.prf64.pg_delayDRXunknown DEV_ID : %x Could not disable regulator device does not support GPIO RESET controlgpio coex disabled device chip specific init has failed (%d) TIMESTAMP_DTUSLEEPcurrent_operational_statedtu_sync%s, state: %s, boot_time_ns: %llu, len_or_date: %u s32offth_boostdataant2.ch5.prf16.pg_delayant2.ch9.prf64.tx_powerant3.ch9.prf64.pg_countant0.ant1.ch9.pdoa_offsetant1.ant3.ch5.pdoa_lutcoex_delay_usDevice already powered off fail to get 'wificoex_gpio' %s Bad antennas set id selected (%d) for pdoa PGF calibration failed device enable failed: %d could not register: %d %s, timeout: %s, timeout_dtu: 0x%0x, next_operational_state: %s IDLE_RCRXSTORXFTO%s, time_ns: %lld %s, ts: %llu, f1: %u, f2: %u, f3: %u, acc: %hu, fpidx: %hu, offset: %d, filter: 0x%x adjusted_powerSPI1_AVAILnb_tlv__data_loc char[]message check failureant3.ch5.prf16.pg_delayant3.ch5.prf64.pg_countant0.ant1.ch5.pdoa_offsetant2.ant3.ch5.pdoa_offsetSET_Xrx_diagpower_regdouble banking not supported device disable failed: %d dw3000-%sdw3000_set_sched_attr failed: %d error reading dt_clamp ret=%d %.12s: power%s, return: %d, value: 0x%x RSSIRANGING_OFFSETts_dtuCOEX_ERRRXFCEbase_power%s, clock_offset_sys_time: 0x%08x (null)ant0.ch5.prf64.tx_powerant0.ch9.prf64.ant_delayant1.ch5.prf16.pg_delayant1.ch9.prf16.pg_delayant2.ch9.prf16.ant_delayant3.selector_gpiorx_sts_modegpio coex enabled : gpio %u, delay %u, interval %u, margin %u fail to get 'cpu' %s enablehard reset failed: %d copy failed DW3000_OP_STATE_IDLE_RClen|RANGING_STS_TIMESTAMP_RCTURXant_offsetRXPHD%s, res: %d, xtrim: %d, bias: %d app_boostSTOPant0.ch5.prf16.ant_delayant1.ch5.prf64.tx_powerant3.ch5.prf16.pg_countant2.ant3.ch5.pdoa_lutant2.ant3.ch9.pdoa_lutCIA_1rx_sts_lencould not transfer : %d fail to get 'wificoex_margin_us' %s test mode: test %d done in %llu ms, %llu us per read (status %x) Could not set reset gpio as output cpu cycles device init failed: %d DW3000_OP_STATE_RXcur_time_dturx_date_dtuIDLE_PLLpageSEMA_ERRPGFCAL_ERR%s, low_sys_status: 0x%08x sys_time_syncs64%s, chip: %s, sts: %u, cir_pwr: %u, pacc_cnt: %u, prf_64mhz: %u, dgc_dec: %u session_idnext_duration_dtuant1.ch5.prf16.pg_countant1.ch5.prf64.ant_delayant1.capsant0.ant3.ch9.pdoa_offsetch5.wifi_coex-enabledtx_phrratetx_antdlyrx_phr_raterx_paclenfail to get 'wificoex_delay_us' %s qos_latency&x->waitdevice reset failed: %d DW3000_OP_STATE_TXDW3000_NFCC_COEX_SEND_STOPRANGING_STS_FOMTXSTSRUNutimef3seq_num%s, next_timestamp_dtu: 0x%08x, next_duration_dtu: 0x%08x %s, mode: %d ant2.ch9.prf64.pg_countant3.ch5.prf16.tx_powerant0.ant2.ch5.pdoa_offsetchip version found : %x could not read the frame info : %d fail to access register %s (%ld) 0x%llx DW3000_PWR_IDLEKEEP_RANGING_CLOCKRXSTSLCSSERRresult%s, res: %d, gpio: %u, value: %u f1next_timestamp_dtutypeant1.ch9.prf16.ant_delayant2.portant0.ant2.ch9.pdoa_lutant2.ant3.ch9.pdoa_offsetGPIO_CTRLBad antennas selected or bad configuration ant1=%d (port=%d), ant2=%d (port=%d) memory allocation failed for cir data buffer WiFi coexistence configuration has failed (%d) Off state: count: %llu dur ns: %llu Deep sleep state: count: %llu dur ns: %llu Run state: count: %llu dur ns: %llu Idle state: count: %llu dur ns: %llu Tx state: count: %llu dur ns: %llu Rx state: count: %llu dur ns: %llu Interrupts: count: %lld device power-off failed: %d device power on failed: %d dt_clamp=%d debugfs directory creation failed %s is not valid value DW3000_PWR_RXSP2STS_MODE_MASKtx_date_dtutimeout_dtuAES_ERRRXFCG%s, operational_state: %s clock_offset_sys_timeSESSION_TIME0Reading from NFCC exceed SCRATCH_AP_SIZEant0.ch9.prf64.tx_powerant2.selector_gpio_valueant1.ant3.ch5.pdoa_offsetpower_statsDW3000_OP_STATE_WAKE_UPdw_name%s RANGING_FOMIRQSoperational_statebiaschan%s, type: %s, data: %s ant0.portant2.ch5.prf16.tx_powerant2.ch5.prf64.pg_countant2.ch9.prf16.tx_powerant3.ch9.prf16.ant_delayEXT_SYNCRF_CALIN_PTR_CFGreset-gpioInvalid or unmanaged operational state %d, current state: %d test mode: cannot create perf_hw_evt %d (err %ld) device OTP read has failed (%d) cir_configDW3000_OP_STATE_OFFDW3000_PWR_DEEPSLEEP%s, flags: %s RXPTOCIA_DONETXFRBIDLEprf_64mhzSLOT_LIST_UUSstart%s, send: %s, idle_duration_dtu: %d, send_timestamp_dtu: 0x%08x  dnfcc_coex_margin_dtu`dhilptux|  $(),-./02||,.||(*||$&|| "|||| $)`+d+h+p*d*h*l*TVyd,.L    l l QJ !!|  ? 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