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T{B*OEWD_C^__zA*4 @B) @@@5d^{ d@`@` @*{¨^__^{O\ QqT2(R@R`7@@4*$@S>@R  (Rh`4??**4*OA{¨^__^{ O^@4*, @ Qq(T2@R6*4*@>@R * h`4??OB @{è^__^{ WO\h4* @ @*q a@93KT @@qq`T7R@@zhq7k T@97*OCWB @{Ĩ^__c*__^{OC@*\%qT`R`7***B1T@4`R* @)@?T{A*OC@^__^{\%qT(@`R`6*{^__|%s: %s size mismatch, phdr_size: 0x%x fw_size: 0x%zxwcd_clsh_state_ear_auxwcd_clsh_state_hph_auxwcd_clsh_state_aux&wdsp->ssr_mutex&wdsp->api_mutexget_impedance_index%s: native_clk %x rx1_rate= %x rx2_rate= %xwdsp_get_segment_listwdsp_add_segment_to_listwcd_clsh_state_hph_sttransportwdsp_get_devops_for_cmpntwdsp_unicast_eventaudio_ext_clk_get_parentwdsp_load_each_segmentwcd_resmgr_post_initwcd_resmgr_initwcd9xxx_soc_init&x->wait%s.mdtwcdcal_hwdep_ioctl_compatvbatwdsp_init_componentsqcom,wdsp-componentswdsp_download_segmentswcd_resmgr_codec_reg_update_bitswdsp_register_cmpnt_opswdsp_collect_ramdumpswdsp_init_and_dload_code_sectionspmic-clock-nameswdsp_mgr_parse_dt_entrieswcd_resmgr_enable_master_bias%s%s%s%s Wrong request for class H state machine requested to %s %sCodec %s%s: buck_users %d, enable %d, mode: %s%s: flyback_users %d, enable %d, mode: %swcd_clsh_state_errpanic_on_errorwdsp_mgrwcd-dsp-mgrwdsp_ssr_handlerwdsp_debug_dump_handlerwdsp_signal_handlerwdsp_is_valid_elf_hdrwcd_clsh_state_hph_earwcd_clsh_state_earwcd_clsh_state_hph_rqcom,codec-lpass-ext-clk-freqwdspwdsp_vote_for_dspwdsp_disable_dspwdsp_enable_dspsleepwcd_cal_create_hwdepwcd_clsh_state_ear_lowcd_clsh_state_hph_lowcd_clsh_state_lowcd_resmgr_disable_clk_rcowcd_resmgr_enable_clk_rcowdsp_ssr_work_fn%s: clock register failed for clk_src = %d\nwcd_clsh_fsmwcd_cls_h_fsmwcd9xxx_dlkmwcdcal_hwdep_ioctlaudio_get_pinctrlqcom,use-pinctrlwcd_clsh_buck_ctrlwcd_clsh_flyback_ctrlcontrolwcdcal_get_fw_calwcd_clsh_state_hph_laudio_lpass_mclkwcd_resmgr_disable_clk_mclkwcd_resmgr_enable_clk_mclkaudio_ext_pmi_clklpass_hw_vote_clkaudio_ext_pmi_lnbb_clkaudio-ref-clkwcd_resmgr_disable_clk_blockwcd_resmgr_enable_clk_blockwcd_enable_clsh_block&resmgr->master_bias_lock&resmgr->codec_bg_clk_lock&fw_data->lockinclude/linux/uaccess.hinclude/linux/dma-mapping.hwdsp_get_cmpnt_type_stringwdsp_get_ssr_type_stringwcd_clsh_imped_configqcom,mclk-clk-regis_native_44_1_activeaudio_ext_clk_unpreparelpass_hw_vote_unprepareaudio_ext_clk_preparelpass_hw_vote_preparewcd_resmgr_get_clk_typewdsp_resumeqcom,img-filenameqcom,wdsp-cmpnt-dev-namewdsp_mgr_parse_phandledisableenablewdsp_load_fw_imagewcd_clsh_set_hph_modewdsp_mgr_probeaudio_ref_clk_probewdsp_mgr_bindwdsp_suspendInvalidqcom,codec-lpass-clk-idwcdcal_hwdep_ioctl_shareddisabledenabled__wdsp_set_ready_locked__wdsp_clr_ready_locked__wdsp_dbg_dump_lockedwcd_resmgr_set_sido_input_src_lockedmadwcd_resmgr_codec_reg_read%s.b%02d%s: clsh_users %d, enable %dwcd_resmgr_set_sido_input_srcqcom,codec-ext-clk-srcipcancmbhctechpack/audio/asoc/codecs/wcd-dsp-mgr.ctechpack/audio/asoc/codecs/audio-ext-clk-up.ctechpack/audio/asoc/codecs/wcd-clsh.ctechpack/audio/asoc/codecs/wcd9xxx-resmgr-v2.ctechpack/audio/asoc/codecs/wcd9xxx-common-v2.caudio_get_clk_data[STATE_UNKNOWN][STATE_IDLE][STATE_AUXSTATE_HPH_RNO_SSRSTATE_EARCDC_UPCLS_H_LPCLS_H_ULPLPASS_HW_MACROSTATE_LOWCD_CLK_RCOWDSP_DOWNCDC_DOWNSTATE_HPH_LCLS_H_NORMALWCD_CLK_MCLKCLS_H_HIFICLS_AB_HIFICLS_H_LOHIFIELFWCD_CLK_OFFCLS_H_INVALIDWCD_CLK_UNDEFINEDCLS_ABaudio_lpass_mclk7audio_lpass_mclk6audio_lpass_mclk5audio_lpass_mclk4audio_lpass_mclk3ln_bb_clk3wcd_resmgr_post_ssr_v2audio_lpass_mclk2pm6125_div_clk1pms405_div_clk1pm6150_div_clk1qpnp_clkdiv_13%s: failed to copy %s: Invalid start addr 0x%x or dump_size 0x%zx %s: base_addr 0x%x, dump_start_addr 0x%x, dump_size 0x%zx %s: base_addr 0x%x, split_fname %s, load_addr 0x%x, size 0x%zx %s: Failed, err = %d for base_addr = 0x%x split_fname = %s, load_addr = 0x%x, size = 0x%zx %s: Failed to read dumps, size 0x%zx at addr 0x%x %s: wdsp in invalid state 0x%x %s: WDSP in invalid state 0x%x %s: ready_status = 0x%x %s: wait_for_ready timed out, status = 0x%x %s: Invalid addr 0x%x, base_addr = 0x%x %s: set 0x%lx, new_state = 0x%x %s: clear 0x%lx, new_state = 0x%x %s: Invalid type %u %s: parent index = %u 4%s: RCO enable requires MCLK to be ON first 3%s: Codec memory is NULL, nothing to post init %s: Error %d to download code sections %s: Invalid input params %s: could not find pmic clock names %s:Invalid old state:%s %s: Failed to register component dev %s %s: Init failed (%d) for component %s %s: cannot dump memory, ssr_type %s, dumps %s %s Wrong request for class H state machine requested to %s %s %s: not valid event_handler for %s 3%s: incorrect firmware size %d for %s %s: ClassH state transition from %s to %s %s: Current ssr_type %s, handling ssr_type %s %s: invalid phandle_arg to of_node %s %s: Class-H not a valid new state: %s %s: Class-H already in requested state: %s %s: mclk_users: %d, clk_type: %s %s: rco clk users: %d, clk_type: %s 3%s: Error enabling MCLK, clk_type: %s 3%s: Unknown Clock type: %s %s: buck_users %d, enable %d, mode: %s %s: flyback_users %d, enable %d, mode: %s %s: mode: %s, %s 3%s: Cannot get wcd9xx pointer %s: Normal mode not applicable for hph_r %s: Ramdump device is not setup %s: SSR handling is running, skip debug ramdump %s: marking ready completion %s, detected impedance is less than 4 Ohm %s, detected impedance is greater than 12 Ohm 3%s: wcd regmap is null 3%s: Firmware too small %s: sido input src to external %s: sido input src to internal %s: no memory for %s cal %s: Normal mode not applicable for hph_l 3%s: No mclk users, cannot disable mclk %s: miss mclk reg %s: could not get sleep pinstate %s: could not get active pinstate %s: already requested before %s: Acquiring BG_CLK done 3%s: Too small MDT file 3%s: Not an ELF file %s: Unable to get pinctrl handle 3%s: Invalid device handle 3%s: rco_clk_users = %d, clk_type = %d, cannot disable 3%s: Not an executable image 3%s: Invalid handle to device %s: firmware %s not found %s: fw mdt %s is invalid 3%s: resmgr not initialized 3%s: resmgr not allocated 3%s: wrong arguments passed 3%s: codec/regmap not defined %s: clk_init is failed 3%s: Disable clock %s failed 3%s: Enable clock %s failed %s ioremap failed RCO Calibration failed %s: Parsing PMI pinctrl failed 3%s afe_set_digital_codec_core_clock failed %s: create_ramdump_device failed %s:clsh is already enabled %s: clsh is not enabled 3%s: Cannot turn on MCLK, BG is not enabled %s: cmpnt %d already added 3%s: no segments to load %s: old_bg_audio_users=%d old_clk_mclk_users=%d old_clk_rco_users=%d %s: component not found at idx %d 3%s: wrong cal type sent %d %s: do_ramdump failed with error %d %s: handling signal %d failed with error %d %s: Raised signal %d 3%s: active state select failed with %d %s: Disable TLMM pins failed with %d %s: Invalid request for segment_type %d 3%s: Invalid ssr_type %d %s: get_dev_ops failed for cmpnt type %d 3%s: Invalid component type %d %s: Error %d to get image segments for type %d %s:Invalid mode %d 3%s: cal not sent by userspace %d %s: Invalid phandle + arg count %d, expected %d %s: new hwdep failed %d 3%s lpass core hw vote failed %d %s: parse_phandle at index %d failed %d %s: selected impedance index = %d %s: could not get clk source, ret = %d 3%s: afe_set_lpass_clk_cfg failed, ret = %d %s: request %s, current users = %d %s: Failed to dload code sections err = %d %s: Failed to add master, err = %d %s: Failed to boot dsp, err = %d %s: Failed to shutdown dsp, err = %d %s: Failed WDSP shutdown, err = %d %s: dload code sections failed, err = %d %s: wdsp %s failed, err = %d %s: Data section download failed, err = %d %s: INIT failed, err = %d %s: Reading property %s failed, error = %d %s, impedance not in range = %d %s: hph_mode = %d %s: Invalid clk source = %d %s: clock add failed for clk_src = %d %s: current master bias users: %d 3%s: init dsp mgr fail: %d 3%s: init extclk fail: %d %s: LO cannot be in this mode: %d %s: ext-clk freq: %d, lpass clk_id: %d, clk_src: %d %s: use-pinctrl : %d 3%s: Invalid private_data %s: Property %s not defined in DT %s: mode: %s cannot be used for EAR %s: Invalid input, arg is NULL 3%s: fw_data is NULL %s: Releasing BG_CLK %s: Acquiring BG_CLK %s: mutex_unlock(%s) %s: mutex_lock(%s) 3%s: wrong ioctl command sent %u! 3%s: wrong ioctl command sent %d! 3%s: codec didn't set this %d!! %s: %s did not register ops %s: component %s failed to resume %s: component %s failed to suspend %s: undefined ssr_type %d %s: component_bind_all failed %d     ppp ! !! Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r Y \ ^ m p r      @H .qcom,wcd-dsp-mgrqcom,audio-ref-clk@W[59-y%"4W:~V /AAC(SdCYEkmT^-0wcd_cls_h_fsmwcd_cls_h_initwcd_clsh_imped_configwcd_clsh_fsmwcd_clsh_get_clsh_statewcd_clsh_initwcd_resmgr_get_clk_typewcd_resmgr_post_ssr_v2wcd_resmgr_enable_master_biaswcd_resmgr_disable_master_biaswcd_resmgr_enable_clk_blockwcd_resmgr_set_sido_input_srcwcd_resmgr_set_sido_input_src_lockedwcd_resmgr_disable_clk_blockwcd_resmgr_initwcd_resmgr_removewcd_resmgr_post_initwcdcal_get_fw_calwcd_cal_create_hwdepwdsp_flush_segment_listwdsp_get_segment_listdescription=WCD Class-H Driverlicense=GPL v2description=WCD9XXX Common Driverlicense=GPL v2description=wcd9xxx resmgr v2 modulelicense=GPL v2description=WCD9XXX CODEC soc init driverlicense=GPL v2description=WCD DSP manager driverlicense=GPL v2description=Audio Ref Up Clock module platform driverlicense=GPL v2vermagic=4.14.285-g5f00bf266851-ab8874763 SMP preempt mod_unload modversions aarch64name=wcd9xxx_dlkmintree=Ydepends=q6_dlkm,wcd_core_dlkmalias=of:N*T*Cqcom,wcd-dsp-mgralias=of:N*T*Cqcom,wcd-dsp-mgrC*alias=of:N*T*Cqcom,audio-ref-clkalias=of:N*T*Cqcom,audio-ref-clkC*Android (7284624, based on r416183b) clang version 12.0.5 (https://android.googlesource.com/toolchain/llvm-project c935d99d7cf2016289302412d708641d52d2f7ee)  E ^{ 4***4** @{¨^__^{{^__wcd9xxx_dlkm-module_layoutQ)afe_unvote_lpass_core_hwq6core_is_avs_up~S*gafe_vote_lpass_core_hwclk_hw_get_num_parentsX___ratelimitduncached_logkxafe_set_lpass_clk_cfgUof_clk_add_providerBeof_clk_src_onecell_getUdevm_clk_register=K__ioremap*pinctrl_select_state0devm_pinctrl_putBڴpinctrl_lookup_stateQ#devm_pinctrl_getK)of_property_read_variable_u32_array~)Hmemcpyxmcomplete.idestroy_ramdump_device16debugfs_remove_recursive~cancel_work_sync/ .queue_work_onӅ3-system_wqUy!qdebugfs_create_bool4debugfs_create_dirKB)component_unbind_all!component_bind_all 7_dev_info,create_ramdump_device}Ѷdma_release_from_dev_coherentjdo_ramdumpЀ9dma_alloc_from_dev_coherentm9W#dummy_dma_opsZ%strcmp{Cwait_for_completion_timeoutͲcomponent_master_delՐcomponent_master_add_with_matchL{arch_setup_dma_ops#\__init_waitqueue_head__init_workcomponent_match_add_releaseU pdevm_kfreeof_parse_phandle_with_fixed_argsof_count_phandle_with_argsof_property_read_stringWhvQdevm_kmalloc%Э8platform_driver_unregisterJh__platform_driver_registerh__list_add_validКDmemcmpM request_firmwareUrS__list_del_entry_validGrelease_firmwareHۈ__check_object_sizedmemsetK__arch_copy_from_userxp __might_fault地__kmalloc Mset_bitѣfind_next_bit3qsnd_hwdep_new`Ϙstrlen ~mutex_destroy zkfreef\__mutex_init"\kmem_cache_alloc_trace-;kmalloc_caches9p4regmap_readYpregmap_update_bits_baseQmutex_unlockSLLmutex_lockXUprintkCwcd9xxx_slim_bulk_write snd_soc_write2̺snd_soc_read&ԱD__dynamic_pr_debugGusleep_range7(snd_soc_update_bitscstrlcat1(snprintf__stack_chk_failA,__dynamic_dev_dbgrdev_errg__stack_chk_guardGNU+qi^  @(8((S f y h H , t  h \ P(/ LE \X(x((@(h(((?(a(x((  'A (! \W "c !u(( #P( 0( "@+X(C(S %f & t+ $3 :X @x^ 4Et ,< L (H(/ N(X( Q((8(a`( $S('(K(o((P(p(( !0PP3 ,00C@e@@X``."P *   Tx((3(W({(0( (@(h(D(t((( X(' =  V fx x ~   , U ~      %I x 1 pp N  ^ 2 pQ p _%  $  z      $L    p $  3   O n   *   00!@@ A Q tP` ̘`t @   Ȓ  h& đ| , (: pPH(op(((( ( 8 ()(V ܛ(m((` ( ( t 8  Lt 45 (X (~ ( H d (( ( h (8 O (uP ( p  (0 ( ( (  (? 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&$xstate_to_strclsh_state_fpwcd_cls_h_fsm.descriptorwcd_cls_h_fsm.descriptor.6wcd_clsh_state_errwcd_clsh_state_earwcd_clsh_state_hph_auxwcd_clsh_state_auxwcd_clsh_state_ear_auxwcd_clsh_state_hph_lwcd_clsh_state_hph_rwcd_clsh_state_hph_stwcd_clsh_state_hph_earwcd_clsh_state_ear.descriptorwcd_clsh_flyback_ctrlwcd_clsh_buck_ctrlwcd_clsh_state_hph_l.descriptorwcd_clsh_state_hph_l.descriptor.36wcd_clsh_state_hph_r.descriptorwcd_clsh_state_hph_r.descriptor.39wcd_clsh_state_hph_st.descriptorwcd_clsh_state_aux.descriptorwcd_clsh_state_hph_aux.descriptorwcd_clsh_state_ear_aux.descriptorwcd_clsh_state_hph_ear.descriptorwcd_clsh_flyback_ctrl.descriptorwcd_clsh_buck_ctrl.descriptor$d__kstrtab_wcd_cls_h_fsm__ksymtab_wcd_cls_h_fsm__kstrtab_wcd_cls_h_init__ksymtab_wcd_cls_h_init__UNIQUE_ID_description87__UNIQUE_ID_license88imped_tableimped_table_tavilwcd_clsh_imped_config.imped_table_ptrget_impedance_index.descriptorget_impedance_index.descriptor.13imped_indexget_impedance_index.descriptor.15wcd_clsh_imped_config.descriptorwcd_clsh_fsm.descriptorwcd_clsh_fsm.descriptor.10wcd_clsh_state_hph_lowcd_clsh_state_lowcd_clsh_state_ear_lowcd_enable_clsh_block.descriptorwcd_clsh_set_hph_modewcd_clsh_state_lo.descriptoris_native_44_1_activewcd_clsh_state_hph_lo.descriptorwcd_clsh_state_hph_lo.descriptor.58wcd_clsh_state_hph_lo.descriptor.60wcd_clsh_state_hph_lo.descriptor.62wcd_clsh_state_ear_lo.descriptoris_native_44_1_active.descriptor__kstrtab_wcd_clsh_imped_config__ksymtab_wcd_clsh_imped_config__kstrtab_wcd_clsh_fsm__ksymtab_wcd_clsh_fsm__kstrtab_wcd_clsh_get_clsh_state__ksymtab_wcd_clsh_get_clsh_state__kstrtab_wcd_clsh_init__ksymtab_wcd_clsh_init__UNIQUE_ID_description90__UNIQUE_ID_license91.L21wcd_resmgr_post_ssr_v2.descriptorwcd_resmgr_post_ssr_v2.descriptor.5wcd_resmgr_post_ssr_v2.descriptor.7wcd_resmgr_post_ssr_v2.descriptor.9wcd_resmgr_enable_master_bias.descriptorwcd_resmgr_enable_clk_rco.descriptorwcd_resmgr_enable_clk_mclk.descriptorwcd_resmgr_set_sido_input_src.descriptorwcd_resmgr_set_sido_input_src.descriptor.17wcd_resmgr_set_sido_input_src_locked.descriptorwcd_resmgr_set_sido_input_src_locked.descriptor.20wcd_resmgr_set_sido_input_src_locked.descriptor.21wcd_resmgr_disable_clk_rco.descriptorwcd_resmgr_disable_clk_mclk.descriptorwcd_resmgr_init.__keywcd_resmgr_init.__key.25__kstrtab_wcd_resmgr_get_clk_type__ksymtab_wcd_resmgr_get_clk_type__kstrtab_wcd_resmgr_post_ssr_v2__ksymtab_wcd_resmgr_post_ssr_v2__kstrtab_wcd_resmgr_enable_master_bias__ksymtab_wcd_resmgr_enable_master_bias__kstrtab_wcd_resmgr_disable_master_bias__ksymtab_wcd_resmgr_disable_master_bias__kstrtab_wcd_resmgr_enable_clk_block__ksymtab_wcd_resmgr_enable_clk_block__kstrtab_wcd_resmgr_set_sido_input_src__ksymtab_wcd_resmgr_set_sido_input_src__kstrtab_wcd_resmgr_set_sido_input_src_locked__ksymtab_wcd_resmgr_set_sido_input_src_locked__kstrtab_wcd_resmgr_disable_clk_block__ksymtab_wcd_resmgr_disable_clk_block__kstrtab_wcd_resmgr_init__ksymtab_wcd_resmgr_init__kstrtab_wcd_resmgr_remove__ksymtab_wcd_resmgr_remove__kstrtab_wcd_resmgr_post_init__ksymtab_wcd_resmgr_post_init__UNIQUE_ID_description91__UNIQUE_ID_license92wcdcal_hwdep_ioctl_compatwcdcal_hwdep_ioctlwcdcal_hwdep_releasewcd_cal_create_hwdep.__keywcdcal_hwdep_ioctl_shared__kstrtab_wcdcal_get_fw_cal__ksymtab_wcdcal_get_fw_cal__kstrtab_wcd_cal_create_hwdep__ksymtab_wcd_cal_create_hwdep__UNIQUE_ID_description65__UNIQUE_ID_license66__kstrtab_wdsp_flush_segment_list__ksymtab_wdsp_flush_segment_list__kstrtab_wdsp_get_segment_list__ksymtab_wdsp_get_segment_listwdsp_mgr_driverwdsp_mgr_probewdsp_mgr_compare_ofwdsp_load_fw_imagewdsp_mgr_probe.__keywdsp_mgr_probe.__key.2wdsp_ssr_work_fn__init_completion.__keywdsp_master_opswdsp_mgr_removewdsp_init_and_dload_code_sectionswdsp_ssr_work_fn.descriptorwdsp_collect_ramdumpswdsp_ssr_work_fn.descriptor.38wdsp_ssr_work_fn.descriptor.40wdsp_ssr_work_fn.descriptor.42wdsp_ssr_work_fn.descriptor.44wdsp_ssr_work_fn.descriptor.45wdsp_ssr_work_fn.descriptor.46wdsp_ssr_work_fn.descriptor.48wdsp_init_and_dload_code_sections.descriptorwdsp_download_segmentswdsp_load_each_segment.descriptorwdsp_download_segments.descriptorwdsp_collect_ramdumps.descriptorwdsp_collect_ramdumps.descriptor.55wdsp_mgr_bindwdsp_opswdsp_mgr_unbindwdsp_register_cmpnt_opswdsp_register_cmpnt_ops.descriptorwdsp_register_cmpnt_ops.descriptor.72wdsp_get_dev_for_cmpntwdsp_get_devops_for_cmpntwdsp_signal_handlerwdsp_signal_handler.descriptorwdsp_signal_handler.descriptor.75wdsp_ssr_handlerwdsp_debug_dump_handler.descriptor__wdsp_dbg_dump_lockedwdsp_debug_dump_handler.descriptor.90wdsp_signal_handler.descriptor.78wdsp_vote_for_dspwdsp_vote_for_dsp.descriptorwdsp_vote_for_dsp.descriptor.96wdsp_enable_dsp.descriptorwdsp_enable_dsp.descriptor.107wdsp_enable_dsp.descriptor.106wdsp_enable_dsp.descriptor.108wdsp_vote_for_dsp.descriptor.102wdsp_disable_dsp.descriptor__wdsp_set_ready_locked.descriptor__wdsp_set_ready_locked.descriptor.87wdsp_disable_dsp.descriptor.110wdsp_disable_dsp.descriptor.111wdsp_disable_dsp.descrip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