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J  /  A        k  k / K       t d    j ,    0 I   ]    / / "%c|%d|%s|%d", REC->type, REC->pid, __get_str(name), REC->value$/$"type=0x%02x length=%u last=%d tx=[%s]", REC->type, __get_dynamic_array_len(tx_buf), REC->last, __print_hex(__get_dynamic_array(tx_buf), __get_dynamic_array_len(tx_buf))"cmd=0x%02x length=%u rx=[%s]", REC->cmd, __get_dynamic_array_len(rx_buf), __print_hex(__get_dynamic_array(rx_buf), __get_dynamic_array_len(rx_buf))"header=%d payload=%d", REC->header, REC->payload 3%s(#%d) failed to get win resource 3%s(#%d) invalid decon id(%d) %s(#%d) Non error reporting format (rx_fifo=0x%x) %s(#%d) word clock is %u MHz %s(#%d) %s: command mode set %s(#%d) -[PLL : offset + 0x100]- %s(#%d) name(%s) type(%d) regs(%p) ../google-modules/display/samsung/cal_9845/dqe_reg.cdqe_reg_print_linear_matrix%s(#%d) [Red] 3%s(#%d) Failed to pack oetf_posy plane: src-pos=%d.%06ux%d.%06u%+d.%06u%+d.%06u partial region[%d %d %d %d] Native%s: obtained fake mmap offset %llu from handle %u recoverycoeff_gdpu_print_log_atomicexynos_dqe_hibernation_enterdstepthreshold_3hibernation_unblock_enter%s: skipping due to (active=%d enable=%d) applied partial regionalign limitation. src_x/y[%d/%d] align[%d] [PARTIAL]: %s: partial[%dx%d] vporch[%d %d %d] hporch[%d %d %d] rd_endelay_comp6%s[%u]: line delay scaler(%d) 3%s[%u]: failed to install FRAME START irq %s[%u]: %s: reset=%d dpp_init_resources3%s: %s[%d]: not supported destination alignment dsim_host_attach6%s: %s[%d]: already disabled(%d) %s: %s[%d]: long packet was received __dsim_wait_for_pl_fifo_empty%s: %s[%d]: no need to wait for payload fifo empty %s: %s[%d]: payload length(%lu) 3%s: %s[%d]: could not get dsi modes 3%s: %s[%d]: %pOF: could not find dsim-modes node pll-vco-range4%s: %s[%d]: %s: diag parsing error with unexpected index %u %s[%d]: PH_FIFO_EMPTY irq occurs tui-driverBT709[BTS] BTS_BW_TYPE(%d) ../google-modules/display/samsung/exynos_drm_fb.c%s(#%d) none blending(no plane alpha) mode 4%s(#%d) decon%d RSC_STATUS_0: SEL_CH = 0x%x %s(#%d) escape clock is %u MHz dpp_reg_set_csc_coef3%s(#%d) IDMA FBC error irq occur dqe_reg_print_hist%s(#%d) DQE: linear matrix %s DISP%s(#%d) %s mode, frame control %s, frame offset: %d %s(#%d) DQE: degamma %s %s(#%d) HDR: eotf %s tui_status3%s: timeout of waiting for fence, name:%s idx:%d 4%s: skip frame update at %s 20110530histogram_roivrr_switch_durationsrc[%u %u %u %u], dst[%d %d %u %u] ABGR8888XBGR88883%s: Failed to map virtual address %s: mapped vaddr: %pK ST2084gammut_matrixvalueforce_disabled reconfig(%d)%s: histogram: created event(0x%pK) of decon%u exynos_degamma_updateexynos_partial_initialize4%s[%u]: WARN: scaler line delay is not defined in DT. %s[%u]: WARN: afbc_rgb_rt_util_pct is not defined in DT. hw trigger.decon_wait_for_te%s[%u]: %s: win=%d enabled dpp_ch=%d [drm] %s: handover memory defined, but cannot find handover dpp decon_atomic_flush4expected present time seems incorrect(now %llu, earliest %llu) %s[%d]: === buffer dump[%s:%s]: dpp%d dma addr 0x%pad, vaddr 0x%p === 3%s: %s[%d]: not supported destination size range disablepending packets remaining ph(%u) pl(%u) %s[%d]: short packet was received 4%s: %s[%d]: timeout: packet payload fifo empty 3%s: %s[%d]: no device tree information %s[%d]: TE from DDI%d 4%s: %s[%d]: failed to get TE gpio %s[%d]: failed to get ERR_FG gpio hs-clkpll-out-range%s[%d]: pll features: output(%llu, %llu) %s[%d]: found proper pll parameter %s[%d]: underrun_lp_ref 0x%x 3%s: %s[%d]: failed to find panel dsim_unbindwb_init_resources[BTS] %s + 6[BTS] decon%u bts feature is enabled ../google-modules/display/samsung/exynos_drm_decon.c%s(#%d) interrupt val = %x 3%s(#%d) decon(%d) is invalid to set dither decon_reg_set_dither_path3%s(#%d) Checksum error(long packet only)! dsim_reg_get_dphy_timing3%s(#%d) IDMA deadlock irq occur %s(#%d) image size: %d x %d %s(#%d) %s exynos_atomic_exit_tui4%s: error of waiting for dma fence, ret=%d [drm:%s] devm_drm_dev_alloc failed: %li &private->waitconnector_pre_commitdisabling bridge chain [ENCODER:%u:%s] RGBA1010102%s: mmaped the offset %lu of size %lu to %#lx Linearurgentdpu_event_get_nextdisp_dither3failed to create cgc directory 3failed to create degamma directory 3failed to create %s lut directory range_x_min DPU POWER:%s DECON STATE:%uexynos_atc_updategain_limitlt_calc_ab_shift6display hibernation is overridden [PARTIAL]: %s: changed full: requested region is bigger is_partial_supported[PARTIAL]: %s: partial command: [%d %d %d %d] [PARTIAL]: %s: slice left(%d) right(%d) 3[RECOVERY] %s: Failed to recover display decon,idppcafbc_rgb_rt_util_pctdimming_start4%s[%u]: %s: irq occurs with decon->state=%d early_wakeup3%s: failed to get cgc-dma id __data_loc u8[]dsim_host_detach%s[%d]: - dsim_parse_dtdsim_remap_regs3%s: %s[%d]: failed to get sys resource 6%s: %s[%d]: dsim power is off state(0x%x) 3%s: %s: s %u is out of range (%u, %u) unknown dsim state (%d) dsim_atomic_check_dsim_exit_ulps_lockedexynos_tui_open6src_f_w[%d %d %d] src_f_h[%d %d %d] 6max scale up(%dx), down(1/%dx) ratio 3failed to get dma resource DECON%u3invalid DPU AXI channel number %u decon_reg_set_win_bnd_function3%s(#%d) Low-power transmit sync error! dsim_reg_enable_lane_phy%s(#%d) === DPP%d SFR DUMP === cgc_dma_dump_regs%s(#%d) === DQE_%d SFR === local_hbm_modeHDR10commit_planesalpha[%d] blend mode[%d] 3%s: Failed to allocate %#zx bytes from DMA-BUF system heap Gamma 2.6en(%d) dirty(%d) vrefresh(%d) dstep(%d/%d) back_light&hibernation->lock[PARTIAL]: %s: slice[%d] is %s outdecon_get_main_dsim_idDP1%s[%u]: blend_mode(%d) color(%s:0x%x) %s[%d]: unable to find vaddr for old buffer %s[%d]: enabled %s: %s DPU protection status changed to %d3%s: %s[%d]: failed to probe exynos dsim driver unable to link %s sysfs (%d) %s: %s[%d]: payload: 0x%x i=%d max=%d %s: %s[%d]: wait for packet header fifo empty 3%s: %s[%d]: wrong dsim id(%d) 4%s: %s[%d]: failed to get TE from DDI k-bits6%s: %s[%d]: 4:Prbs7 Random (%d) dsim_set_hs_clock3%s: %s: max frame time %llu < min frame time %llu %s[%d]: state: %d self_refresh: %d->%d unable to create dev link between decon/dsim 3failed to remap DPP SFR region standarddpu_bts_init6[BTS] IDMA_TYPE(%d) CH(%d) Port(%u) 3%s(#%d) wait timeout decon idle status %s(#%d) === DECON_WINCON%d SHADOW SFR DUMP === decon_windsim_reg_set_mresdsim_reg_sw_resetdsim_reg_wait_enter_ulps_state%s(#%d) slice0 w(%d) slice1 w(%d) slice2 w(%d) slice3(%d) 3%s(#%d) AFBC is not supported idma_reg_print_irqs_msgdpp_dump_regs%s(#%d) DQE: regamma %s %s(#%d) DQE: atc %s %s(#%d) === DQE_%d RCD SFR === [%4d]%4x %s(#%d) POSY: ../google-modules/display/samsung/cal_9855/dqe_reg.c3%s: smc update error %d for %llx exynos_atomic_commit3%s:unable to enter tui without any active crtcs activeplane: rotation=%x zpos=%x alpha=%x blend_mode=%x 3create drm property expected_present_time failed modeset on [CRTC:%u:%s] 3failed to allocate exynos crtc state luminance: min=%d max=%d DPU_EVENT_LOG_ATOMIC_COMMIT6[drm] #%d event log buffers are allocated failed to create debugfs event file %s: DECON%u + verboserange_y_maxZPOS%d%s: pending histogram during hibernation - %s: skipping due to crtc disabled on4%s: unable to enter self refresh (%d) exynos_partial_adjust_region(&decon->worker)->lock3%s[%u]: %s: timeout irq occurs 6%s[%u]: %s - 3%s: fail to get dsim, suppose dsim0 TEdecon_disabledecon_seamless_mode_set3%s: invalid input param(s) 6%s: %s[%d]: attr(0x%lx), port(%d) 6%s: %s[%d]: recovery start(0x%x) cnt(%d) src(%s) mode(%dx%d) %s: mode(%dx%d) %s: %s[%d]: enabled en(%d) dirty(%d) 3%s: %s[%d]: failed to add sysfs hs_clock entries 3%s: %s[%d]: unable to add dsim component 3%s: %s[%d]: unable to register dsi host %s[%d]: rx fifo:0x%8x, response:0x%x, rx_len:%lu 4%s: %s[%d]: RX FIFO is not empty: rx_size:%u, rx_len:%lu %s[%d]: wait for packet payload fifo empty %s[%d]: header(0x%x 0x%x 0x%x) size(%lu) ph fifo(%d) reg-offsetport6dma irq no = %d 4decon%u failed to update bw(%d) to bts(%d) [BTS] AXI_DPU%d = %u [BTS] add DECON%d AXI_DPU%d = %u [BTS] ROT: lat_cycle(%u) %s(#%d) %s: 0x%x decon_reg_set_win_mapcolor3%s(#%d) SoT sync error! %s(#%d) === DSIM %d LINK SFR DUMP(applied to hw) === %s(#%d) -[MC : offset + 0x100]- hdr_reg_set_tm%s(#%d) RNGX: 0x%x hdr_reg_print_oetf_lut[%4d]%8x 3%s(#%d) [idma] timeout sw-reset 4[drm] %s: No windows available for req win cnt=%d->%d (0x%x) dimming_onC83%s: Failed to create dumb of %llu bytes (%ux%u/%ubpp) exynos_drm_gem_mmapobtained fake mmap offset %llu from handle %u valdegamma4%s: decon%u histogram already registered tdr_minscale_modeinvalid partial update region4%s[%u]: failed to parse urgent wr_hi_thres(%d) %s[%u]: can't find rcd node decon_irq_handler6%s[%u]: %s + %s: no private mode config _decon_wait_for_framedone%s[%u]: no planes, enable color map win_id=%d AFBC%s[%d]: total pending packet header(%u) payload(%u) 3%s: %s[%d]: %s failed to get pll-input %s: %s[%d]: pll features: input %llu, optimum%llu %s[%d]: pll features: vco (%llu, %llu) 3%s: %s: invalid reg-base: %s 3%s: %s: wrong number of reg-offset: %d 3%s: %s: failed to read reg-offset 3%s: %s[%d]: Failed to get irq number for err_fg_gpio: %d bist_mode dsim_set_te_pinctrldsim_suspendrangedpu_vote_rt_bw[BTS] DECON%u total bw = %u, read bw = %u, write bw = %u dpu_bts_convert_config_to_info[BTS] -allow_ns(%u) dpu_ns(%u) dpu_bts_deinitdecon_reg_set_win_enable%s(#%d) === DECON_SUB.DSC%d SHADOW SFR DUMP === decon_reg_stop_inst_dsidsim_reg_stop3%s(#%d) (rx_fifo=0x%x) Check DPHY values about HS clk. %s(#%d) %s: video mode set 3%s(#%d) AFBC + ARGB2101010, ABGR2101010 is not supported 3%s(#%d) [odma%d] timeout sw-reset %s(#%d) [%d] green: 0x%x CGC%s(#%d) OFFSETS[%d]: 0x%x noneexpected_present_time size=%dx%d 3create brightness_capability property failedP010_AFBCmapped vaddr: %pK eventblue CMD_ID: 0x%x DATA[0]: 0x%x len: %d%s: histogram: handle event(0x%pK), rstate(%s) [PARTIAL]: %s: partial update is initialized: min rect(%dx%d) slice left(%d) right(%d) afbc_yuv_util_pctdecon_update_dsi_configsw trigger.4%s[%u]: %s + exynos_cgc_dma_register3%s: failed to get cgc dma resource 3%s: %s[%d]: not support AFBC 3%s: %s[%d]: not support CSC 3%s: %s[%d]: not support over %dx scale-up exynos-dsim6%s: %s[%d]: %s - 4%s: %s[%d]: failed on wait for cmd fifo empty (%d) %s: %s[%d]: no need to wait for packet header fifo empty %s[%d]: wait for packet header fifo empty %s[%d]: %s last command %s: %s[%d]: failed to get ERR_FG gpio p-range3%s: %s[%d]: %s failed to get p-range 3%s: %s[%d]: RX ECC Multibit error was detected! 4%s: %s[%d]: error flag detected (decon%d), try to recover (recovering=%d)secexynos_wb_parse_dt%s + dpu_bts_calc_bwdecon_reg_set_pll_sleep4%s(#%d) default outif is set(DSI0) dsim_regs_desc_init3%s(#%d) ECC error, multi-bit(detect, not correct) dqe_reg_print_degamma_luthdr_reg_print3%s(#%d) timeout of CGC COEF DMA request (0x%x) 8bpcOn IRC Onsync_blcolormap%s: decon id is not valid(%d) failed to create debugfs urgent directory matrix %s mode, %s_trigger, out type:0x%x, dsi_mode:%d.(%dx%d@%dhz) crc count(%u)3%s: failed to create a histogram event 3%s: failed to create dqe class enabled(%d) + ctmode[PARTIAL]: %s: reconfigured coordinates: restored partial regionpartial command: [%d %d %d %d] 6%s[%u]: %s[%u]: %s: irq_sts_reg = %x, ext_irq = %x %s[%u]: %s: resource conflict aclkdecon_request_te_irqWBG2Ddpp_checkexynos_gm_update__dpp_disable__dsim_cmd_write_locked%s[%d]: payload length(%lu) %s: %s[%d]: TE from DDI%d 3%s: %s[%d]: %s failed to get k-bits %s[%d]: pll features: input %llu, optimum%llu samsung,exynos9-disp_ss%s[%d]: %s: decon state is %d %s: %s[%d]: %s: decon state is %d dsim_update_clock_config%s[%d]: %s(p:0x%x,m:0x%x,s:0x%x,k:0x%x) %s: %s[%d]: current state: %d 3failed to remap DPU_DMA SFR region 6%s - 6writeback(dpp%d) disabled(%d) 6writeback(dpp%d) already disabled(%d) [BTS] dst x(%u) right(%u) y(%u) bottom(%u) [BTS] -dpu_cycle(%u) aclk_x_1k_ns(%u) dpu_lat_t_ns(%u) 3%s(#%d) timeout of updating decon registers (0x%x) %s(#%d) === DECON_SUB.DSIMIF%d SFR DUMP === decon_reg_wait_run_is_off_timeoutdsim_reg_wait_phy_ready_dlanedsim_reg_wait_exit_ulps_state3%s(#%d) not supported slice mode dsc(%d), slice(%d) dpp_regs_desc_init3%s(#%d) invalid CSC type %s(#%d) [stride] y(0x%x 0x%x) c(0x%x 0x%x) dpp_reg_print_irqs_msg3%s(#%d) ODMA write error irq occur dma_reg_dump_com_debug_regsdqe_reg_print_gamma_matrixdqe_dump%s(#%d) HDR: gammut %s intDolby Vision%s base(%pa) size(%pa) %s: mapped dma_addr: 0x%llx alpha: 0x%x [%6llu.%06lu] %20s CH:%d WIN:%d SRC:%llu%u %s[%dx%d%+d%+d] plane%d/win%d src[%d.%06ux%d.%06u%+d.%06u%+d.%06u] dst[%dx%d%+d%+d] 4%s[%u]: win config[%d] set during handover wr_en6%s[%u]: line delay comp(%d) decon_parse_dtmax_dfs_lv_for_wb%s[%u]: %s - 3%s[%u]: cannot support %d dsc %s[%u]: suspended %s[%d]: rcd state is off cgc-dma,id6%s: %s[%d]: dpp irq no = %d dpp_check_scalelast%s: %s[%d]: + %s: %s[%d]: packetgo disabled m-rangedphy-extra3%s: %s[%d]: failed to remap io region %s[%d]: No dedicated ERR_FG for dsim, skip irq registration dsim_dphy_extra3%s: %s: hs clock %llu out of range 3%s: %s[%d]: could not get main dsi 3%s: %s[%d]: TE error: pinctrl not found 3%s: %s[%d]: invalid TE config for hw trigger mode dsim_runtime_suspend3%s: failed to init writeback connector 6wb(%d) already enabled(%d) dpu_vote_avg_bw[BTS] add DECON%d Overlap BW = %u decon_reg_set_window_control%s(#%d) === DECON%d_MAIN SFR DUMP === 3%s(#%d) failed decon sub ioremap 3%s(#%d) failed wincon ioremap 3%s(#%d) unsupported dsc path decon_reg_read_resource_status3%s(#%d) can't find proper dphy timing(%u Mhz) dsim_reg_wait_phy_ready_clane%s(#%d) unspecified CSC type! -> BT_601 force_bpclp_modemax_avg_luminancememory-regionrot[%d] afbc[%d] format[%d] ch[%u] zpos[%u] comp_src[%llu] %s%s lutTimeUnknown %s: %s[0x%llx] CH%d SRC[%d %d %d %d] %s%s%s6%s: histogram: use cached data exynos_dqe_register%s: histogram: run_state: %s -> %s 4%s: try to enable disp_dither while in_bpc == out_bpc, correct it to "disable" ns3[PARTIAL]: %s: cannot support partial update(%dx%d, %dx%d) exynos_partial_set_sizeexynos_recovery_registerafbc_yuv_rt_util_pct6%s[%u]: found dpp%d dimming_end3Invalid dsim id: %d 4%s[%u]: decon state = %u at resuming %s[%u]: resumed cgc-dma is supported 3%s: %s[%d]: failed to get dma resource %s DPU protection status changed to %du16dsim_phy_power_off3%s: %s[%d]: invalid rx len(%lu) max(%d) dsim_cmd_packetgo_ready_lockeddsim,iderrfg-gpio3%s: %s[%d]: %s failed to get pll-out-range 4%s: %s[%d]: %s: no memory for %u diag items dphy6%s: %s[%d]: %s: hs clock %u, apply now: %u 3%s: %s: p %u is out of range (%u, %u) already in self refresh state. state:%d dsim_attach_bridgedpp,idBT601_525dpu_vote_clock[BTS] Overlap BW%d = %u [BTS] WARN: latency calc is abnormal!(-> %u%%) %s(#%d) dual slice(%d) dsim_reg_stop_and_enter_ulps3%s(#%d) %s : DSIM_status is not IDLE! %s(#%d) escape clock divider is 0x%x 3%s(#%d) [dpp%d] timeout sw-reset dpp_reg_set_bpc3%s(#%d) IDMA cfg err irq occur(0x%x) dqe_reg_print_cgc_lut3%s(#%d) Failed to pack tm_posx hdr_reg_print_eotf_lut%s(#%d) OFFSETS: %s: invalid reserved mask (0x%x) for win_cnt (%d->%d)rcd_plane_idsync_lhbmhbm_modeexynos_drm_gem_dumb_createstate3failed to create gammut matrix directory 6%s: display quality enhancer is not supported exynos_dither_updatestrequested update region&decon->framedone_wait%s[%u]: plane possible_crtcs = 0x%x decon_exit_hibernationDP0%s[%u]: bypass mode: get extra power ref %s[%u]: %s: frame done after: ~%dus (%dhz)decon_enable_vblankdecon_disable_planedecon_set_color_mapdpu_sysmmu_fault_handler3%s: failed to install CGC DMA irq 3%s: %s[%d]: failed to remap HDR SFR region dpp_check_dst_sizetype=0x%02x length=%u last=%d tx=[%s] 4%s: %s[%d]: timed out but payload fifo was empty 3%s: %s[%d]: %pOF: no modes specified 3%s: failed to get dsi resource dsim_get_pinctrlchannellabel6writeback state is off 3failed to install DPU DMA irq 3%s(#%d) failed to perframe_stop(DSI) decon_reg_set_start_crcignored dsim%d crc in protected status sub3%s(#%d) failed to change running status of DECON%d exitidma_reg_set_block_mode3%s(#%d) IDMA AFBC conflict irq occur %s(#%d) ATC configuration hdr_reg_set_hdr../google-modules/display/samsung/cal_9845/hdr_reg.c6tui enabled reject commit(%pK) name trig_mode=%s ddi=%d panel orientationY010_8P2exynos_drm_gem_get_vaddr3%s: Invalid mmap with empty attach! 4unable to add decon_debug sysfs files (%d) 4%s: failed to create %s 3failed to create %s dir lut_writeCOLORchecking plane%d ... min size limitation. width[%d] height[%d] %s[%u]: afbc: rgb_util(%u) yuv_util(%u) rgb_rt_util(%u) yuv_rt_util(%u) 3%s[%u]: failed to install FRAME DONE irq %s: state(%d) 4%s[%u]: unable to get free win_id=%d mask=0x%x %s[%d]: unable to find vaddr cgc-dmadpp_print_restriction6%s: %s[%d]: dma irq no = %d dpp_check_size3%s: %s[%d]: failed to %s protection(ch:%u, ret:%d) %s: %s[%d]: disabled 6%s: %s[%d]: %s + [drm]%s[%d]: long packet was received 6%s: %s[%d]: rx fifo:0x%8x, response:0x%x %s: %s[%d]: %s last command %s: %s[%d]: header(0x%x 0x%x 0x%x) size(%lu) ph fifo(%d) %s: %s[%d]: payload: 0x%x dsim-modes3%s: %s[%d]: could not find child node of dsim-modesmode-namepll-inputdiag-namedesc%s: %s[%d]: framedone irq occurs 3%s: %s[%d]: Request err_fg irq number(%d) failed: %d %d:%s6dst_w[%d %d %d] dst_h[%d %d %d] dst_x_y_align[%d %d] BT601_525_UNADJUSTEDExtendedhw restrictions[BTS] DSC: lat_cycle(%u) ../google-modules/display/samsung/exynos_drm_crtc.c../google-modules/display/samsung/exynos_drm_dpp.cdecon_reg_stop_perframe_dsi3%s(#%d) SBWC + RGB format is not supported %s(#%d) DQE: %s dither %s NAexynos-drmcolor modehistogram_thresholdwidth(%d), height(%d), pitches(%d) disabling [ENCODER:%u:%s] NV12_AFBC (off) 6%s: port: %s, dest: %s force_enablegammutSECURECHs: DISABLED6%s: display quality enhancer is supported(DQE_V%d) %s: decon state: %d + exynos_crtc_self_refresh_update3[PARTIAL]: %s: failed to initialize partial update reconfigured coordinates: %s[%u]: DECON state is not On(%d) decon%u_kthread4%s[%u]: failed to parse urgent rd_lo_thres(%d) %s[%u]: WARN: bus_util_pct is not defined in DT. 3%s[%u]: can't find dpp%d structure %s[%u]: can't find rcd structure decon6%s[%u]: dimming end irq is not supported decon_binddecon_update_configDual DSI_decon_handover_checkdecon_disable_win%s[%d]: dpp is protected %s: cgc-dma is supported 3%s: %s[%d]: not support under 1/%dx scale-down 3%s: %s[%d]: not supported source alignment %s: %s[%d]: wait for packet payload fifo empty 4%s: %s[%d]: timed out but header fifo was empty need_wait_vblank%s: %s[%d]: packet go ready (ph: %d, pl: %d) dsim_register_irqDPU_UNDERRUN3%s: %s[%d]: failed to enable dphy(%d) hs_clockdsim_update_config_for_modereg-namesdmawriteback_bind../google-modules/display/samsung/exynos_drm_bts.c%s(#%d) win id = %d 3%s(#%d) failed to change off status of DECON%d %s(#%d) TEN_BPC=%d : A=%02Xh, R=%03Xh, G=%03Xh, B=%03Xh 3%s: invalid bit range [%u, %u] 3%s(#%d) Error to enable PHY lane(err=%d) 3%s(#%d) type(%d): id(%d) %s(#%d) === DPP%d SHADOW SFR DUMP === dqe_reg_print_regamma_luthdr_reg_set_gm%s(#%d) COEFFS[%d]: 0x%x %s(#%d) POSX: cal_write3%s: not in tui charwait_for_fencescgc_lut_fdoffset(%d), handle(%d), size(%lu) XRGB8888force_te_onoffsets [%d %d %d %d] ecc count(%u)RCDDST[%d %d %d %d] dpu_itmon_check3%s: failed to remap dqe registers 3%s: failed to create to atc sysfs device threshold_2../google-modules/display/samsung/exynos_drm_partial.cpartial[%dx%d] vporch[%d %d %d] hporch[%d %d %d] 6[RECOVERY] %s: recovery is successfully finished(%d) unbalanced te irq (%d) 6%s[%u]: successfully probed3%s[%u]: failed to parse max windows count 6%s[%u]: PPC(%u) delay_scaler3%s[%u]: failed to map sysreg-disp address.6%s[%u]: failed to get aclk_disp(optional) decon_enter_hibernation%s[%u]: new win_id=%d zpos=%d mask=0x%x %s[%d]: framebuffer not found cgc-dma is not supported 3%s: %s[%d]: probe failed6%s: %s[%d]: src_f_w[%d %d %d] src_f_h[%d %d %d] 6%s: %s[%d]: dst_f_w[%d %d %d] dst_f_h[%d %d %d] 3%s: %s[%d]: failed to install DPP irq 3%s: %s[%d]: failed to add sysfs bist_mode entries 3%s: %s[%d]: read timeout dsim_of_get_clock_modepll-optimumdsim_of_parse_diag3%s: %s: empty diag-name dsim_underrun_infounderrun irq occurs(%u): MIF(%lu, %d), INT(%lu, %d), DISP(%lu, %d) hw_te_on3%s: %s[%d]: failed to get hw_te_off pin state %s: %s[%d]: underrun_lp_ref 0x%x dsim_encoder_enable_dsim_enter_ulps_lockedexynos_tui_releaseexynos-writeback6src_w[%d %d %d] src_h[%d %d %d] src_x_y_align[%d %d] odma_irq_handlerBT601_625[BTS] final: avg %u, rt %u 3[BTS] [%s] undefined decon id(%u)! ../google-modules/display/samsung/cal_9845/dsim_reg.c%s(#%d) === DECON%d_MAIN SHADOW SFR DUMP === %s(#%d) = DECON_SUB.DSIMIF%d SHADOW SFR DUMP = decon_wincondecon_reg_set_winmap3%s(#%d) False control error! dsim_reg_wait_hs_clk_disable__dphy_dump3%s(#%d) ODMA deadlock error irq occur 3%s(#%d) ODMA cfg err irq occur(0x%x) dma_dump_regsdqe_reg_set_regamma_lutdqe_reg_set_linear_matrixdqe_reg_set_histogram%s(#%d) RNGY: 0x%x hdr_reg_print_gm3%s(#%d) CGC DMA read error irq occur dqe_reg_wait_cgc_dma_done_internalhistogram_weightswait_for_flip_donesrc[%d %d %d %d], dst[%d %d %d %d] 3%s: Failed to mmap with offset %lu. 3%s: Failed to create a handle of GEM failed to initialize plane 4[drm] failed to alloc event log buf[%d]. retry OFFlt[PARTIAL]: %s: %s[%dx%d%+d%+d] reconfigure(%d) 3[PARTIAL]: %s: invalid min size(%dx%d) of partial update dfs_lv6%s[%u]: failed to get aclk(optional) decon_disable_vblank3%s[%u]: bypass mode only supported in self refresh %s[%d]: %s - %s: %s[%d]: - 3%s: %s: failed to read bit-range 3%s: failed to get dphy resource 3%s: %s[%d]: failed to map sysreg-disp address.6%s: %s[%d]: Request err_fg irq number(%d) okay dsim_err_fg_irq_handlerdsim_calc_underrundsim_bindvideodsim_encoder_disable3%s: %s[%d]: failed to control decon TE(%d) %s: %s[%d]: state: %d [TUI Driver] %s ../google-modules/display/samsung/cal_9845/dpp_reg.cdecon_reg_set_interrupts__decon_dump3%s(#%d) Not specified case for Partial Update dsc_get_partial_update_info4%s(#%d) decon%d RSC_STATUS_2: SEL_WIN = 0x%x 3%s(#%d) DSIM status is not IDLE! 3%s(#%d) mode[%d] doesn't support multi resolution dsim_reg_set_clocks6%s(#%d) DPHY PLL is already stable 3%s(#%d) The ddi(%d) doesn't support ULPS dsim_reg_print_size_of_slice%s(#%d) -[CMD 2 : offset + 0x100]- dqe_reg_set_cgc_lut3%s(#%d) Failed to pack regamma %d element %s(#%d) [%d] blue: 0x%x dqe_reg_print_dumpfence: %s-%s %llu-%llu status:%s BT2100 HLGBGRA8888underrun_cnt[%08lX] green3failed to create gammut directory %s %s%s %s %s pending_framedoneexynos_linear_matrix_updateDisplay hibernation handler is called This panel doesn't support partial update feature partial update is initialized: min rect(%dx%d) %s[%u]: WARN: rot_util_pct is not defined in DT. hdrdma_irq_handler4%s: %s[%d]: timeout: packet header fifo empty Not%s[%d]: PL_FIFO_EMPTY irq occurs 3%s: %s[%d]: failed to get dsim phy dsim_get_phys3%s: %s[%d]: failed to get possible crtc, ret = %d %s: %s[%d]: disable right after self refresh. state:%d %s: %s[%d]: op mode change not allowed seamlessly %s[%d]: state: %d dpu_vote_peak_bw[BTS] DISP bus freq(%u), operating freq(%u) [BTS] -tx_allow_t_ns(%u) rot_init_bw(%u) rot_need_clk(%llu) %s(#%d) regs->ch(%d) __decon_init_resources3%s(#%d) failed to get sub resource wincon%s(#%d) requested escape clock %u MHz 3%s(#%d) DSI Master clock isn't disabled. 3%s(#%d) DSI Master is not stop state. dsim_reg_set_size_of_sliceidma_reg_wait_sw_reset_status3%s(#%d) IDMA read error irq occur %s(#%d) === DPU_DMA%d SHADOW SFR DUMP === %s(#%d) === DPU_DMA(RCD%d) SFR DUMP === %s(#%d) POSY[%d]: 0x%x %s(#%d) block x(%d) y(%d) w(%d) h(%d) 3%s: failed to atomic commit suspend_state(0x%x) no partial region request sync_ghbmbrightness_capabilityfailed to get reserve memory phandle rmem_device_initconnector_commit[CRTC-%d] new en:%d active:%d change[%d %d %d] ARGB2101010oetf../google-modules/display/samsung/exynos_drm_debug.c%s, block_cnt(%d) cgc3failed to create atc directory ID:%u mst_security:%#x PID: %dBUFFER3%s: failed to find crtc object exynos_partial_updatechanged full: requested region is bigger [PARTIAL]: %s: align limitation. src_x/y[%d/%d] align[%d] 3%s[%u]: can't find dpp%d node %s[%u]: %s: frame start unbalanced te irq %s[%u]: %s: final win_mask=0x%lx %s[%u]: disabling winid:%d %s[%u]: in/out/force bpc(%d/%d/%d) 3%s: %s[%d]: src[%d %d %d %d %d %d] dst[%d %d %d %d %d %d] fmt[%d] %s: %s[%d]: ch:%u, en:%d 6%s: %s[%d]: dsim idle_ip_index[%d] dsim_cmd_packetgo_queue_lockeddsim_mode%s: %s[%d]: No dedicated ERR_FG for dsim, skip irq registration dsim_calc_pmsk%s: %s: underrun_param for mode "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x not specified4%s: %s[%d]: %s: seamless mode switch not supported for %s 6attr(0x%lx), port(%d) 3failed to get dpp resource BT2020_CONSTANT_LUMINANCE[BTS] COMP: lat_cycle(%u) ../google-modules/display/samsung/exynos_drm_gem.cwin3%s(#%d) failed decon win ioremap decon_sub3%s(#%d) failed to reset decon%d dsim_reg_rx_err_handler3%s(#%d) SoT error! dis%s(#%d) DSI Master is ULPS state. 3%s(#%d) SBWC is not supported odma_reg_wait_sw_reset_status3%s(#%d) BT601 with limited range is set as default dqe_reg_set_degamma_lut%s(#%d) [%d]: 0x%x %s(#%d) ROI position start x,y(%d,%d) plane: crtc-pos=%dx%d%+d%+d dqe_enabled type=0x%x failed to create colormap gem failed to lookup gem object offsets[%d](%d) size(%zd) obj[%d]->size(%zd) modesetmapped dma_addr: 0x%llx IDMA_ERRORregammahistogramtone_mapping minimum rect size[%dx%d]6%s: histogram: idle, query now %s: enabled(%d) + hiber_blk_cntexynos_hibernation_exit[PARTIAL]: %s: plane mask[0x%x] exynos_partial_find_included_slicedecon_mode_update_btsrd_wait_cyclewr_lo_thres3%s[%u]: failed to parse dta_hi_thres(%d) 6%s[%u]: DPU DFS Level : dpps3%s[%u]: failed to get main resource 6%s[%u]: dimming start irq is not supported TE from DDI%d [drm] %s: handover memory defined, but no windows attached 3%s[%u]: framestart timeout (%dhz), recovering: %d, pending: %d early_wakeup_storedecon_resume4%s[%u]: decon state = %u at suspending %s[%d]: === old buffer dump[%s:%s]: dma addr 0x%pad, vaddr 0x%p === 3%s: failed to remap cgc-dma registers 6%s: %s[%d]: max scale up(%dx), down(1/%dx) ratio 3%s: %s[%d]: support rotation only for YUV420 format %s: %s[%d]: in/force bpc(%d/%d) u8dsim_dsim_disable%s[%d]: packet go ready (ph: %d, pl: %d) te_from%s[%d]: framedone irq occurs %s[%d]: failed to get pinctrl (%d) %d %s[%d]: %s(hs:%d,esc:%d) enabled%s[%d]: disable right after self refresh. state:%d 3%s: unable to get decon UnspecifiedAdobe RGBexynos_drm[BTS] MAX DISP CH FREQ = %u dpu_bts_sum_all_decon_bw%s(#%d) === DECON_WIN%d SHADOW SFR DUMP === decon_reg_wait_run_status_timeout3%s(#%d) ECC error, single-bit(detect and correct) %s(#%d) bps(%u) clk_prepare(%u) clk_zero(%u) clk_post(%u) 3%s(#%d) PHY %s failed[timeout] dsim_reg_wait_hs_clk_ready%s(#%d) shadow addr 1p(0x%x) 2p(0x%x) 3p(0x%x) 4p(0x%x) %s(#%d) h_ratio : %#x, v_ratio : %#x %s(#%d) [Green] 3%s: there is no suspend_state Offsync_refresh_ratebrightness_levelwait_for_crtc_flipRGBX8888NV12exynos_drm_gem_mmap_object3%s: Failed to create mmap fake offset for handle %u win_id=%d %d[%c] exynos_regamma_updatehibernation3failed to map camera operation register [PARTIAL]: %s: This panel doesn't support partial update feature final update regionexynos_partial_send_command4%s[%u]: failed to parse urgent rd_en(%d) dta_lo_thresrot_util%s[%u]: WARN: afbc_rgb_util_pct is not defined in DT. 4%s[%u]: WARN: DPU DFS Info is not defined in DT. frame_transferaclk-disp6%s[%u]: already enabled(%d) %s[%u]: reuse existing win_id=%d zpos=%d mask=0x%x wait for earliest present time%s[%d]: dpp state is off 3%s: %s[%d]: failed to get hdr resource exynos_oetf_updateboolpayload%s: %s[%d]: %s + 3%s: %s[%d]: fifo would be full. ph(%u) pl(%lu) max(%d/%d) dsim_of_parse_modes3%s: %s[%d]: %s failed to get s-range %s: %s[%d]: pll features: output(%llu, %llu) %s: %s[%d]: pll limits: p(%u, %u), m(%u, %u), s(%u, %u), k(%u) 4%s: %s[%d]: %s: decon is NULL %s: %s[%d]: failed to get pinctrl (%d) 3%s: %s[%d]: invalid bist mode 3%s: %s[%d]: Unable to attach panel bridge writeback_disable[BTS] peak = %u, rt = %u, read = %u, write = %u %s(#%d) === DECON_SUB.DPIF%d SFR DUMP === %s(#%d) = DECON_SUB.DSC%d SFR DUMP = %s(#%d) %s: dsc configuration is set dsim_dphy_diag_mask_from_range3%s(#%d) %u Mhz can't be used as escape clock %s(#%d) %s: checked = %d Dither%s(#%d) %s: ignored in protected status %s(#%d) HDR: oetf %s exynos_drm_bind6encoder[%d] type(0x%x) possible_clones(0x%x) Post DQELeft Side Uphdr_formatscrtc_disableBGR565BGRA1010102exynos_drm_gem_prime_import_sg_table decon_id=%d max_luminancedsim_diag_create_debugfsredread %d bytes from userspace 3failed to create histogram directory range_y_minswremained event(0x%pK) pending histogram during hibernation pl_w1pp_endstep(%u), actual dstep(%u), vrefresh(%d) threshold_1_exynos_hibernation_runscaling is detected. partial->full _decon_mode_update_bts_handoverdta_en4%s[%u]: WARN: scaler ppc is not defined in DT. 3%s[%u]: failed to get sys resource DSI0exynos-dppdpp_updateset_resource_protection%s[%d]: === DSIM SFR DUMP === 3%s: %s[%d]: failed to disable dphy(%d) dsim_wait_for_cmd_fifo_empty%s: %s[%d]: PH_FIFO_EMPTY irq occurs 6%s: %s[%d]: dsim handover. skip_init=%d dsim_phy_power_on3%s: %s[%d]: Failed to update underrun dsim_runtime_resume3[TUI Driver] failed to enter TUI 4wb(%d) instant off irq occurs DCI-P3../google-modules/display/samsung/exynos_drm_dsim.cdecon_regs_desc_initdecon_reg_set_mresdecon_reg_set_data_path3%s(#%d) Invalid transmission length! dpu_sysreg_select_dphy_rst_control%s(#%d) b_dphyctl(%u) 3%s(#%d) PHY clock lane is not ready[timeout] 3%s(#%d) not support attribute(0x%lx) %s(#%d) base addr 1p(0x%lx) 2p(0x%lx) 3p(0x%lx) 4p(0x%lx) %s(#%d) [Blue] %s(#%d) HDR: tone mapping %s 3%s(#%d) CGC DMA deadlock irq occur exynos_atomic_check_windowsdpu_find_fmt_infoexynos_drm_gem_alloc3%s: Failed to find DMA-BUF system heap 3%s: invalid decon cgc_dither3failed to create %s matrix directory coeff_rON enable(%d) active(%d) sr(%d) [p:%d m:%d a:%d c:%d]%s: remained event(0x%pK) histogram_set_run_statehistogram: run_state: %s -> %s exynos_hibernation_cancelexynos_plane_print_infobus_width%s[%u]: WARN: afbc_yuv_util_pct is not defined in DT. dfs_lv_cnt%s[%u]: found rcd: dpp%d 3%s[%u]: failed decon ioremap %s[%u]: switch to mode %s can be seamless 4%s[%u]: %s: dpp is owned by decon #%d dpp,video3%s: %s[%d]: failed to remap DPP SFR region 3%s: %s: invalid reg_base %u cmd%s[%d]: no need to wait for payload fifo empty 4%s: %s[%d]: warning. changed last command. pend pl/pl(%u,%u) new pl(%zu) %s[%d]: last(%lld) cur(%lld) diff(%lld) ready allow period(%d) 3%s: %s[%d]: %s failed to get m-range %s: %s[%d]: pll features: vco (%llu, %llu) 3%s: %s[%d]: failed to install DSIM irq dsim_irq_handler3%s: %s: no proper s found %s: %s[%d]: preferred panel is %s %s[%d]: dsc change not allowed seamlessly 3[TUI Driver] failed to exit TUI %s - wb(%d) framedone irq occurs Limiteddpu_bts_update_disp_ch_bw../google-modules/display/samsung/cal_9845/decon_reg.cdecon_reg_wait_update_done_timeout%s(#%d) slice mode change(%d) 6%s(#%d) clearing dsimif%u sel, val: %u decon_reg_reset3%s(#%d) DSI VC ID invalid! %s(#%d) === DSIM %d LINK SFR DUMP === %s(#%d) hs_trail(%u) lpx(%u) hs_exit(%u) __dpp_checkdpp_reg_wait_sw_reset_statusR2Yhdr_reg_set_oetf_lut Decon #%u (state:%d) histogram_posOn IRC Offexynos_drm_fb_dma_addr4[drm] %s is not proper format for colormap [CRTC-%d] old en:%d active:%d change[%d %d %d] system3%s: Failed to mmap imported buffer: %d DPP #%dHLGdpu_itmon_notifierdumpverbose_count3failed to create cgc lut directory mif(%lu) int(%lu) disp(%lu) peak(%u,%u) rt(%u,%u) total(%u,%u)6display hibernation is supported %s: %s took %lldus [PARTIAL]: %s: reconfigure(%d) rotation is detected. partial->full slice[%d] is %s 6%s[%u]: %s mode. %s %s output.(%dx%d@%uhz, bts %uhz) %s[%u]: %s %s[%d]: disabled &dsim->cmd_lock%s[%d]: packetgo disabled %s: %s[%d]: short packet was received %s[%d]: payload: 0x%x 6%s: %s[%d]: already enabled(%d) 3%s: %s[%d]: failed to enable ext dphy(%d) 4%s: %s[%d]: cmd_underrun_cnt is not set correctly dual-dsimain%s: underrun_param for mode "%s": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x not specified%s: %s[%d]: state: %d self_refresh: %d->%d dsim_resume6writeback(dpp%d) successfully probe../google-modules/display/samsung/exynos_drm_writeback.cattrdppexynos_drm_writeback_destroy_state[BTS] -line_t_ns(%u) v_blank_t_ns(%u) 3win config is invalid 6%s(#%d) pll wake-up is not allowed 4%s(#%d) decon%d RSC_STATUS_5: SEL_DSCC = 0x%x 3%s(#%d) CLK lane doesn't be switched to LP mode 3%s(#%d) HS receive timeout error! 3%s(#%d) dsim%d function reset timeout %s(#%d) -[BIAS]- %s(#%d) -[MD 3 : offset + 0x100]- %s(#%d) 0x%4x 0x%4x 0x%4x 3%s(#%d) DPP cfg err irq occur(0x%x) dqe_reg_print_lutexynos4crtc[%s]: skipping duplication of inactive crtc state exynos-crtc-%u dsi_mode=%s (%d) is_partialBGRX88883%s: failed to get dma buf exynos_drm_gem_create3%s: Failed to lookup gem object from handle %u. SMPTE 170MGamma 2.8[%08X] linear_matrix3failed to create regamma lut directory WIN off[PARTIAL]: %s: clipped src[%d.%06ux%d.%06u%+d.%06u%+d.%06u] dst[%dx%d%+d%+d] rd_lo_thresframe_startdecon_enable4%s[%u]: seamless not possible for mode %s decon_atomic_begindecon_unbind6%s: %s[%d]: src_h_rot_max[%d] 3%s: %s[%d]: rot[0x%x] comp_type[%d] exynos_eotf_updateexynos_tm_update%s: %s[%d]: EoTp was received dsim_write_payload3%s: %s: m %u is out of range (%u, %u) %s: %s[%d]: %s(p:0x%x,m:0x%x,s:0x%x,k:0x%x) %s: %s[%d]: %s(hs:%d,esc:%d) %s[%d]: preferred panel is %s %s[%d]: clock mode change not allowed seamlessly writeback_atomic_commit[BTS] SCALE: lat_cycle(%u) decon_reg_set_pll_wakeup3%s(#%d) failed to inst_stop(DSI) %s(#%d) === DECON_WINCON%d SFR DUMP === 3%s(#%d) DSI data type not recognized! %s(#%d) -[CMD 1 : offset + 0x100]- dpp_reg_set_csc_paramsdma_reg_set_base_addr%s(#%d) === DPU_DMA(CGC%d) SFR DUMP === %s(#%d) [%d] red: 0x%x %s: %d: pos(%d) __data_loc char[]%s: visible_win_mask(0x%x) max_disp_freqexynos_crtc_atomic_checkfailed to allocate exynos connector state Right Side Up3failed to reserve memory lookup itmon,portcoeffs te cnt(%u)exynos_gamma_matrix_updatetdr_maxexynos_hibernation_suspend[PARTIAL]: %s: plane%d/win%d src[%d.%06ux%d.%06u%+d.%06u%+d.%06u] dst[%dx%d%+d%+d] clipped src[%d.%06ux%d.%06u%+d.%06u%+d.%06u] dst[%dx%d%+d%+d] %s[%u]: seamless mode change from %dhz to %dhz 3%s[%u]: failed to run display thread wr_hi_thres%s[%u]: plane idx[%d]: alpha(0x%x) hw alpha(0x%x) 3%s: %s[%d]: failed to get dpp resource __dpp_enabledpp[%u] mst_security: %#x dpp_bindtx_buf%s[%d]: enabling packetgo %s: %s[%d]: enabling packetgo 4%s: %s[%d]: force batching is attempted in video mode 4%s: %s[%d]: failed to remap io region. it's optional dsim_set_display_mode%s[%d]: dsim mode %s dsc is %s [%d %d %d %d] scale_downdpu_bts_calc_dpp_bw[BTS] DPP%d bandwidth: avg %u, rt %u, rot %u 3invalid RCD AXI channel number %u dpu_bts_calc_rotate_aclk../google-modules/display/samsung/exynos_drm_drv.c3%s(#%d) Escape mode entry command error! dsim_reg_function_reset3%s(#%d) %s is timeout. dsim_reg_wait_idle_status%s(#%d) size(%ux%u) %s(#%d) COEFFS: exynos_atomic_enter_tui(null) bpc=%d 10bpcoetf_lutfailed to create debugfs recovery file gamma_matrix%d 3%s: failed to get dqe from decon%u ../google-modules/display/samsung/exynos_drm_dqe.catc__exynos_dqe_updateexynos_partial_check[PARTIAL]: %s: min size limitation. width[%d] height[%d] 4%s[%u]: failed to parse urgent wr_lo_thres(%d) 3%s[%u]: failed to parse dta_lo_thres(%d) ppc_scalerbus_util[drm] %s: planes updated on commit, skipping handover couldn't find win id (%d) for zpos=%d plane_mask=0x%x SBWC%s: %s[%d]: rx fifo:0x%8x, response:0x%x, rx_len:%lu %s[%d]: EoTp was received __dsim_wait_for_ph_fifo_empty%s: %s[%d]: last(%lld) cur(%lld) diff(%lld) ready allow period(%d) dsim_write_data_dual3%s: %s[%d]: %s failed to get pll-vco-range dsisyshw_te_off%s: %s[%d]: found proper pll parameter reg%s[%d]: op mode change not allowed seamlessly scale_up6%s + dpu_bts_find_nearest_high_freq%s(#%d) number of DSC slice(%d) __dsim_dumpdsim_reg_enable_pll3%s(#%d) failed to %s ULPSenter%s(#%d) %d bpc mode is set %s(#%d) weight red(%d) green(%d) blue(%d) Shift%s(#%d) %s + %s(#%d) POSX[%d]: 0x%x %s: win cnt changed: %d -> %d %s: current win_mask=0x%x new=0x%x avail=0x%x fence: err=%d Pre DQE%s:%d, dma_addr[%d] = 0x%llx (+0x%x) exynos_drm_gem_fd_to_objexynos_drm_gem_dumb_map_offsetGamma 2.2eotfposxposyEvent ID CH:%d, WIN:%d, %sAFBC dqe%uidle%s: DPU power %s exynos_partial_reconfig_coords6[RECOVERY] %s: starting recovery... 4%s[%u]: failed to parse urgent wr_en(%d) 3%s[%u]: failed to find disp_ss node3%s[%u]: failed to install EXTRA irq decon_fs_irq_handler%s[%u]: seamless mode set to %s %s: cgc-dma is not supported GPU6%s: %s[%d]: dst_w[%d %d %d] dst_h[%d %d %d] dst_x_y_align[%d %d] %s[%d]: in/force bpc(%d/%d) enable%s[%d]: %s + 3%s: %s[%d]: could not get secondary dsi __dsim_cmd_packetgo_enable_locked%s[%d]: no need to wait for packet header fifo empty pmskdphy_diagreg-basehelpdsim_dphydisabled4%s: %s[%d]: %s: mode set is only supported w/exynos connector %s: %s[%d]: clock mode change not allowed seamlessly 3%s: %s[%d]: failed to create panel bridge FILM[BTS] [Run: D%u] resol clock = %u Khz @%u fps dpu_bts_update_overlap_bw../google-modules/display/samsung/exynos_drm_hibernation.c6%s(#%d) pll sleep is not allowed 6%s(#%d) op mode[%d] doesn't support multi resol dsim_reg_set_ulps_by_ddi%s(#%d) -[CMD 0 : offset + 0x100]- dpp_reg_deinitdma_reg_get_shd_addrdpp_reg_set_scale_ratioodma_reg_print_irqs_msg%s(#%d) === DPU_DMA%d SFR DUMP === rcd_dma_dump_regsdqe_reg_init%s(#%d) DQE: histogram EN(%d) ROI_ON(%d) LUMA_SEL(%d) rcd_reg_set_block_mode%s: avail_win=0x%x freed_mask=0x%x Samsung SoC DRMEXYNOS_HISTOGRAM_CANCEL reserved_win_mask=0x%x vidfailed to initialize framebuffer 6[drm] %s: can't find format(%d) in supported format list ABGR2101010DPU_EVENT_LOGecc_cntidma_err_cntitmon,destcoeff_brange_x_max---------------------------------------------------- DPU POWER:%s DSIM STATE:%u DSIM POWER:%sSECURE enexynos_partial_initadjusted update region[PARTIAL]: %s: checking plane%d ... %s[%u]: %s: configure bts for handover max_windta_hi_thresppc_rotator6%s[%u]: rotator ppc(%d) 6%s[%u]: scaler ppc(%d) afbc_rgb_util_pct_decon_stop_locked%s[%u]: TE irq number(%d) header6%s: %s[%d]: driver has been probed. dsim_read_datas-rangebit-range6blk_w[%d %d %d] blk_h[%d %d %d] blk_x_y_align[%d %d] exynos_drm_writeback_duplicate_statedpu_bts_release_resources[BTS] %s + : DECON%u dpu_bts_get_vblank_time_ns[BTS] DPP%d : bpp(%u) src w(%u) h(%u) rot(%d) afbc(%d) yuv(%d) [BTS] [ROT-] AFTER latency check: %llu KHz decon_dsc_reg_init%s(#%d) OUTIF is WB dsim%u: PLL_EN is not %sable %s(#%d) threshold: %d %s(#%d) DQE: gamma matrix %s hdr_reg_set_eotf_lutpid%c|%d|%s|%d errorcgc_lutpartial_regionsync_noneexynos_rmem_registerP010allocated %zu bytes with flags %#x blockmin_luminance6%s: power %s state underrun: %u crc: %u ecc: %u idma_error: %u CH:%u WIN:%u SRC:%s COUNT:%uROT histogram: created event(0x%pK) of decon%u histogram_cancel_ioctlterminated histogram event of decon%u histogram: handle event(0x%pK), rstate(%s) dqeforce_updateambient_lightoverride-hibernationcamera-operationexynos_hibernation_enterexynos_hibernation_handlerplane mask[0x%x] in6[RECOVERY] %s: ESD recovery is supported exynos_recovery_handlerdecon_seamless_mode_bts_update4%s[%u]: WARN: comp line delay is not defined in DT. 6%s[%u]: %6d rcd%s[%u]: bypass mode: drop extra power ref %s[%u]: %s + decon_suspend6%s: %s[%d]: successfully probed6%s: %s[%d]: blk_w[%d %d %d] blk_h[%d %d %d] blk_x_y_align[%d %d] 3%s: %s[%d]: failed to install DPU DMA irq dpp_convert_plane_state_to_config%s: en(%d) dirty(%d) 3%s: %s[%d]: failed to get protection id(%u) set_protection4%s: %s[%d]: idle ip index is not provided 3%s: %s[%d]: unable to create dsi packet (%d) esc-clk&x->waitdsim_register_err_fg_irq%s[%d]: current state: %d 6dst_f_w[%d %d %d] dst_f_h[%d %d %d] dpu_bts_find_max_disp_freqdecon_reg_clear_dsimifdecon_reg_set_bpc3%s(#%d) EoT error! %s(#%d) %s - 3%s(#%d) CGC DMA cfg err irq occur dqe_reg_set_histogram_pos_internalfence: timestamp:%lld.%09ld EXYNOS_HISTOGRAM_REQUESTmodeset on [ENCODER:%u:%s] Display P3simplified rot[0x%x] rot[%d] afbc[%d] format[%u] ch[%u] comp_src[%llu] NV21not supported modifier(0x%llx) sRGBeotf_lutdsim%d3failed to create dqe directory 3failed to create regamma directory 3failed to create %s directory WINs: req[%d %d %d %d] adj[%d %d %d %d] prev[%d %d %d %d]%s: en(%d) dirty(%d) vrefresh(%d) dstep(%d/%d) exynos_cgc_updatepl_w2upgrade_on%s: aborted due to normal commit pending [PARTIAL]: %s: rotation is detected. partial->full %s[%u]: update decon bts config for mode: %dx%dx%d 4%s[%u]: failed to parse urgent rd_hi_thres(%d) 4%s[%u]: WARN: rotator ppc is not defined in DT. frame_done3%s[%u]: %s: failed to pm_runtime_get_sync 4TE from DDI is not valid (%d) DSI1decon%d: wait for frame done timed out (%dhz)decon_update_planedecon_runtime_suspend6%s: %s[%d]: src_w[%d %d %d] src_h[%d %d %d] src_x_y_align[%d %d] typedsim_probe3%s: %s[%d]: failed to request dsi read command 3%s: %s[%d]: %s failed to get pll-optimum 3%s: %s[%d]: failed to get hw_te_on pin state 3%s: %s[%d]: Failed to update pll for hsclk %d dsim_add_mipi_dsi_devicedsim_mode_is_seamless%s: %s[%d]: dsc change not allowed seamlessly 6src_h_rot_max[%d] exynos_drm_writeback_reset[BTS] Max Overlap BW = %u, Max AXI_DPU = %u [BTS] aclk_base is greater than L0 frequency!dpu_bts_update_resources%s(#%d) %s: WINCON%d = 0x%x %s(#%d) === DECON_WIN%d SFR DUMP === 4%s(#%d) decon%d RSC_STATUS_4: SEL_DSC = 0x%x %s(#%d) clk_trail(%u) hs_prepare(%u) hs_zero(%u) Y2R%s(#%d) -< DMA COMMON DEBUG SFR >- %s(#%d) DQE: cgc %s dqe_reg_set_gamma_matrixdqe_reg_print_atc%s(#%d) === DQE_%d HIST SFR === hdr_reg_print_tm../google-modules/display/samsung/cal_9855/dpp_reg.cmmaped the offset %lu of size %lu to %#lx [%2d] %4x %14s %20s %20s Remarks CH:%u WIN:%uhw CH%u: 0x%llx, %ux%u, ZPOS%u, %s4%s: invalid number: %d %s: terminated histogram event of decon%u %s: - exynos_hibernation_check%s[%u]: bus_width(%u) bus_util(%u) rot_util(%u) %s[%u]: max_dfs_lv_for_wb(%u) decon-ss%s[%u]: %s: frame done decon%d3Unable to support DSI along with out_type: 0x%x 3Unsupported encoder type: %d command%s[%u]: %s: exceed 1 TE period for %dhz decon_check_modesetdpp_probeexynos_dpp_parse_dt%s[%d]: ch:%u, en:%d &dsim->state_lock3%s: %s[%d]: failed to disable ext dphy(%d) 3%s: %s[%d]: runtime resume failed (%d). unable to transfer cmd dsim_write_data_locked%s: %s[%d]: total pending packet header(%u) payload(%u) dsim_pktgo_wait_vblankdsim_of_get_pll_features4%s: %s[%d]: %s: diag parsing error for item %u read_onlybist_mode_store%s: %s[%d]: dsim mode %s dsc is %s [%d %d %d %d] BT470M[BTS] %s - decon_reg_stop%s(#%d) = DECON_SUB.DPIF%d SHADOW SFR DUMP = 3%s(#%d) %s invalid config (null) dsim_reg_set_config3%s(#%d) DSI Master is not HS state. %s(#%d) ---[%s CSC Type: std=%d, rng=%d]--- dqe_reg_print_ditherBT2100 PQpanel_idle_supportUpside Downexynos_user_fb_createexynos_atomic_commit_tailRGBA8888RGB565%s: allocated %zu bytes with flags %#x 3%s: Unable to import created DMA-BUF heap buffer exynos_drm_gem_offsetexynos_plane_atomic_checktransfercounters disp(%u) peak(%u) rt(%u) read(%u) write(%u) %uhz (crtc: %uhz) underrun count(%u)4%s: invalid win state %d handle_histogram_eventdither%s: block_cnt(%d) 6display hibernation is not supported 6doesn't need to get camera operation register exynos_partial_prepare4%s[%u]: failed to parse urgent rd_wait_cycle(%d) %s[%u]: max_dfs_lv_for_wb is not defined in DT. connectorextradecon_te_irq_handler3%s[%u]: unsupported decon output (%d) 4decon%u scheduler late to service fs irq handle (%d fps) decon_runtime_resume3%s: %s[%d]: failed to remap DPU_DMA SFR region 3%s: %s[%d]: not supported source size range dsim_dphy_diag_get_regheader=%d payload=%d %s[%d]: + dsim_host_transfer%s[%d]: payload: 0x%x i=%d max=%d %s[%d]: pll limits: p(%u, %u), m(%u, %u), s(%u, %u), k(%u) 3%s: %s: invalid bit range %d, %d 6%s: %s[%d]: 0:Disable 1:ColorBar 2:GRAY Gradient 3:UserDefined ../google-modules/display/samsung/exynos_drm_tui.c%s wb_convert_connector_state_to_configwriteback_enableBT2020writeback_unbind[BTS] Nearest DFS: %u KHz @L%d decon_reg_wait_idle_status_timeout3%s(#%d) failed to get wincon resource dsc_reg_set_encoder4%s(#%d) undefined blending mode %s(#%d) %s: phy_con_sel val=0x%x3%s(#%d) dsim%d wait timeout idle status %s(#%d) === DSIM %d DPHY SFR DUMP === %s(#%d) Table red(%c) green(%c) blue(%c) %s(#%d) COEFF: 0x%x cal_write_relaxedrcd_reg_wait_sw_reset_statuscgc_reg_print_irqs_msgexynos_atomic_helper_wait_for_fencesplane: fb allocated by = %s mipi_syncNormalARGB88883%s: Failed to allocate IOVM (%lld) crc_cnthistogram_request_ioctl3%s: failed to get dqe resource hibernation_block_syncexynos_partial_restore[PARTIAL]: %s: scaling is detected. partial->full exynos-deconrd_hi_thres4%s[%u]: WARN: bus_width is not defined in DT. %s[%u]: WARN: afbc_yuv_rt_util_pct is not defined in DT. decon is not ready%s[%d]: buffer doesn't have compressed data rx_bufcmd=0x%02x length=%u rx=[%s] %s: %s[%d]: %s - 3%s: %s[%d]: packet format is invalid. te-gpio3%s: mode %s has wrong pmsk elements number %d cmd_underrun_cntdsim_of_get_pll_diags%s: %s[%d]: PL_FIFO_EMPTY irq occurs 3%s: %s[%d]: RX CRC error was detected! 4%s: %s[%d]: failed to get dsim extra phy _dsim_enablehs_clock_store3writeback(dpp%d) probe failedBT601_625_UNADJUSTEDFulldpu_bts_update_bwdpu_bts_update_disp[BTS] [ROT+] BEFORE latency check: %u KHz Pt4@XdLp(|<L(,d<<<<<(\\\\XX4\L  $).388hT T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T< < < < < T< < < \\\\\< X< < < < < < < < ((xx< (@@(#2P( P3p +   +   *   +   +   +   *  ~ *  t *  j *  ` )  V )  L )  B )  8 )  . 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'! ,E^w@e e<<e e@ 84 R pm R 55 R mp R dd M~{9y&qfXI6 "" 6IXfq&y9{~M @q?a;Q7B04(&&(40B7Q;a?qu j_UJ%@.77.@%JU_j u~%w)p/i5 b; [ATGNNGTA[ ;b 5i/p)w%~ 4vv4 0rz8 -n}< )j@&fD#bH^MYQUUQYM^Hb#Df&@j) <}n- 8zr0 -KnoDDonK-  7OkuW66WukO7==.Sjs dQ;#  #;Qd sjS.UUVGUi8P|+H =0   0= H+|P8iUGh0hY.xL*?%4*!  !*4%?*Lx.YvvgZ N  C90(!!(09C N ZgodXND;2$++$2;DNXdoToTTaTTTV)T1T7`T TwTTT;  T1T7`T TwTT|T(T1T7`T TwT1T7`T TwTfTT>T3T|T62kD-:S%b7U4rj$92kD-:S%]4&S8mg-72kD-:S%2kD-:S%p*\4[#B!g7A'N]: S4mn%6t*^1[C\=R3kq#5@ 0@P`p (08@HPX`hpx @ !6US>"Vs 2 3r0!#Y&7)K,/%3568 ;1=m????????? 08@HPTX\^`dfhlpx 0@` @`@   6DUi<R 05)4<>???????@`p 0@P`p 0@P`p 0@P`pV+~9 3y' \ ( D~ _!"#|%'(&*+m-/02d48689;=>^???A @P`p 0@P`p 0@P`p 0@P`p(TrY-@/i C   A|X^!"$8&')w+M-./135&7B9i;=>J? @` @` 0@P`p (08@HPX`hpx0UUUzl1 ~ g f {^{jej{? !i#$&(()+-/135R8:S=4] =F:'(l: Q9eNOBJF?0 F< >UDT.AEjdVHwG@  "$(,04683W=Zu%D`n{?c:  $(,048<Hj:Tl5Rn)Qv  @`  $(,08[w ?W{6IYhu @`  $(08<*9OlN} As\{ @`  $(08<*9OlN} As2Xx  @  "$(,0248<9LeBb~>[v%Ik @  $(,08<G]y&;`:Xt4Vv  !"#$%&'()*+,-.0@`@@@@  !#$%&()*+-./02345789<UCqN Z!(c/e7@@@  @  0  "#%&()+,05<Rq"]!}dpu@d@Ad@ C8 AR24 AB24 RA24 BA24 XR24XB24RX24BX24RG16 BG16AR30 AB30 RA30 BA30 NV12 NV21 P010 Y010 YU08 YU10  event_log_maxevent_print_maxdebug_dump_maskNONEDECON_ENABLEDDECON_DISABLEDDECON_FRAMEDONEDECON_FRAMESTARTDECON_RSC_OCCUPANCYDECON_TRIG_MASKDECON_UPDATE_CONFIGDSIM_ENABLEDDSIM_DISABLEDDSIM_COMMANDDSIM_ULPS_ENTERDSIM_ULPS_EXITDSIM_UNDERRUNDSIM_FRAMEDONEDSIM_PH_FIFO_TIMEOUTDSIM_PL_FIFO_TIMEOUTDPP_FRAMEDONEDPP_SET_PROTECTIONDMA_RECOVERYIDMA_AFBC_CONFLICTIDMA_FBC_ERRORIDMA_READ_SLAVE_ERRORIDMA_DEADLOCKIDMA_CFG_ERRORATOMIC_COMMITTE_INTERRUPTDECON_RUNTIME_SUSPENDDECON_RUNTIME_RESUMEDECON_SUSPENDDECON_RESUMEDSIM_RUNTIME_SUSPENDDSIM_RUNTIME_RESUMEDSIM_SUSPENDDSIM_RESUMEENTER_HIBERNATION_INENTER_HIBERNATION_OUTEXIT_HIBERNATION_INEXIT_HIBERNATION_OUTATOMIC_BEGINATOMIC_FLUSHWB_ENABLEWB_DISABLEWB_ATOMIC_COMMITWB_FRAMEDONEWB_ENTER_HIBERNATIONWB_EXIT_HIBERNATIONPREPARE_FBCLEANUP_FBPLANE_UPDATEPLANE_DISABLEREQ_CRTC_INFO_OLDREQ_CRTC_INFO_NEWFRAMESTART_TIMEOUTBTS_RELEASE_BWBTS_CALC_BWBTS_UPDATE_BWPARTIAL_INITPARTIAL_PREPAREPARTIAL_UPDATEPARTIAL_PESTOREDSIM_CRCDSIM_ECCVBLANK_ENABLEVBLANK_DISABLEDIMMING_STARTDIMMING_ENDCGC_FRAMEDONEITMON_ERRORSYSMMU_FAULTsamsung,exynos-deconsamsung,exynos-dppAR24AB24RA24BA24XR24XB24RX24BX24RG16BG16AR30AB30RA30BA30NV12NV21NV16NV61P010YU08YU10C8 AR24AB24RA24BA24XR24XB24RX24BX24RG16BG16AR30AB30RA30BA30  panelpanel_name@sec_panel_name@samsung,exynos-dsimsamsung,exynos-writebackRA24NV12`` 8DH` @2400x1080 pdqe__traceiter_tracing_mark_writeexynos_recovery_register__SCK__tp_func_tracing_mark_writeexynos_drm_connector_get_properties__tracepoint_tracing_mark_writeof_find_dpp_by_nodeexynos_drm_connector_init@1JM GxZ j p NQaf0 mNWkov|E-09IOU\n}z3:~ 'Cs6nn7R7l1T1 La}AlE]@CHV1ehRVZ^bfko9BZ)uJfvR+/sxP3[iXcwM d  <%G~^t[`d@DzNY^d` &F^admV'Y4 G   0ARewq]o"$?Ki 4DNPQkvtracing_mark_writedsi_txdsi_rxdsi_cmd_fifo_statusauthor=Inki Dae author=Joonyoung Shim author=Seung-Woo Kim description=Samsung SoC DRM Driverlicense=GPLparmtype=event_log_max:uintparmtype=event_print_max:uintparmtype=debug_dump_mask:uintparm=event_log_max:entry count of event log buffer arrayparm=event_print_max:print entry count of event log bufferparm=debug_dump_mask:mask for dump debug event logauthor=Hyung-jun Kim author=Seong-gyu Park description=Samsung SoC Display and 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/)8.note.gnu.property.note.Linux.text.comment.init.plt.rela.text.decon_regs_desc_init.rela__tracepoints.rela_ftrace_events.bss.rela__tracepoints_ptrs.rela.altinstructions__versions__tracepoints_strings__ksymtab_strings.rela__bpf_raw_tp_map.modinfo.rela__param.note.GNU-stack.llvm_addrsig.rela__dyndbg.rela___ksymtab+__tracepoint_tracing_mark_write.rela___kcrctab+__tracepoint_tracing_mark_write.rela.data.__SCK__tp_func_tracing_mark_write.text.ftrace_trampoline.rela.rodata..L__const.dqe_reg_print_dither.dither_name.rela.gnu.linkonce.this_module.rela__jump_table.rela__bug_table.note.gnu.build-id.shstrtab.strtab__ksymtab.symtab__kcrctab.rodata.rela.ref.dataexynos_drm_connector_set_propertyexynos_drm_writeback_set_propertyexynos_drm_plane_set_propertyexynos_drm_crtc_set_propertyexynos_drm_connector_get_propertyexynos_drm_writeback_get_propertyof_get_propertyexynos_drm_plane_get_propertyexynos_drm_crtc_get_propertydrm_plane_create_zpos_propertydrm_plane_create_rotation_propertyexynos_drm_crtc_create_partial_propertydrm_object_attach_propertydrm_plane_create_zpos_immutable_propertydrm_plane_create_blend_mode_propertyof_find_propertyexynos_drm_crtc_create_rcd_id_propertydrm_plane_create_alpha_propertydsim_reg_rx_fifo_is_emptydsim_reg_header_fifo_is_emptydsim_reg_payload_fifo_is_empty__dsim_wait_for_pl_fifo_empty__dsim_wait_for_ph_fifo_emptydsim_wait_for_cmd_fifo_emptyinit_wait_entrydecon_trigger_recoverystrcpymemcpystrlcpyexynos_hibernation_destroydrm_prime_gem_destroyexynos_drm_writeback_destroyexynos_drm_crtc_destroydrm_gem_fb_destroydsim_reg_enable_lane_physysfs_notifydrm_rotation_simplifyinit_timer_keyexynos_hibernation_register.__keyexynos_dqe_register.__key__init_completion.__keydecon_probe.__keydsim_probe.__keyexynos_drm_bind.__keyarm64_const_caps_readydsim_reg_wait_hs_clk_readyof_property_read_variable_u8_arrayof_property_read_variable_u16_arrayof_property_read_variable_u64_arrayof_property_read_variable_u32_array__const_udelaypm_runtime_set_autosuspend_delaydrm_modeset_lock_all_ctxtrace_raw_output_dsi_tx__tracepoint_dsi_txtrace_event_raw_event_dsi_tx__event_dsi_txprint_fmt_dsi_txevent_class_dsi_txtrace_event_fields_dsi_txtrace_event_type_funcs_dsi_tx__traceiter_dsi_tx__bpf_trace_tp_map_dsi_txperf_trace_dsi_tx__bpf_trace_dsi_tx__SCK__tp_func_dsi_tx__tpstrtab_dsi_txtrace_raw_output_dsi_rx__tracepoint_dsi_rxtrace_event_raw_event_dsi_rx__event_dsi_rxprint_fmt_dsi_rxevent_class_dsi_rxtrace_event_fields_dsi_rxtrace_event_type_funcs_dsi_rx__traceiter_dsi_rx__bpf_trace_tp_map_dsi_rxperf_trace_dsi_rx__bpf_trace_dsi_rx__SCK__tp_func_dsi_rx__tpstrtab_dsi_rxdqe_reg_print_linear_matrixdqe_reg_set_linear_matrixexynos_debugfs_add_matrixdqe_reg_print_gamma_matrixdqe_reg_set_gamma_matrixbts_get_bwindexexynos_get_idle_ip_indexof_reserved_mem_device_init_by_idxdpu_event_print_max__param_str_event_print_max__param_event_print_maxdev_attr_tdr_maxdpu_event_log_max__param_str_event_log_max__param_event_log_maxrecovery_showtdr_max_showdphy_diag_text_showlut_showst_showdpu_debug_event_showlt_showgain_limit_showambient_light_showback_light_showlt_calc_ab_shift_showtui_status_showcounters_showns_showdither_showearly_wakeup_showdump_showdstep_showhibernation_showupgrade_on_showtdr_min_showpp_en_showhs_clock_showdphy_diag_reg_showforce_te_showctmode_showbist_mode_showscale_mode_showthreshold_3_showpl_w2_showthreshold_2_showpl_w1_showthreshold_1_showdecon_reg_update_req_windowdpu_bts_calc_dpp_bwdpu_bts_update_overlap_bwdpu_bts_sum_all_decon_bwdpu_bts_update_disp_ch_bwdpu_bts_update_bwdpu_bts_calc_bwdrm_gem_prime_import_devcompare_devdpu_event_get_nextdrm_connector_list_iter_nextdrm_dev_putdrm_gem_object_putdrm_mode_object_putdma_heap_putdrm_crtc_vblank_putdma_buf_putdrm_property_blob_putdma_fence_wait_timeoutdsim_reg_set_timeoutdecon_reg_wait_run_status_timeoutdecon_reg_wait_idle_status_timeoutwait_for_completion_timeoutdecon_reg_wait_run_is_off_timeoutdecon_reg_wait_update_done_timeoutschedule_timeoutdqe_reg_print_lutodma_reg_set_in_qos_lutidma_reg_set_in_qos_lutexynos_debugfs_add_hdr_luthdr_reg_print_eotf_luthdr_reg_set_eotf_luthdr_reg_print_oetf_luthdr_reg_set_oetf_lutdqe_reg_print_cgc_lutdqe_reg_set_cgc_lutdqe_reg_print_regamma_lutdqe_reg_set_regamma_lutdqe_reg_print_degamma_lutdqe_reg_set_degamma_lutdpu_formats_listexynos_drm_crtc_histogram_pos_property.histogram_pos_listexynos_drm_plane_create_transfer_property.transfer_listexynos_drm_connector_create_orientation_property.drm_panel_orientation_enum_listexynos_drm_connector_create_brightness_properties.hbm_enum_listexynos_drm_wb_conn_create_range_property.range_listexynos_drm_plane_create_range_property.range_listexynos_drm_crtc_create_color_mode_property.color_mode_listexynos_drm_wb_conn_create_standard_property.standard_listexynos_drm_plane_create_standard_property.standard_listexynos_drm_crtc_create_force_bpc_property.bpc_listexynos_drm_connector_create_brightness_properties.mipi_sync_listdqe_reg_print_histdsim_reg_set_bistexynos_pm_qos_requestexynos_pm_qos_remove_requestexynos_pm_qos_update_requestdev_attr_stexynos_drm_gem_prime_importdsim_restart__cfi_jt_startdecon_reg_startdsim_reg_startdsim_reg_exit_ulps_and_startcgc_reg_set_cgc_startdbg_snapshot_emergency_rebootadjust_managed_page_countkstrtouintparam_ops_uintdpu_event_log_printhdr_reg_printdsim_reg_clear_intprepare_to_wait_eventhandle_histogram_eventdrm_crtc_arm_vblank_eventdecon_force_vblank_eventdrm_crtc_send_vblank_eventexynos_crtc_handle_eventdrm_send_eventdecon_reg_set_urgentdsim_reg_get_ph_cntdrm_crtc_enable_color_mgmtdev_attr_ltexynos_drm_connector_set_property.cfi_jtexynos_drm_writeback_set_property.cfi_jtexynos_drm_plane_set_property.cfi_jtexynos_drm_crtc_set_property.cfi_jtexynos_drm_connector_get_property.cfi_jtexynos_drm_writeback_get_property.cfi_jtexynos_drm_plane_get_property.cfi_jtexynos_drm_crtc_get_property.cfi_jtexynos_drm_writeback_destroy.cfi_jtexynos_drm_crtc_destroy.cfi_jtdrm_gem_fb_destroy.cfi_jttrace_raw_output_dsi_tx.cfi_jttrace_event_raw_event_dsi_tx.cfi_jt__traceiter_dsi_tx.cfi_jtperf_trace_dsi_tx.cfi_jt__bpf_trace_dsi_tx.cfi_jttrace_raw_output_dsi_rx.cfi_jttrace_event_raw_event_dsi_rx.cfi_jt__traceiter_dsi_rx.cfi_jtperf_trace_dsi_rx.cfi_jt__bpf_trace_dsi_rx.cfi_jtrecovery_show.cfi_jttdr_max_show.cfi_jtdphy_diag_text_show.cfi_jtlut_show.cfi_jtst_show.cfi_jtdpu_debug_event_show.cfi_jtlt_show.cfi_jtgain_limit_show.cfi_jtambient_light_show.cfi_jtback_light_show.cfi_jtlt_calc_ab_shift_show.cfi_jttui_status_show.cfi_jtcounters_show.cfi_jtns_show.cfi_jtdither_show.cfi_jtearly_wakeup_show.cfi_jtdump_show.cfi_jtdstep_show.cfi_jthibernation_show.cfi_jtupgrade_on_show.cfi_jttdr_min_show.cfi_jtpp_en_show.cfi_jths_clock_show.cfi_jtdphy_diag_reg_show.cfi_jtforce_te_show.cfi_jtctmode_show.cfi_jtbist_mode_show.cfi_jtscale_mode_show.cfi_jtthreshold_3_show.cfi_jtpl_w2_show.cfi_jtthreshold_2_show.cfi_jtpl_w1_show.cfi_jtthreshold_1_show.cfi_jtdpu_bts_calc_bw.cfi_jtcompare_dev.cfi_jtexynos_drm_gem_prime_import.cfi_jtexynos_hibernation_exit.cfi_jtdpu_bts_deinit.cfi_jttrace_event_raw_init.cfi_jtdpu_bts_init.cfi_jtexynos_drm_connector_init.cfi_jtexynos_partial_init.cfi_jtrmem_device_init.cfi_jtexynos_atomic_commit.cfi_jtwriteback_atomic_commit.cfi_jtexynos_drm_gem_dumb_map_offset.cfi_jtexynos_drm_connector_reset.cfi_jtexynos_drm_writeback_reset.cfi_jtexynos_drm_plane_reset.cfi_jtexynos_drm_crtc_reset.cfi_jtdsim_atomic_mode_set.cfi_jtexynos_drm_gem_free_object.cfi_jttrace_raw_output_dsi_cmd_fifo_status.cfi_jttrace_event_raw_event_dsi_cmd_fifo_status.cfi_jt__traceiter_dsi_cmd_fifo_status.cfi_jtperf_trace_dsi_cmd_fifo_status.cfi_jt__bpf_trace_dsi_cmd_fifo_status.cfi_jtexynos_drm_connector_get_properties.cfi_jtwriteback_get_modes.cfi_jtdrm_helper_probe_single_connector_modes.cfi_jtdpu_bts_update_resources.cfi_jtdpu_bts_release_resources.cfi_jtdsim_encoder_early_unregister.cfi_jtexynos_recovery_register.cfi_jtexynos_drm_connector_late_register.cfi_jtdsim_encoder_late_register.cfi_jtexynos_drm_plane_late_register.cfi_jtexynos_drm_crtc_late_register.cfi_jtexynos_drm_crtc_get_vblank_counter.cfi_jtexynos_hibernation_enter.cfi_jtexynos_recovery_handler.cfi_jtdpu_sysmmu_fault_handler.cfi_jtdecon_fs_irq_handler.cfi_jtdpp_irq_handler.cfi_jtdecon_irq_handler.cfi_jtdsim_irq_handler.cfi_jtdsim_err_fg_irq_handler.cfi_jtdecon_te_irq_handler.cfi_jtcgc_irq_handler.cfi_jtodma_irq_handler.cfi_jtbuf_dump_handler.cfi_jtexynos_hibernation_handler.cfi_jtdpu_itmon_notifier.cfi_jtdsim_host_transfer.cfi_jtexynos_crtc_mode_fixup.cfi_jtdrm_encoder_cleanup.cfi_jtdrm_plane_cleanup.cfi_jtdrm_atomic_helper_page_flip.cfi_jtexynos_drm_gem_mmap.cfi_jtexynos_get_format_info.cfi_jt__drm_printfn_info.cfi_jtexynos_drm_platform_shutdown.cfi_jtexynos_partial_adjust_region.cfi_jtdecon_atomic_begin.cfi_jtexynos_crtc_atomic_begin.cfi_jtkthread_delayed_work_timer_fn.cfi_jtkthread_worker_fn.cfi_jtrecovery_open.cfi_jtdphy_diag_text_open.cfi_jtlut_open.cfi_jtdpu_debug_event_open.cfi_jtdump_open.cfi_jthibernation_open.cfi_jtdrm_gem_vm_open.cfi_jtexynos_drm_open.cfi_jtexynos_tui_open.cfi_jtdphy_diag_reg_open.cfi_jtforce_te_open.cfi_jthistogram_request_ioctl.cfi_jtdrm_compat_ioctl.cfi_jtdrm_ioctl.cfi_jthistogram_cancel_ioctl.cfi_jtexynos_tui_ioctl.cfi_jtdrm_poll.cfi_jtexynos_atomic_commit_tail.cfi_jtexynos_hibernation_cancel.cfi_jtcommit_work.cfi_jtcommit_kthread_work.cfi_jtdecon_disable_vblank.cfi_jtexynos_drm_crtc_disable_vblank.cfi_jtdecon_enable_vblank.cfi_jtexynos_drm_crtc_enable_vblank.cfi_jtseq_lseek.cfi_jtdpp_check.cfi_jtexynos_hibernation_check.cfi_jtexynos_partial_check.cfi_jtexynos_atomic_check.cfi_jtdecon_atomic_check.cfi_jtdsim_atomic_check.cfi_jtwriteback_atomic_check.cfi_jtexynos_plane_atomic_check.cfi_jtexynos_crtc_atomic_check.cfi_jtdecon_atomic_flush.cfi_jtexynos_crtc_atomic_flush.cfi_jtof_device_match.cfi_jtdsim_host_attach.cfi_jtdsim_host_detach.cfi_jt__drm_printfn_debug.cfi_jtdrm_atomic_helper_set_config.cfi_jttrace_event_reg.cfi_jtexynos_partial_set_size.cfi_jtdpp_remove.cfi_jtdecon_remove.cfi_jtexynos_drm_platform_remove.cfi_jtdsim_remove.cfi_jtwriteback_remove.cfi_jtexynos_tui_remove.cfi_jtrecovery_write.cfi_jtlut_write.cfi_jthibernation_write.cfi_jttrace_raw_output_tracing_mark_write.cfi_jttrace_event_raw_event_tracing_mark_write.cfi_jt__traceiter_tracing_mark_write.cfi_jtperf_trace_tracing_mark_write.cfi_jt__bpf_trace_tracing_mark_write.cfi_jtdphy_diag_reg_write.cfi_jtforce_te_write.cfi_jtexynos_drm_connector_destroy_state.cfi_jtexynos_drm_writeback_destroy_state.cfi_jtexynos_drm_plane_destroy_state.cfi_jtexynos_drm_crtc_destroy_state.cfi_jtexynos_atomic_destroy_priv_state.cfi_jtexynos_atomic_duplicate_priv_state.cfi_jtexynos_drm_connector_print_state.cfi_jtexynos_drm_plane_print_state.cfi_jtexynos_drm_crtc_print_state.cfi_jtexynos_drm_connector_duplicate_state.cfi_jtexynos_drm_writeback_duplicate_state.cfi_jtexynos_drm_plane_duplicate_state.cfi_jtexynos_drm_crtc_duplicate_state.cfi_jtexynos_drm_gem_dumb_create.cfi_jtexynos_user_fb_create.cfi_jtdpp_update.cfi_jt__exynos_dqe_update.cfi_jtexynos_plane_atomic_update.cfi_jtexynos_drm_postclose.cfi_jtdrm_gem_vm_close.cfi_jtseq_release.cfi_jtdrm_release.cfi_jtexynos_tui_release.cfi_jtsingle_release.cfi_jtdma_fence_release.cfi_jtrmem_device_release.cfi_jttdr_max_store.cfi_jtst_store.cfi_jtlt_store.cfi_jtgain_limit_store.cfi_jtambient_light_store.cfi_jtback_light_store.cfi_jtlt_calc_ab_shift_store.cfi_jtns_store.cfi_jtdither_store.cfi_jtearly_wakeup_store.cfi_jtdstep_store.cfi_jtupgrade_on_store.cfi_jttdr_min_store.cfi_jtpp_en_store.cfi_jths_clock_store.cfi_jtforce_update_store.cfi_jtctmode_store.cfi_jtbist_mode_store.cfi_jtscale_mode_store.cfi_jtthreshold_3_store.cfi_jtpl_w2_store.cfi_jtthreshold_2_store.cfi_jtpl_w1_store.cfi_jtthreshold_1_store.cfi_jtdecon_wait_for_flip_done.cfi_jtdrm_atomic_helper_update_plane.cfi_jtdecon_update_plane.cfi_jtdrm_atomic_helper_disable_plane.cfi_jtdecon_disable_plane.cfi_jtdecon_resume.cfi_jtdsim_resume.cfi_jtdecon_runtime_resume.cfi_jtdsim_runtime_resume.cfi_jtinit_module.cfi_jtcleanup_module.cfi_jt__drm_puts_seq_file.cfi_jt__drm_printfn_seq_file.cfi_jtdrm_gem_prime_fd_to_handle.cfi_jtdrm_gem_fb_create_handle.cfi_jtexynos_drm_gem_prime_import_sg_table.cfi_jtdsim_encoder_disable.cfi_jtdpp_disable.cfi_jtdecon_disable.cfi_jtwriteback_disable.cfi_jtexynos_plane_atomic_disable.cfi_jtexynos_drm_crtc_atomic_disable.cfi_jtdsim_encoder_enable.cfi_jtdecon_enable.cfi_jtwriteback_enable.cfi_jtexynos_drm_crtc_atomic_enable.cfi_jtdrm_gem_object_free.cfi_jt__drm_atomic_state_free.cfi_jtof_find_dpp_by_node.cfi_jtdpp_probe.cfi_jtdecon_probe.cfi_jtexynos_drm_platform_probe.cfi_jtdsim_probe.cfi_jtwriteback_probe.cfi_jtexynos_tui_probe.cfi_jtdpp_unbind.cfi_jtdecon_unbind.cfi_jtexynos_drm_unbind.cfi_jtdsim_unbind.cfi_jtwriteback_unbind.cfi_jtdpp_bind.cfi_jtdecon_bind.cfi_jtexynos_drm_bind.cfi_jtdsim_bind.cfi_jtwriteback_bind.cfi_jtdecon_suspend.cfi_jtdsim_suspend.cfi_jtdecon_runtime_suspend.cfi_jtdsim_runtime_suspend.cfi_jtexynos_partial_send_command.cfi_jtdsim_mode_valid.cfi_jtexynos_crtc_mode_valid.cfi_jtdrm_gem_prime_handle_to_fd.cfi_jtseq_read.cfi_jtdrm_read.cfi_jtexynos_crtc_mode_set_nofb.cfi_jtexynos_plane_cleanup_fb.cfi_jtexynos_plane_prepare_fb.cfi_jtexynos_hibernation_exithibernation_block_exitexynos_hibernation_async_exitdpu_bts_deinitdpp_reg_deinitrcd_reg_deinitphy_init__mutex_inittrace_event_raw_initdrm_gem_private_object_initdpu_bts_init__kstrtabns_exynos_drm_connector_init__crc_exynos_drm_connector_init__kstrtab_exynos_drm_connector_init__ksymtab_exynos_drm_connector_initdrm_writeback_connector_initdrm_framebuffer_initdrm_encoder_initdrm_kms_helper_poll_initexynos_partial_initdrm_vblank_initdrm_atomic_private_obj_initexynos_drm_mode_config_initdrmm_mode_config_initdpp_reg_initdecon_reg_initdsim_reg_initdqe_reg_initrcd_reg_initdecon_dsc_reg_initdrm_event_reserve_initdrm_modeset_acquire_initexynos_plane_initdrm_universal_plane_initrmem_device_inithdr_regs_desc_initdpp_regs_desc_initdecon_regs_desc_initdsim_regs_desc_initdqe_regs_desc_inittm_y_axis_2084_1000nittm_x_axis_2084_1000nittrace_event_buffer_commitdrm_atomic_helper_setup_commitdrm_atomic_nonblocking_commitexynos_atomic_commitdrm_atomic_commitwriteback_atomic_commit___ratelimitdev_attr_gain_limitperf_trace_run_bpf_submitfind_next_bitfinish_waitdev_attr_ambient_lightdev_attr_back_lightdev_attr_lt_calc_ab_shifttm_y_axis_dfteotf_y_axis_dfttm_x_axis_dfteotf_x_axis_dftmemsetdpp_reg_set_uv_offsetdrm_gem_create_mmap_offsetexynos_drm_gem_dumb_map_offsetexynos_drm_gem_offsetdsc_reg_swresetrcd_reg_set_sw_resetodma_reg_set_sw_resetidma_reg_set_sw_resetdsim_reg_sw_resetexynos_drm_connector_resetdsim_reg_function_resetexynos_drm_writeback_resetdrm_mode_config_resetdecon_reg_resetexynos_dqe_resetexynos_drm_plane_reset__drm_atomic_helper_crtc_resetexynos_drm_crtc_resetdrm_atomic_helper_check_modesetdecon_check_modesetdecon_seamless_mode_setdrm_bridge_chain_mode_setdsim_atomic_mode_setmipi_dsi_create_packetdsim_reg_enable_multi_cmd_packetdevm_phy_getdrm_mode_object_getdevm_pinctrl_getdrm_crtc_vblank_getdevm_clk_getdma_buf_getktime_getdrm_pro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