ELF- @@42  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;;;  ;;;;;  ;;;;;  ;;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;;  ;;;;;  ;;;;;;  ;;;;;  ;;;;;;;;;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;  ;;;;;;  ;;;;;;;;;;;***;*****  ***;*****  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  ;;;;;U B P _ d | i Z w B        B  4   0  p   q     + l P ^ A 2 "    x       g ;  $            5 a      Y x G  h w   E  @       j        S $ ($$,((\XX`\\d``hddlhhplltppxttxx||   $(  ,$$p 00   @  @@  "$$ $$$((<@@@DDDHHHLL  00 088,<<0@@4DD8HH<LL@PPD``T xxxx "%s", REC->dw_name "%s, return: %d", REC->dw_name, REC->ret "%s, return: %d, value: 0x%x", REC->dw_name, REC->ret, REC->val "%s, return: %d, value: 0x%llx", REC->dw_name, REC->ret, REC->val "%s, flags: %s, skb->len: %d", REC->dw_name, __print_flags(REC->flags, "|", { MCPS802154_TX_FRAME_CONFIG_TIMESTAMP_DTU, "TIMESTAMP_DTU" }, { MCPS802154_TX_FRAME_CONFIG_CCA, "CCA" }, { MCPS802154_TX_FRAME_CONFIG_RANGING, "RANGING" }, { MCPS802154_TX_FRAME_CONFIG_KEEP_RANGING_CLOCK, "KEEP_RANGING_CLOCK" }, { MCPS802154_TX_FRAME_CONFIG_SP3, "SP3" }, { MCPS802154_TX_FRAME_CONFIG_SP2, "SP2" }, { MCPS802154_TX_FRAME_CONFIG_SP1, "SP1" }, { MCPS802154_TX_FRAME_CONFIG_STS_MODE_MASK, "STS_MODE_MASK" }),REC->len "%s, cannot program delayed, tx_date_dtu: 0x%x, cur_time_dtu: 0x%x", REC->dw_name, REC->tx_date_dtu, REC->cur_time_dtu "%s, flags: %s, timeout: %d", REC->dw_name, __print_flags(REC->flags, "|", { MCPS802154_RX_FRAME_CONFIG_TIMESTAMP_DTU, "TIMESTAMP_DTU" }, { MCPS802154_RX_FRAME_CONFIG_AACK, "AACK" }, { MCPS802154_RX_FRAME_CONFIG_RANGING, "RANGING" }, { MCPS802154_RX_FRAME_CONFIG_KEEP_RANGING_CLOCK, "KEEP_RANGING_CLOCK" }, { MCPS802154_RX_FRAME_CONFIG_RANGING_PDOA, "RANGING_PDOA" }, { MCPS802154_RX_FRAME_CONFIG_SP3, "SP3" }, { MCPS802154_RX_FRAME_CONFIG_SP2, "SP2" }, { MCPS802154_RX_FRAME_CONFIG_SP1, "SP1" }, { MCPS802154_RX_FRAME_CONFIG_STS_MODE_MASK, "STS_MODE_MASK" }), REC->timeout "%s, too late to program delayed, rx_date_dtu: 0x%x, current_dtu: 0x%x", REC->dw_name, REC->rx_date_dtu, REC->cur_time_dtu "%s, flags: %s", REC->dw_name, __print_flags(REC->flags, "|", { MCPS802154_RX_FRAME_INFO_TIMESTAMP_DTU, "TIMESTAMP_DTU" }, { MCPS802154_RX_FRAME_INFO_TIMESTAMP_RCTU, "TIMESTAMP_RCTU" }, { MCPS802154_RX_FRAME_INFO_LQI, "LQI" }, { MCPS802154_RX_FRAME_INFO_RSSI, "RSSI" }, { MCPS802154_RX_FRAME_INFO_RANGING_FOM, "RANGING_FOM" }, { MCPS802154_RX_FRAME_INFO_RANGING_OFFSET, "RANGING_OFFSET" }, { MCPS802154_RX_FRAME_INFO_RANGING_PDOA, "RANGING_PDOA" }, { MCPS802154_RX_FRAME_INFO_RANGING_PDOA_FOM, "RANGING_PDOA_FOM" }, { MCPS802154_RX_FRAME_INFO_RANGING_STS_TIMESTAMP_RCTU, "RANGING_STS_TIMESTAMP_RCTU" }, { MCPS802154_RX_FRAME_INFO_RANGING_STS_FOM, "RANGING_STS_FOM" }, { MCPS802154_RX_FRAME_INFO_AACK, "AACK" }) "%s, flags: %s", REC->dw_name, __print_flags(REC->flags, "|", { MCPS802154_RX_FRAME_INFO_TIMESTAMP_DTU, "TIMESTAMP_DTU" }, { MCPS802154_RX_FRAME_INFO_TIMESTAMP_RCTU, "TIMESTAMP_RCTU" }, { MCPS802154_RX_FRAME_INFO_LQI, "LQI" }, { MCPS802154_RX_FRAME_INFO_RSSI, "RSSI" }, { MCPS802154_RX_FRAME_INFO_RANGING_FOM, "RANGING_FOM" }, { MCPS802154_RX_FRAME_INFO_RANGING_OFFSET, "RANGING_OFFSET" }, { MCPS802154_RX_FRAME_INFO_RANGING_PDOA, "RANGING_PDOA" }, { MCPS802154_RX_FRAME_INFO_RANGING_PDOA_FOM, "RANGING_PDOA_FOM" }, { MCPS802154_RX_FRAME_INFO_RANGING_STS_TIMESTAMP_RCTU, "RANGING_STS_TIMESTAMP_RCTU" }, { MCPS802154_RX_FRAME_INFO_RANGING_STS_FOM, "RANGING_STS_FOM" }, { MCPS802154_RX_FRAME_INFO_AACK, "AACK" }) "%s, timeout: %s, timeout_dtu: 0x%0x, next_operational_state: %s", REC->dw_name, REC->timeout ? "true" : "false", REC->timeout_dtu, __print_symbolic(REC->next_operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, page: %u, channel: %u, preamble_code: %u", REC->dw_name, REC->page, REC->channel, REC->pcode "%s, changed: 0x%x", REC->dw_name, REC->changed "%s, n_segs: %u", REC->dw_name, REC->n_segs "%s, rmarker_dtu: 0x%x", REC->dw_name, REC->rmarker_dtu "%s, rmarker_rctu: 0x%llx", REC->dw_name, REC->rmarker_rctu "%s, rmarker_dtu: 0x%x, ts_rctu: 0x%llx, rmarker_rctu: 0x%llx", REC->dw_name, REC->rmarker_dtu, REC->ts_rctu, REC->rmarker_rctu "%s, ts_dtu: 0x%x, ant_offset: 0x%x, rmarker_rctu: 0x%llx", REC->dw_name, REC->ts_dtu, REC->ant_offset, REC->rmarker_rctu "%s, status: %s", REC->dw_name, __print_flags(REC->status, "|", { (u64)(0x20000UL) << 32, "RXSTS" }, { (u64)(0x10000UL) << 32, "TXSTS" }, { (u64)(0x8000U) << 32, "SEMA_ERR" }, { (u64)(0x4000U) << 32, "COEX_CLR" }, { (u64)(0x2000U) << 32, "COEX_ERR" }, { (u64)(0x1000U) << 32, "CCA_FAIL" }, { (u64)(0x800U) << 32, "SPIERR" }, { (u64)(0x400U) << 32, "SPI_UNF" }, { (u64)(0x200U) << 32, "SPI_OVF" }, { (u64)(0x100U) << 32, "CMD_ERR" }, { (u64)(0x80U) << 32, "AES_ERR" }, { (u64)(0x40U) << 32, "AES_DONE" }, { (u64)(0x20U) << 32, "GPIO_IRQ" }, { (u64)(0x10U) << 32, "VT_DET" }, { (u64)(0x4U) << 32, "PGFCAL_ERR" }, { (u64)(0x2U) << 32, "RXPREJ" }, { 0x80000000UL, "TIMER1" }, { 0x40000000UL, "TIMER0" }, { 0x20000000UL, "ARFE" }, { 0x10000000UL, "CPERR" }, { 0x8000000UL, "HPDWARN" }, { 0x4000000UL, "RXSTO" }, { 0x2000000UL, "PLL_HILO" }, { 0x1000000UL, "RCINIT" }, { 0x800000UL, "SPIRDY" }, { 0x400000UL, "LCSSERR" }, { 0x200000UL, "RXPTO" }, { 0x100000UL, "RXOVRR" }, { 0x80000UL, "VWARN" }, { 0x40000UL, "CIAERR" }, { 0x20000UL, "RXFTO" }, { 0x10000UL, "RXFSL" }, { 0x8000U, "RXFCE" }, { 0x4000U, "RXFCG" }, { 0x2000U, "RXFR" }, { 0x1000U, "RXPHE" }, { 0x800U, "RXPHD" }, { 0x400U, "CIA_DONE" }, { 0x200U, "RXSFDD" }, { 0x100U, "RXPRD" }, { 0x80U, "TXFRS" }, { 0x40U, "TXPHS" }, { 0x20U, "TXPRS" }, { 0x10U, "TXFRB" }, { 0x8U, "AAT" }, { 0x4U, "SPICRCERR" }, { 0x2U, "CLK_PLL_LOCK" }, { 0x1U, "IRQS" }) "%s, low_sys_status: 0x%08x", REC->dw_name, REC->low_sys_status "%s, operational_state: %s", REC->dw_name, __print_symbolic(REC->operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, operational_state: %s", REC->dw_name, __print_symbolic(REC->operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, delay_dtu: %d, current_operational_state: %s, next_operational_state: %s", REC->dw_name, REC->delay_dtu, __print_symbolic(REC->current_operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }), __print_symbolic(REC->next_operational_state, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, sys_time_sync: 0x%08x, dtu_sync: 0x%08x", REC->dw_name, REC->sys_time_sync, REC->dtu_sync "%s, result: %d", REC->dw_name, REC->result "%s, time_ns: %lld", REC->dw_name, REC->time_before "%s, delay: %dus", REC->dw_name, REC->delay_us "%s, sleep_us: %lld, sleep_enter_dtu: 0x%x, next_op_date: 0x%x, next_op: %s", REC->dw_name, REC->sleep_time_us, REC->sleep_enter_dtu, REC->dtu_next_op, __print_symbolic(REC->next_op, { DW3000_OP_STATE_OFF, "OFF" }, { DW3000_OP_STATE_DEEP_SLEEP, "DEEP_SLEEP" }, { DW3000_OP_STATE_SLEEP, "SLEEP" }, { DW3000_OP_STATE_WAKE_UP, "WAKE_UP" }, { DW3000_OP_STATE_INIT_RC, "INIT_RC" }, { DW3000_OP_STATE_IDLE_RC, "IDLE_RC" }, { DW3000_OP_STATE_IDLE_PLL, "IDLE_PLL" }, { DW3000_OP_STATE_TX_WAIT, "TX_WAIT" }, { DW3000_OP_STATE_TX, "TX" }, { DW3000_OP_STATE_RX_WAIT, "RX_WAIT" }, { DW3000_OP_STATE_RX, "RX" }) "%s, state: %s, boot_time_ns: %llu, len_or_date: %u", REC->dw_name, __print_symbolic(REC->state, { DW3000_PWR_OFF, "OFF" }, { DW3000_PWR_DEEPSLEEP, "DEEPSLEEP" }, { DW3000_PWR_RUN, "RUN" }, { DW3000_PWR_IDLE, "IDLE" }, { DW3000_PWR_RX, "RX" }, { DW3000_PWR_TX, "TX" }), REC->boot_time_ns, (unsigned)REC->len_or_date "%s, res: %d, xtrim: %d, bias: %d", REC->dw_name, REC->res, REC->value, REC->bias "%s, res: %d, gpio: %u, value: %u", REC->dw_name, REC->res, REC->gpio, REC->value "%s, utime: %llu, prf: %u, sts: %u", REC->dw_name, REC->utime, REC->prf, REC->stsMode "%s, ts: %llu, f1: %u, f2: %u, f3: %u, acc: %hu, fpidx: %hu, offset: %d, filter: 0x%x", REC->dw_name, REC->ts, REC->f1, REC->f2, REC->f3, REC->acc, REC->fpidx, REC->off, REC->filter "%s, current state: %s, new state: %s, delay_us: %d, expire: %u", REC->dw_name, REC->status ? "ON" : "OFF", REC->state ? "ON" : "OFF", REC->delay_us, (unsigned)REC->expire "%s, delay_us: %d, status: %s, coex_interval_us: %d", REC->dw_name, REC->delay_us, REC->status ? "ON" : "OFF", REC->coex_interval_us "%s, status: %s", REC->dw_name, REC->status ? "ON" : "OFF" "%s base pwr: 0x%08x, adjusted: 0x%08x (chan: %u,frm_dur: %u, PL_len: %u, th. boost: %u, applied boost: %u)", REC->dw_name, REC->base_power, REC->adjusted_power, REC->chan, REC->frm_dur, REC->pl_len, REC->th_boost, REC->app_boost "%s, chip: %s, sts: %u, cir_pwr: %u, pacc_cnt: %u, prf_64mhz: %u, dgc_dec: %u", REC->dw_name, REC->chip_name, REC->sts, REC->cir_pwr, REC->pacc_cnt, REC->prf_64mhz, REC->dgc_dec "%s, dss_stat: %s", REC->dw_name, __print_flags(REC->dss_stat, "|", { 0x1U, "SPI1_AVAIL" }, { 0x2U, "SPI2_AVAIL" }) "%s, ver_id: %u, seq_num: %u", REC->dw_name, REC->ver_id, REC->seq_num "%s, session_time0_sys_time: 0x%08x", REC->dw_name, REC->session_time0_sys_time "%s, clock_offset_sys_time: 0x%08x", REC->dw_name, REC->clock_offset_sys_time "%s, session_id %d", REC->dw_name, REC->session_id "%s, next_timestamp_dtu: 0x%08x, next_duration_dtu: 0x%08x", REC->dw_name, REC->next_timestamp_dtu, REC->next_duration_dtu "%s, signature: %s, ver_id: %u, seq_num: %u, nb_tlv: %u", REC->dw_name, __print_hex(REC->signature, 5), REC->ver_id, REC->seq_num, REC->nb_tlv "%s, type: %s, data: %s", REC->dw_name, __print_symbolic(REC->type, { DW3000_NFCC_COEX_TLV_TYPE_UNSPEC, "UNSPEC" }, { DW3000_NFCC_COEX_TLV_TYPE_SESSION_TIME0, "SESSION_TIME0" }, { DW3000_NFCC_COEX_TLV_TYPE_SLOT_LIST, "SLOT_LIST" }, { DW3000_NFCC_COEX_TLV_TYPE_TLV_UWBCNT_OFFS, "TLV_UWBCNT_OFFS" }, { DW3000_NFCC_COEX_TLV_TYPE_ERROR, "ERROR" }, { DW3000_NFCC_COEX_TLV_TYPE_SLOT_LIST_UUS, "SLOT_LIST_UUS" }), __print_hex(__get_dynamic_array(data), __get_dynamic_array_len(data)) "%s, start: %s, idle_duration_dtu: 0x%08x, timestamp_dtu: 0x%08x, duration_dtu: 0x%08x, chan: %d", REC->dw_name, REC->start ? "true" : "false", REC->idle_duration_dtu, REC->timestamp_dtu, REC->duration_dtu, REC->chan "%s, send: %s, idle_duration_dtu: %d, send_timestamp_dtu: 0x%08x", REC->dw_name, __print_symbolic(REC->send, { DW3000_NFCC_COEX_SEND_CLK_SYNC, "CLK_SYNC" }, { DW3000_NFCC_COEX_SEND_CLK_OFFSET, "CLK_OFFSET" }, { DW3000_NFCC_COEX_SEND_STOP, "STOP" }), REC->idle_duration_dtu, REC->send_timestamp_dtu "%s, err: "%s"", REC->dw_name, __get_str(err) "%s, warn: "%s"", REC->dw_name, __get_str(warn) "%s, channel: %d", REC->dw_name, REC->channel "%s, mode: %d", REC->dw_name, REC->mode "%s, pdoa: 0x%08x", REC->dw_name, REC->pdoa "%s, chan: %d, len: %d, rate: %d", REC->dw_name, REC->chan, REC->len, REC->rate "%s", REC->dw_name "%s, clockoffset: %d", REC->dw_name, REC->cfo "%s", REC->dw_name "%s", REC->dw_name ant0.ch9.prf16.pg_delayant0.ant1.ch5.pdoa_lutch9.wifi_coex-enabledAES RAMrx_sfdtypecould not request the IRQ %d: %d wificoex_gpiodevice configuration has failed (%d) regulator failed to set voltage :%d Allocation failed. Cannot open file. u32SP3%s, page: %u, channel: %u, preamble_code: %u statusTXFRSfpidx%s, session_id %d ant0.ant1.ch9.pdoa_lutsmart_tx_powerdigi_diag_clrdisableDW3000_NFCC_COEX_TLV_TYPE_TLV_UWBCNT_OFFSDW3000_DSS_STAT_SPI2_AVAIL_BIT_MASK%s, return: %d, value: 0x%llx SPI_OVFCMD_ERRvalueerrant3.ch9.prf16.pg_delayant1.ant3.ch9.pdoa_lutdw3000_pidTX_CALtx_pream_lendevice not in IDLE_RC state &stm->work_wqdbgfs: impossible to alloc buffers mem include/linux/uaccess.hmask defined but modify not supported for this size DW3000_OP_STATE_IDLE_PLLTXsleep_enter_dtugpioprff2pl_lenstsu8[5]__data_loc u8[]ant2.ch5.prf64.ant_delaydevice LDO & bias tune setup has failed (%d) dw3000_isr_handle_spi_errorCOEX_CLRTIMER1CIAERRcoex_interval_us%s, delay_us: %d, status: %s, coex_interval_us: %d %s base pwr: 0x%08x, adjusted: 0x%08x (chan: %u,frm_dur: %u, PL_len: %u, th. boost: %u, applied boost: %u) cir_pwrant0.ch5.prf16.pg_countant1.selector_gpioant2.selector_gpioGEN_CFG1AONdevice XTRIM setup has failed (%d) cache missesantennas set id %d is out of range, max is %d A timer cmd is already queued, this cmd will be ignored unable to dump registers: device not ready buffer too smallinput format error (%d) DW3000_OP_STATE_INIT_RCDW3000_NFCC_COEX_TLV_TYPE_UNSPECflagsCCA%s, sys_time_sync: 0x%08x, dtu_sync: 0x%08x mode(&nfcc_coex->watchdog_timer)ant0.ch5.prf64.ant_delayant0.ch5.prf64.pg_delayant0.selector_gpio_valueant1.ch5.prf64.pg_countant1.ch5.prf64.pg_delayant1.portant0.ant3.ch9.pdoa_lutGEN_CFG0frame_filter_cfgtx_pream_chuwbhal,reset-gpioLoading driver uwbm-4.5.0...wait device power on failed: %d device present using debug min clamp=%d valSP1%s, rmarker_dtu: 0x%x, ts_rctu: 0x%llx, rmarker_rctu: 0x%llx len_or_datestsModeidle_duration_dtuant0.ant2.ch5.pdoa_lutchan_pll_cfgCould not enable regulator device CIA DIAG setup has failed (%d) instructions&dw->operational_state_wqDW3000_PWR_TX%s, return: %d AACKRANGING_PDOA_FOMTX_WAIT%s, rmarker_rctu: 0x%llx ts_rctuSPICRCERRconst char *CLK_OFFSETant1.ch9.prf16.tx_powerant0.ant3.ch5.pdoa_offsettemperature_referenceOTP_IF %s: %llu test mode: counter overflow for event %x:%llx false%s, n_segs: %u %s, rmarker_dtu: 0x%x %s, pdoa: 0x%08x Error while reading NFCC scratch RAMant0.ch9.prf16.ant_delayant2.ch9.prf64.pg_delayant1.ant2.ch5.pdoa_lutch9.pll_locking_codeCIA_2fail to get 'regulator_delay_us' %s test mode: start test %d registers%u intRANGINGLQInext_operational_stateSPI_UNFnext_optimestamp_dtu%s, err: "%s" cfoant3.ch5.prf64.ant_delayant3.ch9.prf64.pg_delayant3.portant1.ant2.ch9.pdoa_offsetNo regulators, assuming always on invalid reset gpio Failure to allocate message for reg 0x%x (index %u, len %d, mode %d) &stm->mtxunable to reach registers: device not ready DW3000_OP_STATE_DEEP_SLEEPDW3000_NFCC_COEX_TLV_TYPE_SLOT_LIST_UUSDW3000_DSS_STAT_SPI1_AVAIL_BIT_MASKu16%s, flags: %s, skb->len: %d timeout%s, flags: %s, timeout: %d %s, changed: 0x%x CPERRRXPRDfilter%s, current state: %s, new state: %s, delay_us: %d, expire: %u frm_durdss_stat%s, start: %s, idle_duration_dtu: 0x%08x, timestamp_dtu: 0x%08x, duration_dtu: 0x%08x, chan: %d warn%s, channel: %d s16include/linux/thread_info.hwatchdog timer is pendingant2.ch5.prf16.pg_countant3.ch9.prf16.pg_countant3.ch9.prf64.tx_powerSTS_CFGFS_CTRLrx_phrmoderolethread cpu %d cannot set CIA diagnostic option while the double buffering is disabled Failed to power device: %d state machine initialisation failed: %d DW3000_OP_STATE_SLEEPchannelTXPHSlow_sys_statusdelay_usstatepdoa%s, clockoffset: %d ../google-modules/uwb/qorvo/dw3000/kernel/drivers/net/ieee802154/dw3000_core.cant2.ch9.prf16.pg_delayant2.capsant3.ch5.prf16.ant_delayant3.ch5.prf64.pg_delaydataratetx_pwrdw3000-resetdevice coarse code setup has failed (%d) Could not set reset gpio as input RX buffer allocation failed device checking failed: %d poweron returns %d RANGING_PDOARX_WAITTIMER0%s, delay_dtu: %d, current_operational_state: %s, next_operational_state: %s time_beforeant1.ant2.ch5.pdoa_offsetDIG_DIAGchan_pg_delaytoo late to program delayed tx date_dtu=%x current_dtu=%x n_segsHPDWARNRXPHE%s, result: %d sleep_time_usboot_time_nsexpireSLOT_LISTsendant1.ch9.prf16.pg_countant1.ant2.ch9.pdoa_luttxrf_pwrfinC0Timeout waiting poweron event. regulator %s failed for 2p5 (%d) restricted_channels.pdoa_lutSPI pid: %u, dw3000 pid: %u checking device presence min_clamppoweroff returns %d DW3000_OP_STATE_TX_WAITDEEP_SLEEPpcode%s, ts_dtu: 0x%x, ant_offset: 0x%x, rmarker_rctu: 0x%llx ARFEVWARNAATCLK_PLL_LOCKresUNSPECenum dw3000_nfcc_coex_sendCLK_SYNCant0.ch9.prf16.tx_powerant1.ch5.prf16.tx_powercoex_margin_usgpiodirxtal_trimfail to get 'qos_latency' %s char[32]OFFINIT_RCrmarker_rctuSPIERRRXFR%s, sleep_us: %lld, sleep_enter_dtu: 0x%x, next_op_date: 0x%x, next_op: %s tschip_nameenum dw3000_nfcc_coex_tlv_typeduration_dtuSPIxMAVAIL interrupts enable failedspi available without timer pendingant0.ch9.prf16.pg_countant3.ch9.prf64.ant_delayant3.capsant0.ant3.ch5.pdoa_lutauto_sleep_marginspi_pidRX_TUNEPMSCeuidregulator_delay_us(work_completion)(&dw->timer_expired_work)branch instssetup mode: %d, %u bits/w, %u Hz max work enqueuing interrupted by signalimpossible to copy data to userlandDW3000_OP_STATE_RX_WAITtrueVT_DETPLL_HILORXFSLdelay_dtu%s, delay: %dus pacc_cntdgc_decant0.ch9.prf64.pg_countant0.selector_gpioant1.ch9.prf64.ant_delayant1.ch9.prf64.tx_powerant3.selector_gpio_valueant0.ant2.ch9.pdoa_offsetRF_CONFrx_antdlywificoex_delay_usqos latency %d uwberror when init of virtual registers DW3000_NFCC_COEX_TLV_TYPE_SLOT_LISTDW3000_NFCC_COEX_TLV_TYPE_ERRORCCA_FAILsignaturesend_timestamp_dtu../google-modules/uwb/qorvo/dw3000/kernel/drivers/net/ieee802154/dw3000_mcps.cwriting to nfcc exceed SCRATCH_AP_SIZEant0.ch5.prf16.tx_powerant0.ch5.prf16.pg_delayant2.ch5.prf64.tx_powerant1.ant3.ch9.pdoa_offsetalternate_pulse_shapegpiooutwificoex_margin_usFail to get %s regulator (%d) error when init of chip's registers no valid value provided DW3000_PWR_RUNDW3000_NFCC_COEX_SEND_CLK_OFFSETretu64u8TIMESTAMP_RCTUenum operational_stateAES_DONEGPIO_IRQRXOVRRDEEPSLEEPacc%s, session_time0_sys_time: 0x%08x %s, signature: %s, ver_id: %u, seq_num: %u, nb_tlv: %u %s, chan: %d, len: %d, rate: %d bad rssi value. Forced to 0 CIA_3RX_BUFFER1ext_clkdly_enpower_reg_1p8wificoex_interval_us&dw->cir_data->mutexregulator %s failed for 1p8 (%d) Bad antenna number (%d) can_dma: %d DW3000_PWR_OFFDW3000_NFCC_COEX_TLV_TYPE_SESSION_TIME0boolTXPRS%s, dss_stat: %s session_time0_sys_timeERRORQORVOant0.capsant1.ch9.prf64.pg_delayant2.ch9.prf64.ant_delayant3.ch5.prf64.tx_powercoex_gpioDRX_CONFRX_BUFFERext_clkdlydigi_diag_enD0Device already powered on fail to get 'wificoex_interval_us' %s regulator delay %d us Fail to read registers in fileId %d (%d) changedrmarker_dtu%s, utime: %llu, prf: %u, sts: %u %s, warn: "%s" configure channel failsprepare the configuration failsant1.ch5.prf16.ant_delayant1.ch9.prf64.pg_countant1.selector_gpio_valueant2.ch5.prf16.ant_delaySCRATCH_RAMframe_filterrx_sfd_toE0&dw->msg_mutexmrxlut configuration has failed (%d) unable to create parent dir %ld register %s is protected. Write refused because device is active %s, cannot program delayed, tx_date_dtu: 0x%x, cur_time_dtu: 0x%x RXSFDDdtu_next_opONTLV_UWBCNT_OFFSant0.ch5.prf64.pg_countant2.ch9.prf16.pg_countant3.ch9.prf16.tx_powerch5.pll_locking_codephr_modepdoa_modecannot program delayed rx date_dtu=%x current_dtu=%x power_reg_2p5irq-gpiocpucannot write frame data to DW IC regulator %s failed for vdd (%d) no support for callback %scir_data%u value not handled DW3000_NFCC_COEX_SEND_CLK_SYNC%s, too late to program delayed, rx_date_dtu: 0x%x, current_dtu: 0x%x WAKE_UP%s, status: %s RXPREJRCINITSPIRDYSPI2_AVAILver_id%s, ver_id: %u, seq_num: %u rateant0.ch9.prf64.pg_delayant2.ch5.prf64.pg_delayDRXunknown DEV_ID : %x Could not disable regulator device does not support GPIO RESET controlgpio coex disabled device chip specific init has failed (%d) TIMESTAMP_DTUSLEEPcurrent_operational_statedtu_sync%s, state: %s, boot_time_ns: %llu, len_or_date: %u s32offth_boostdataant2.ch5.prf16.pg_delayant2.ch9.prf64.tx_powerant3.ch9.prf64.pg_countant0.ant1.ch9.pdoa_offsetant1.ant3.ch5.pdoa_lutcoex_delay_usDevice already powered off fail to get 'wificoex_gpio' %s Bad antennas set id selected (%d) for pdoa PGF calibration failed device enable failed: %d could not register: %d %s, timeout: %s, timeout_dtu: 0x%0x, next_operational_state: %s IDLE_RCRXSTORXFTO%s, time_ns: %lld %s, ts: %llu, f1: %u, f2: %u, f3: %u, acc: %hu, fpidx: %hu, offset: %d, filter: 0x%x adjusted_powerSPI1_AVAILnb_tlv__data_loc char[]message check failureant3.ch5.prf16.pg_delayant3.ch5.prf64.pg_countant0.ant1.ch5.pdoa_offsetant2.ant3.ch5.pdoa_offsetSET_Xrx_diagpower_regdouble banking not supported device disable failed: %d dw3000-%sdw3000_set_sched_attr failed: %d error reading dt_clamp ret=%d %.12s: power%s, return: %d, value: 0x%x RSSIRANGING_OFFSETts_dtuCOEX_ERRRXFCEbase_power%s, clock_offset_sys_time: 0x%08x (null)ant0.ch5.prf64.tx_powerant0.ch9.prf64.ant_delayant1.ch5.prf16.pg_delayant1.ch9.prf16.pg_delayant2.ch9.prf16.ant_delayant3.selector_gpiorx_sts_modegpio coex enabled : gpio %u, delay %u, interval %u, margin %u fail to get 'cpu' %s enablehard reset failed: %d copy failed DW3000_OP_STATE_IDLE_RClen|RANGING_STS_TIMESTAMP_RCTURXant_offsetRXPHD%s, res: %d, xtrim: %d, bias: %d app_boostSTOPant0.ch5.prf16.ant_delayant1.ch5.prf64.tx_powerant3.ch5.prf16.pg_countant2.ant3.ch5.pdoa_lutant2.ant3.ch9.pdoa_lutCIA_1rx_sts_lencould not transfer : %d fail to get 'wificoex_margin_us' %s test mode: test %d done in %llu ms, %llu us per read (status %x) Could not set reset gpio as output cpu cycles device init failed: %d DW3000_OP_STATE_RXcur_time_dturx_date_dtuIDLE_PLLpageSEMA_ERRPGFCAL_ERR%s, low_sys_status: 0x%08x sys_time_syncs64%s, chip: %s, sts: %u, cir_pwr: %u, pacc_cnt: %u, prf_64mhz: %u, dgc_dec: %u session_idnext_duration_dtuant1.ch5.prf16.pg_countant1.ch5.prf64.ant_delayant1.capsant0.ant3.ch9.pdoa_offsetch5.wifi_coex-enabledtx_phrratetx_antdlyrx_phr_raterx_paclenfail to get 'wificoex_delay_us' %s qos_latency&x->waitdevice reset failed: %d DW3000_OP_STATE_TXDW3000_NFCC_COEX_SEND_STOPRANGING_STS_FOMTXSTSRUNutimef3seq_num%s, next_timestamp_dtu: 0x%08x, next_duration_dtu: 0x%08x %s, mode: %d ant2.ch9.prf64.pg_countant3.ch5.prf16.tx_powerant0.ant2.ch5.pdoa_offsetchip version found : %x could not read the frame info : %d fail to access register %s (%ld) 0x%llx DW3000_PWR_IDLEKEEP_RANGING_CLOCKRXSTSLCSSERRresult%s, res: %d, gpio: %u, value: %u f1next_timestamp_dtutypeant1.ch9.prf16.ant_delayant2.portant0.ant2.ch9.pdoa_lutant2.ant3.ch9.pdoa_offsetGPIO_CTRLBad antennas selected or bad configuration ant1=%d (port=%d), ant2=%d (port=%d) memory allocation failed for cir data buffer &dw->rx.lockWiFi coexistence configuration has failed (%d) Off state: count: %llu dur ns: %llu Deep sleep state: count: %llu dur ns: %llu Run state: count: %llu dur ns: %llu Idle state: count: %llu dur ns: %llu Tx state: count: %llu dur ns: %llu Rx state: count: %llu dur ns: %llu Interrupts: count: %lld device power-off failed: %d device power on failed: %d dt_clamp=%d debugfs directory creation failed %s is not valid value DW3000_PWR_RXSP2STS_MODE_MASKtx_date_dtutimeout_dtuAES_ERRRXFCG%s, operational_state: %s clock_offset_sys_timeSESSION_TIME0../google-modules/uwb/qorvo/dw3000/kernel/drivers/net/ieee802154/dw3000_trc.hReading from NFCC exceed SCRATCH_AP_SIZEant0.ch9.prf64.tx_powerant2.selector_gpio_valueant1.ant3.ch5.pdoa_offsetpower_statsDW3000_OP_STATE_WAKE_UPdw_name%s RANGING_FOMIRQSoperational_statebiaschan%s, type: %s, data: %s ant0.portant2.ch5.prf16.tx_powerant2.ch5.prf64.pg_countant2.ch9.prf16.tx_powerant3.ch9.prf16.ant_delayEXT_SYNCRF_CALIN_PTR_CFGreset-gpioInvalid or unmanaged operational state %d, current state: %d test mode: cannot create perf_hw_evt %d (err %ld) device OTP read has failed (%d) cir_configDW3000_OP_STATE_OFFDW3000_PWR_DEEPSLEEP%s, flags: %s RXPTOCIA_DONETXFRBIDLEprf_64mhzSLOT_LIST_UUSstart%s, send: %s, idle_duration_dtu: %d, send_timestamp_dtu: 0x%08x (((((((((((((( xx*nfcc_coex_margin_dtu`dhilptux|  $(),-./02||,.||(*||$&|| "|||| $)---****TVyd,.L    l l QJ !!|  ?  ?>~66>}~d,T!.,Q    l l QJ !!|  ?  ?>~66>}>n~~@G6M6^6_]_stats_enabled, X ` < h oo8Gi?Y.ESL6SiZ0fa  Yg nP u " 88?mE L S{Zsaq  zg )ns.u"spitestsP  @ @ @H @  lna_pa_modedecawave,dw3000dw3000min_clamp_valuecount %u filter 0x%x offset %d `@ ``@ ` @ @ @ @ @ @ @ @      @      !#&),/26:?DDFHJMPSVY]afkq4 dw3000?#EH6T=H  ThW(=TjVl#T&҈lS=T҈h%lgTȜ렣Th٨(PHTȳLhp ThҨ(%(,TlҨκH~(a,!T4覧(D:T(ފ(ݪ]WcTFH6`T҈$ȇhV!Tv҈HlT h}Th2H#l8Tar`T=H TH"(GHeGAThHҽTH 2|,Th(,6T?Hs(]TȳLhp`TH!HdqaTyȋHƬL7lT(3҈z 4TȦ(bȮH[TW(=렑T聡(D~ATH҈:((wTҨH7h3T(J~YTҨ(%(T(~҈`Hȯ!T+(A҈cT(K{,2T( hlWTw҈H TEH@HT H(HL,T(ҍH·80TH҈Ư,UTHҽ`T((TH?`/T7҈Ȣ,TTȕjV`TH(hS끎T(7,/Th҈("1RTlҨκH~(a`T(豨Hh!Th`H$l.TN,QT( h}`}TWTҨB_(-TȨҨhOTh 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SLOT_LIST_UUS__TRACE_SYSTEM_DW3000_NFCC_COEX_TLV_TYPE_TLV_UWBCNT_OFFS__TRACE_SYSTEM_DW3000_NFCC_COEX_TLV_TYPE_ERROR__TRACE_SYSTEM_DW3000_OP_STATE_WAKE_UP__TRACE_SYSTEM_DW3000_NFCC_COEX_SEND_STOP__TRACE_SYSTEM_DW3000_OP_STATE_DEEP_SLEEP__TRACE_SYSTEM_DW3000_OP_STATE_SLEEP__TRACE_SYSTEM_DW3000_PWR_DEEPSLEEP__TRACE_SYSTEM_DW3000_PWR_RUN__TRACE_SYSTEM_DW3000_OP_STATE_IDLE_PLL__TRACE_SYSTEM_DW3000_DSS_STAT_SPI2_AVAIL_BIT_MASK__TRACE_SYSTEM_DW3000_DSS_STAT_SPI1_AVAIL_BIT_MASK__TRACE_SYSTEM_DW3000_PWR_OFF__TRACE_SYSTEM_DW3000_OP_STATE_OFF__TRACE_SYSTEM_DW3000_PWR_IDLE__TRACE_SYSTEM_DW3000_OP_STATE_INIT_RC__TRACE_SYSTEM_DW3000_OP_STATE_IDLE_RC__TRACE_SYSTEM_DW3000_NFCC_COEX_SEND_CLK_SYNC__TRACE_SYSTEM_DW3000_NFCC_COEX_TLV_TYPE_UNSPECbpf_trace_run9fine_gain_lut_chan9dw3000_e0_get_config_mrxlut_chan.dw3000_e0_configmrxlut_ch9dw3000_d0_get_config_mrxlut_chan.dw3000_d0_configmrxlut_ch9dw3000_c0_get_config_mrxlut_chan.dw3000_c0_configmrxlut_ch9dw3000_default_lut_ch9$d.2999$d.1999$d.999$d.2899$x.1899$d.899$x.2799$d.1799$x.799$x.2699$d.1699$x.699$x.2599$d.1599$d.599$d.2499$d.1499$x.499$d.3399$x.2399$d.1399$x.399$d.3299.Ltmp2299$x.2299$d.1299$d.299$d.3199$x.2199$d.1199$x.199$d.3099$x.2099$x.1099$x.99$d.2989$d.1989$d.989$x.2889$x.1889$d.889$x.2789$d.1789$d.789$x.2689$d.1689$d.689$d.2589$x.1589$d.589$x.2489$d.1489$d.489$d.3389$x.2389$x.1389$x.389$d.3289$x.2289$d.1289$d.289$d.3189$x.2189$d.1189$x.189$d.3089$x.2089$d.1089$x.89.Ltmp2979$d.2979$x.1979$x.979$x.2879$x.1879$d.879.Ltmp779$x.2779.Ltmp1779$x.1779$d.779$d.2679$x.1679$d.679$x.2579$d.1579$x.579$x.2479$x.1479$d.479$d.3379$x.2379$d.1379$x.379$d.3279$x.2279$d.1279$d.279$d.3179$x.2179$d.1179$d.179$d.3079$x.2079$d.1079$x.79$d.2969$x.1969$x.969$x.2869$d.1869$d.869$x.2769$x.1769$d.769$x.2669$x.1669$x.669$x.2569$x.1569$x.569__UNIQUE_ID_description469$d.2469$x.1469$x.469$d.3369$x.2369$d.1369$x.369__UNIQUE_ID_alias269$d.3269$x.2269$d.1269$d.269$d.3169$x.2169$d.1169$d.169$d.3069$x.2069$x.1069$x.69$d.2959$x.1959$x.959$x.2859$x.1859$x.859$x.2759$d.1759$d.759$x.2659$d.1659$x.659$d.2559$x.1559$x.559$x.2459$x.1459$x.459$d.3359$x.2359$x.1359$d.359$d.3259$x.2259$x.1259$x.259$d.3159$x.2159$x.1159$x.159$d.3059$x.2059$x.1059$x.59$d.2949$x.1949$x.949$x.2849$x.1849$x.849$x.2749$d.1749$x.749$d.2649$x.1649$x.649$x.2549$d.1549$x.549$x.2449$x.1449$d.449$d.3349$x.2349$d.1349$d.349$d.3249$x.2249$x.1249$x.249$d.3149$x.2149$x.1149$x.149$d.3049$x.2049$x.1049$x.49$d.2939$d.1939$x.939$x.2839$d.1839$d.839$x.2739$x.1739$x.739$x.2639$x.1639$x.639$x.2539$x.1539$d.539$x.2439.Ltmp1439$x.1439$d.439$d.3339$x.2339$d.1339$d.339.Ltmp239$d.3239$x.2239$x.1239$d.239$d.3139$x.2139$d.1139$d.139$d.3039$x.2039$x.1039$d.39$d.2929$d.1929$x.929$x.2829$d.1829$d.829$x.2729$x.1729$x.729.Ltmp2629$x.2629$d.1629$d.629$d.2529$x.1529$d.529$d.3429$x.2429$d.1429$x.429$d.3329$x.2329$x.1329$d.329$d.3229.Ltmp2229$x.2229$x.1229$d.229$d.3129$x.2129$d.1129$d.129$d.3029$d.2029$x.1029$d.29$d.2919$x.1919$x.919$x.2819$d.1819$d.819$x.2719$d.1719$x.719$d.2619$d.1619$d.619$x.2519$x.1519$x.519$d.3419$x.2419$d.1419$x.419dw3000_handle_idle_timeout.419$d.3319$x.2319$x.1319$x.319$d.3219$x.2219$x.1219$d.219$d.3119$x.2119$d.1119$d.119$d.3019$x.2019$x.1019$x.19trace_dw3000_nfcc_coex_err.19$d.2909$x.1909$x.909$x.2809$d.1809$x.809$x.2709$d.1709$x.709$x.2609$d.1609$x.609$x.2509$x.1509$x.509$x.2409$d.1409$x.409trace_dw3000_return_int.409$d.3309$x.2309$x.1309$x.309$d.3209$x.2209$x.1209$d.209$d.3109$x.2109.Ltmp1109$d.1109$d.109$d.3009$d.2009$x.1009$d.9dw3000_reg_modify8.Ltmp8bpf_trace_run8dw3000_reg_write8dw3000_reg_read8$d.2998$x.1998$x.998$d.2898$d.1898$x.898$x.2798$x.1798$x.798$x.2698$x.1698$x.698$d.2598$x.1598$x.598$x.2498$x.1498$x.498$d.3398.Ltmp2398$d.2398$x.1398$d.398$d.3298$d.2298$x.1298$x.298$d.3198.Ltmp2198$x.2198$x.1198$d.198$d.3098$x.2098$x.1098$d.98$d.2988$x.1988$x.988$x.2888$d.1888$x.888$x.2788$x.1788$x.788$d.2688$x.1688$x.688$x.2588$x.1588$x.588$x.2488$x.1488$x.488$d.3388$d.2388$x.1388$d.388$d.3288$x.2288$x.1288$x.288$d.3188$d.2188$x.1188$d.188$d.3088$x.2088$x.1088$d.88$d.2978$d.1978$d.978.Ltmp878$x.2878.Ltmp1878$d.1878$x.878$x.2778$d.1778$x.778$x.2678$d.1678$x.678$x.2578.Ltmp1578$x.1578$d.578$d.2478$d.1478$x.478$d.3378$x.2378$x.1378$d.378$d.3278$d.2278$x.1278$x.278$d.3178$d.2178$x.1178$x.178$d.3078$x.2078$x.1078$d.78$d.2968$d.1968$x.968$x.2868$x.1868$x.868$x.2768$d.1768$x.768$x.2668$x.1668$d.668$d.2568$d.1568$d.568__UNIQUE_ID_author468$x.2468$d.1468$x.468$d.3368$d.2368$x.1368$d.368__UNIQUE_ID_alias268$d.3268$d.2268$x.1268$x.268$d.3168$x.2168$x.1168$x.168$d.3068$x.2068$d.1068$d.68$d.2958$d.1958$d.958$x.2858$d.1858$d.858$d.2758$x.1758$x.758$d.2658$x.1658$d.658$x.2558$d.1558$d.558$x.2458$d.1458$x.458$d.3358$d.2358$d.1358$x.358$d.3258$x.2258$d.1258$d.258$d.3158$d.2158$d.1158$d.158$d.3058.Ltmp2058$x.2058$d.1058$d.58$d.2948$d.1948$x.948$x.2848$d.1848$x.848$x.2748$x.1748$d.748$x.2648$d.1648$d.648$x.2548$x.1548$d.548$d.2448$d.1448$x.448$d.3348$x.2348$x.1348$x.348$d.3248$d.2248$d.1248$d.248$d.3148$d.2148$d.1148$d.148$d.3048$d.2048$d.1048$d.48$d.2938$x.1938$d.938.Ltmp2838$x.2838$x.1838$x.838$x.2738$d.1738$x.738$x.2638$d.1638$d.638$d.2538$x.1538$x.538$x.2438$x.1438$x.438.Ltmp338$d.3338$d.2338$x.1338$x.338$d.3238$d.2238$x.1238$x.238$d.3138$x.2138$x.1138$x.138$d.3038$x.2038$d.1038$x.38$d.2928$x.1928$d.928$x.2828$x.1828$x.828.Ltmp2728$x.2728$x.1728$d.728$d.2628$x.1628$x.628$x.2528$x.1528$x.528$d.3428$d.2428$x.1428$x.428$d.3328$d.2328$d.1328$x.328$d.3228$x.2228$d.1228$x.228$d.3128.Ltmp2128$d.2128$x.1128$x.128$d.3028$x.2028$d.1028$x.28$d.2918$d.1918$d.918$x.2818$x.1818$x.818$x.2718$x.1718$x.718$x.2618$x.1618$x.618$x.2518$d.1518$x.518$d.3418$d.2418$x.1418$x.418$d.3318$x.2318$d.1318$d.318$d.3218$d.2218$x.1218$x.218$d.3118$d.2118$x.1118$x.118$d.3018$x.2018$x.1018$d.18$d.2908$x.1908$d.908$x.2808$x.1808$d.808$x.2708$x.1708$d.708$x.2608$x.1608$x.608$d.2508$d.1508$x.508$d.3408$x.2408$x.1408$x.408$d.3308$d.2308$x.1308$d.308$d.3208$d.2208.Ltmp1208$x.1208$x.208$d.3108$x.2108$x.1108$x.108$d.3008$x.2008$x.1008$x.8$d.8bpf_trace_run7_note_7$d.2997$d.1997$d.997$d.2897$x.1897$d.897$x.2797$d.1797$d.797$x.2697$d.1697$x.697$x.2597$d.1597$d.597.Ltmp2497$x.2497$d.1497$x.497$d.3397$x.2397$d.1397$x.397$d.3297$x.2297$d.1297$d.297$d.3197$x.2197$d.1197$x.197$d.3097$x.2097$x.1097$x.97$d.2987$d.1987$x.987$x.2887$x.1887$x.887$x.2787$d.1787$d.787$x.2687$x.1687$d.687$x.2587$d.1587$x.587$d.2487$d.1487$d.487$d.3387$x.2387$x.1387$x.387$d.3287$x.2287$d.1287$d.287$d.3187$x.2187$x.1187$x.187$d.3087$x.2087$d.1087$x.87.Ltmp977$d.2977.Ltmp1977$x.1977$x.977$x.2877$x.1877$d.877$x.2777$x.1777$x.777$x.2677$x.1677$x.677.Ltmp577$d.2577$d.1577$x.577$x.2477$x.1477$d.477$d.3377$x.2377$d.1377$x.377$d.3277$x.2277$d.1277$d.277$d.3177$x.2177$d.1177$d.177$d.3077$x.2077$d.1077$x.77$d.2967$x.1967$x.967$x.2867$d.1867$x.867$x.2767$x.1767$d.767$d.2667$d.1667$x.667$x.2567$x.1567$x.567__UNIQUE_ID_license467$x.2467$x.1467$x.467$d.3367$x.2367$x.1367$x.367__UNIQUE_ID_alias267$d.3267$x.2267$d.1267$d.267$d.3167$x.2167$x.1167$d.167$d.3067$x.2067$x.1067$x.67$d.2957$x.1957$x.957$x.2857$x.1857$x.857$x.2757$d.1757$x.757$x.2657$d.1657$x.657$x.2557$x.1557$x.557$d.2457$x.1457$x.457$d.3357$x.2357$x.1357$d.357$d.3257$x.2257$x.1257$x.257$d.3157$x.2157$x.1157$x.157$d.3057$x.2057$x.1057$x.57$d.2947$x.1947$x.947$x.2847$x.1847$x.847$x.2747$x.1747$x.747$x.2647.Ltmp1647$x.1647$x.647$d.2547$x.1547$x.547$x.2447$x.1447$d.447$d.3347$x.2347$d.1347$x.347$d.3247$x.2247$x.1247$x.247$d.3147$x.2147$x.1147$x.147$d.3047$x.2047$x.1047$x.47$d.2937$x.1937$x.937$x.2837$d.1837$d.837$x.2737$x.1737$x.737$d.2637$x.1637$x.637$x.2537$x.1537$d.537.Ltmp437$x.2437$x.1437$x.437$d.3337$x.2337$d.1337$d.337$d.3237$x.2237$x.1237$d.237$d.3137$x.2137$d.1137$d.137$d.3037$x.2037$x.1037$d.37$d.2927$x.1927$x.927$x.2827$x.1827$d.827$x.2727$x.1727$x.727$x.2627$d.1627$d.627$x.2527$x.1527$d.527$d.3427$x.2427$d.1427$x.427$d.3327$x.2327$x.1327$d.327$d.3227$x.2227$x.1227$x.227$d.3127$x.2127$d.1127$d.127$d.3027$d.2027$x.1027$d.27$d.2917$x.1917$x.917$x.2817$d.1817$x.817$x.2717$d.1717$x.717$x.2617$d.1617$d.617$d.2517$x.1517$x.517$d.3417$x.2417$d.1417$x.417$d.3317$x.2317$x.1317$x.317$d.3217$x.2217$x.1217$d.217$d.3117$x.2117$d.1117$d.117$d.3017$x.2017$x.1017$x.17$d.2907$x.1907$x.907$x.2807$d.1807$x.807$x.2707$x.1707$x.707$d.2607$d.1607$x.607$x.2507$x.1507$x.507$d.3407$x.2407$d.1407$x.407$d.3307$x.2307.Ltmp1307$x.1307$x.307$d.3207$x.2207$x.1207$x.207.Ltmp107$d.3107$x.2107$d.1107$d.107$d.3007$d.2007$x.1007trace_dw3000_nfcc_coex_err.7$d.7$d.2996$x.1996$x.996$d.2896$x.1896$x.896$x.2796$x.1796$x.796$x.2696$x.1696$x.696.Ltmp2596$x.2596$x.1596$x.596$d.2496$x.1496$x.496$d.3396$x.2396$x.1396$d.396$d.3296$d.2296$x.1296$x.296$d.3196$d.2196$x.1196$d.196$d.3096$x.2096$x.1096$d.96$d.2986$x.1986$d.986$x.2886$d.1886$x.886$x.2786$x.1786$x.786$x.2686$d.1686$x.686$d.2586$x.1586$x.586$x.2486$x.1486$x.486$d.3386$d.2386$x.1386$x.386$d.3286$d.2286$x.1286$x.286$d.3186$x.2186$x.1186$x.186$d.3086$x.2086$x.1086$d.86.Ltmp2976$d.2976$d.1976$d.976$x.2876$d.1876$x.876$x.2776$d.1776$x.776$d.2676$d.1676$x.676$x.2576$x.1576$d.576$x.2476$d.1476$x.476$d.3376$d.2376$x.1376$d.376$d.3276$x.2276$x.1276$x.276$d.3176$d.2176$x.1176$x.176$d.3076$x.2076.Ltmp1076$x.1076$d.76$d.2966$d.1966$d.966$x.2866$x.1866$d.866$d.2766$x.1766$x.766$x.2666$x.1666$d.666$x.2566$x.1566$x.566__UNIQUE_ID_min_clamp_value466__UNIQUE_ID_lna_pa_mode466$d.2466$d.1466$x.466$d.3366$x.2366$x.1366$x.366__UNIQUE_ID_depends266$d.3266.Ltmp2266$d.2266$x.1266$x.266$d.3166$d.2166$x.1166$x.166$d.3066$x.2066$d.1066$d.66$d.2956$d.1956$d.956$x.2856$d.1856$d.856$d.2756$x.1756$d.756$x.2656$x.1656$x.656$d.2556$x.1556$d.556$x.2456$d.1456$x.456$d.3356$d.2356$d.1356$x.356$d.3256$d.2256$d.1256$d.256$d.3156$x.2156$d.1156$d.156$d.3056$x.2056$d.1056$d.56$d.2946$x.1946$x.946$x.2846$x.1846$x.846.Ltmp746$x.2746.Ltmp1746$d.1746$d.746$d.2646$d.1646$d.646$x.2546$x.1546$d.546$d.2446$d.1446$x.446$d.3346$d.2346$x.1346$d.346$d.3246$x.2246$d.1246$x.246$d.3146$d.2146$d.1146$d.146$d.3046$d.2046$d.1046$d.46$d.2936$d.1936$d.936$x.2836$x.1836$x.836$x.2736$d.1736$d.736$x.2636$d.1636$x.636.Ltmp536$x.2536$x.1536$x.536$d.2436$d.1436$x.436$d.3336$x.2336$x.1336$x.336$d.3236$d.2236$d.1236$x.236$d.3136$d.2136$x.1136$x.136$d.3036$d.2036$d.1036$x.36$d.2926$d.1926$x.926$x.2826$x.1826$x.826$x.2726$x.1726$d.726$x.2626$x.1626$x.626$d.2526$x.1526$x.526$d.3426$x.2426$x.1426$x.426$d.3326$d.2326$d.1326$x.326$d.3226$d.2226$d.1226$x.226$d.3126$x.2126$x.1126$x.126$d.3026$x.2026$x.1026$x.26dw3000_reg_modify16dw3000_reg_write16dw3000_reg_read16$d.2916$x.1916$d.916$x.2816$x.1816$d.816$x.2716$x.1716$d.716$d.2616$x.1616$x.616$x.2516$d.1516$x.516$d.3416$d.2416$x.1416$x.416$d.3316$d.2316$d.1316$d.316$d.3216$x.2216$x.1216$x.216$d.3116$d.2116$x.1116$x.116$d.3016$x.2016$d.1016$d.16$d.2906$x.1906$x.906$x.2806$x.1806$d.806$x.2706$x.1706$d.706$x.2606$x.1606$x.606$x.2506$d.1506$x.506$d.3406$d.2406.Ltmp1406$x.1406$x.406$d.3306$x.2306$x.1306$d.306.Ltmp206$d.3206$d.2206$x.1206$x.206$d.3106$x.2106$x.1106$x.106$d.3006$x.2006$x.1006$x.6bpf_trace_run5fine_gain_lut_chan5dw3000_e0_get_config_mrxlut_chan.dw3000_e0_configmrxlut_ch5dw3000_d0_get_config_mrxlut_chan.dw3000_d0_configmrxlut_ch5dw3000_c0_get_config_mrxlut_chan.dw3000_c0_configmrxlut_ch5dw3000_default_lut_ch5$d.2995$d.1995$d.995$x.2895$x.1895$d.895$x.2795$d.1795$d.795.Ltmp2695$x.2695$d.1695$d.695$d.2595$d.1595$d.595$x.2495$d.1495$x.495$d.3395$x.2395$d.1395$x.395$d.3295$x.2295$d.1295$d.295$d.3195$x.2195$d.1195$x.195$d.3095.Ltmp2095$x.2095$x.1095$x.95$d.2985$d.1985$x.985$x.2885$x.1885$d.885$x.2785$x.1785$d.785$d.2685$x.1685$d.685$x.2585$d.1585$x.585$x.2485$d.1485$d.485$d.3385$x.2385$d.1385$x.385$d.3285$x.2285$x.1285$x.285$d.3185$x.2185$d.1185$x.185$d.3085$x.2085$d.1085$x.85$d.2975$x.1975$x.975$x.2875$x.1875$d.875$x.2775$x.1775$d.775$x.2675$x.1675$x.675$x.2575$d.1575$x.575$d.2475$x.1475$x.475$d.3375$x.2375$d.1375$x.375$d.3275$x.2275$d.1275$d.275$d.3175$x.2175.Ltmp1175$d.1175$d.175$d.3075$x.2075$d.1075$x.75$d.2965$x.1965$x.965$x.2865$x.1865$x.865$x.2765$d.1765$d.765$x.2665$d.1665$x.665$d.2565$x.1565$x.565__UNIQUE_ID_min_clamp_valuetype465__UNIQUE_ID_lna_pa_modetype465$x.2465$x.1465$x.465$d.3365.Ltmp2365$x.2365$d.1365$d.365__UNIQUE_ID_name265$d.3265$x.2265$d.1265$x.265$d.3165.Ltmp2165$x.2165$x.1165$x.165$d.3065$x.2065$x.1065$x.65$d.2955$x.1955$x.955$x.2855$x.1855$x.855$x.2755$d.1755$x.755$d.2655$d.1655$x.655$x.2555$x.1555$x.555$x.2455$x.1455$d.455$d.3355$x.2355$x.1355$d.355$d.3255$x.2255$x.1255$x.255$d.3155$x.2155$x.1155$x.155$d.3055$x.2055$x.1055$x.55$d.2945$d.1945$x.945.Ltmp845$x.2845.Ltmp1845$d.1845$x.845$x.2745$x.1745$x.745$x.2645$x.1645$x.645__UNIQUE_ID_nfcc_coex_margin_dtu545$x.2545.Ltmp1545$x.1545$x.545$x.2445$x.1445$d.445$d.3345$x.2345$d.1345$x.345$d.3245$x.2245$x.1245$d.245$d.3145$x.2145$x.1145$x.145$d.3045$x.2045$x.1045$x.45$d.2935$x.1935$x.935.Ltmp2835$x.2835$d.1835$d.835$x.2735$x.1735$x.735$x.2635$x.1635$x.635$d.2535$d.1535$d.535$x.2435$x.1435$x.435$d.3335$x.2335$d.1335$d.335$d.3235$x.2235$x.1235$d.235$d.3135$x.2135$d.1135$d.135$d.3035$x.2035$x.1035$d.35$d.2925$x.1925$x.925$x.2825$x.1825$d.825$x.2725$d.1725$x.725$d.2625$d.1625$d.625$x.2525$x.1525$d.525$d.3425$x.2425$d.1425$x.425$d.3325$x.2325$x.1325$d.325$d.3225$x.2225$x.1225$d.225$d.3125$x.2125$d.1125$d.125$d.3025.Ltmp2025$x.2025$x.1025$d.25$d.2915$x.1915$x.915$x.2815$d.1815$x.815$x.2715$d.1715$x.715$x.2615$d.1615$d.615$x.2515$x.1515$x.515$d.3415$x.2415$d.1415$x.415dw3000_calib_ant_set_id_to_ant.set_id_to_ant.415$d.3315$x.2315$x.1315$x.315$d.3215$x.2215$x.1215$d.215$d.3115$x.2115$d.1115$d.115$d.3015$d.2015$x.1015$x.15$d.2905$x.1905$d.905$x.2805$x.1805$x.805$x.2705$d.1705$x.705$x.2605.Ltmp1605$d.1605$d.605$d.2505$x.1505$x.505$d.3405$x.2405$d.1405$x.405.Ltmp305$d.3305$x.2305$x.1305$x.305$d.3205$x.2205$d.1205$x.205$d.3105$x.2105$d.1105$d.105$d.3005$d.2005$d.1005$d.5bpf_trace_run4$d.2994$x.1994$x.994$x.2894$x.1894$x.894$x.2794$x.1794$x.794$x.2694$x.1694$x.694$x.2594$x.1594$x.594$x.2494$x.1494$x.494$d.3394$d.2394$x.1394$d.394$d.3294$x.2294$x.1294$x.294$d.3194$d.2194$x.1194$d.194$d.3094$x.2094$x.1094$d.94$d.2984$x.1984$d.984$x.2884$d.1884$x.884$x.2784$d.1784$x.784$x.2684$d.1684$x.684$x.2584$x.1584$d.584$d.2484$x.1484$x.484$d.3384$x.2384$x.1384$d.384$d.3284$d.2284$x.1284$x.284$d.3184$d.2184$x.1184$x.184$d.3084$x.2084$x.1084$d.84.Ltmp74$d.2974.Ltmp1974$d.1974$d.974$x.2874$d.1874$x.874$x.2774$d.1774$x.774$x.2674$d.1674$d.674__UNIQUE_ID_stats_enabled574$d.2574$x.1574$d.574$x.2474$d.1474$x.474$d.3374$d.2374$x.1374$d.374$d.3274$d.2274.Ltmp1274$x.1274$x.274$d.3174$x.2174$x.1174$x.174$d.3074$x.2074$x.1074$d.74trace_raw_output_dw3000_return_int_u64__tracepoint_dw3000_return_int_u64trace_event_raw_event_dw3000_return_int_u64__event_dw3000_return_int_u64print_fmt_dw3000_return_int_u64event_class_dw3000_return_int_u64trace_event_fields_dw3000_return_int_u64trace_event_type_funcs_dw3000_return_int_u64__traceiter_dw3000_return_int_u64__bpf_trace_tp_map_dw3000_return_int_u64perf_trace_dw3000_return_int_u64__bpf_trace_dw3000_return_int_u64__SCK__tp_func_dw3000_return_int_u64__tpstrtab_dw3000_return_int_u64dw3000_set_eui64$d.2964$d.1964$d.964$x.2864$d.1864$d.864$d.2764$x.1764$x.764$d.2664$x.1664$d.664$x.2564$x.1564$x.564.Ltmp2464$x.2464$d.1464$x.464$d.3364$d.2364$x.1364$x.364__UNIQUE_ID_vermagic264$d.3264$x.2264$x.1264$d.264$d.3164$d.2164$x.1164$x.164$d.3064$x.2064$d.1064$d.64$d.2954$d.1954$d.954$x.2854$d.1854$d.854$d.2754$x.1754$d.754$x.2654$x.1654$d.654$x.2554$x.1554$d.554$d.2454$d.1454$x.454$d.3354$x.2354$d.1354$x.354$d.3254$d.2254$d.1254$d.254$d.3154$d.2154$d.1154$d.154$d.3054$x.2054$d.1054$d.54.Ltmp944$d.2944.Ltmp1944$x.1944$d.944$x.2844$x.1844$x.844$x.2744$d.1744$d.744$x.2644$d.1644$d.644__UNIQUE_ID_nfcc_coex_margin_dtutype544$d.2544$x.1544$d.544$x.2444$d.1444$x.444$d.3344$d.2344$x.1344$d.344$d.3244$d.2244$d.1244$x.244$d.3144$x.2144$d.1144$x.144$d.3044$x.2044$d.1044$d.44$d.2934$d.1934$d.934$x.2834$x.1834$x.834$x.2734$d.1734$d.734$d.2634$d.1634$x.634$x.2534$x.1534$x.534$d.2434$x.1434$x.434$d.3334$d.2334$x.1334$x.334$d.3234$x.2234$d.1234$x.234trace_dw3000_coex_gpio.234$d.3134$d.2134$x.1134$x.134$d.3034$d.2034$d.1034$x.34$d.2924$d.1924$d.924$x.2824$x.1824$x.824$x.2724$x.1724$d.724$x.2624$x.1624$x.624$x.2524$x.1524$x.524$d.3424$d.2424$x.1424$x.424$d.3324$x.2324$d.1324$x.324$d.3224$d.2224$d.1224$x.224$d.3124$d.2124$x.1124$x.124$d.3024$d.2024$x.1024$x.24$d.2914$x.1914$d.914$x.2814$x.1814$d.814$x.2714$x.1714$d.714$x.2614.Ltmp1614$x.1614$x.614$d.2514$d.1514$x.514$d.3414$x.2414$x.1414$x.414$d.3314$d.2314$d.1314$d.314$d.3214$d.2214$x.1214$x.214$d.3114$x.2114$x.1114$x.114$d.3014$x.2014$d.1014$d.14$d.2904$d.1904$x.904$x.2804$x.1804$d.804$x.2704$x.1704$d.704$d.2604$x.1604$x.604$x.2504$d.1504$x.504.Ltmp404$d.3404$d.2404$x.1404$d.404$d.3304$d.2304$x.1304$x.304$d.3204$x.2204$x.1204$d.204$d.3104$x.2104$x.1104$x.104$d.3004$x.2004$x.1004$x.4$d.4bpf_trace_run3$d.2993$d.1993$d.993$x.2893$x.1893$d.893$x.2793$d.1793$d.793$x.2693$d.1693$d.693$x.2593$d.1593$d.593$d.2493$d.1493$d.493$d.3393$x.2393$d.1393$x.393$d.3293$x.2293$d.1293$d.293$d.3193$x.2193$d.1193$x.193$d.3093$x.2093$x.1093$x.93$d.2983.Ltmp1983$d.1983$x.983$x.2883$x.1883$d.883$x.2783$x.1783$d.783$x.2683$x.1683$d.683$d.2583$d.1583$x.583$x.2483$x.1483$d.483$d.3383$x.2383$d.1383$x.383$d.3283$x.2283$x.1283$d.283$d.3183$x.2183$d.1183$d.183$d.3083$x.2083$d.1083$x.83.Ltmp2973$d.2973$x.1973$x.973$x.2873$x.1873$d.873$x.2773$x.1773$d.773$d.2673$x.1673$x.673__UNIQUE_ID_stats_enabledtype573$x.2573$d.1573$x.573$x.2473$x.1473$x.473$d.3373$x.2373.Ltmp1373$d.1373$x.373$d.3273$x.2273$d.1273$d.273.Ltmp173$d.3173$x.2173$d.1173$d.173$d.3073$x.2073$d.1073$x.73$d.2963$x.1963$x.963$x.2863$x.1863$x.863$x.2763$d.1763$d.763$x.2663$d.1663$x.663.Ltmp2563$x.2563$x.1563$x.563$d.2463$x.1463$x.463$d.3363$x.2363$x.1363$d.363$d.3263$x.2263$x.1263$x.263$d.3163$x.2163$x.1163$x.163trace_raw_output_dw3000_check_operational_state.symbols.163$d.3063$x.2063$x.1063$x.63$d.2953$x.1953$x.953$x.2853$x.1853$x.853$x.2753$d.1753$x.753$x.2653$d.1653$x.653$d.2553$x.1553$x.553$x.2453$x.1453$d.453$d.3353$x.2353$x.1353$d.353$d.3253$x.2253$x.1253$x.253$d.3153$x.2153$x.1153$x.153$d.3053$x.2053$x.1053$x.53$d.2943$x.1943$x.943$x.2843$d.1843$x.843$x.2743$x.1743$x.743.Ltmp643$d.2643$x.1643$x.643$x.2543$x.1543$x.543$x.2443$x.1443$d.443$d.3343$x.2343$d.1343$x.343$d.3243$x.2243$x.1243$d.243$d.3143$x.2143$x.1143$x.143$d.3043$x.2043.Ltmp1043$x.1043$x.43$d.2933$x.1933$x.933$x.2833$d.1833$d.833$x.2733$x.1733$x.733$x.2633$x.1633$x.633$x.2533$x.1533$d.533$x.2433$x.1433$x.433$d.3333$x.2333$d.1333$d.333$d.3233$x.2233$x.1233$d.233$d.3133$x.2133$d.1133$d.133$d.3033$x.2033$x.1033$d.33$d.2923$x.1923$x.923$x.2823$d.1823$d.823$x.2723$d.1723$x.723$x.2623$d.1623$d.623$d.2523$d.1523$x.523$d.3423$x.2423$d.1423$x.423$d.3323$x.2323$x.1323$x.323$d.3223$x.2223$x.1223$d.223$d.3123$x.2123$x.1123$x.123$d.3023$x.2023$x.1023$x.23$d.2913$x.1913$x.913$x.2813$d.1813$x.813.Ltmp713$x.2713.Ltmp1713$d.1713$x.713$d.2613$d.1613$x.613$x.2513$x.1513$x.513$x.2413$d.1413$x.413$d.3313$x.2313$x.1313$x.313$d.3213$x.2213$x.1213$d.213$d.3113$x.2113$d.1113$d.113$d.3013$d.2013$x.1013$x.13$d.2903$x.1903$d.903$x.2803$d.1803$x.803$x.2703$d.1703$x.703$x.2603$d.1603$d.603.Ltmp503$x.2503.Ltmp1503$x.1503$x.503$d.3403$x.2403$d.1403$x.403$d.3303$x.2303$d.1303$d.303$d.3203$x.2203$d.1203$x.203$d.3103$x.2103$x.1103$x.103$d.3003$d.2003$d.1003dw3000_state_init.__key.3$x.3perf_hw_evt.3$d.3bpf_trace_run2$d.2992.Ltmp1992$x.1992$x.992$x.2892$x.1892$x.892$x.2792$x.1792$x.792$x.2692$x.1692$x.692$d.2592$x.1592$x.592$x.2492$x.1492$x.492$d.3392$d.2392$x.1392$d.392$d.3292$d.2292$x.1292$x.292$d.3192$x.2192$x.1192$d.192$d.3092$x.2092$x.1092$d.92$d.2982$x.1982$d.982$x.2882$d.1882$x.882$x.2782$d.1782$x.782$d.2682$d.1682$x.682$x.2582$x.1582$d.582$x.2482$x.1482$x.482$d.3382$d.2382$x.1382$d.382$d.3282$x.2282$x.1282$x.282$d.3182$d.2182$x.1182$x.182$d.3082$x.2082$x.1082$x.82$d.2972$d.1972$d.972$x.2872$x.1872$x.872.Ltmp3772$x.2772$d.1772$x.772$x.2672$d.1672$d.672$x.2572$x.1572$d.572$d.2472.Ltmp1472$d.1472$x.472$d.3372$x.2372$x.1372$d.372.Ltmp272$d.3272$d.2272$x.1272$x.272$d.3172$d.2172$x.1172$x.172$d.3072$x.2072$x.1072$d.72$d.2962$d.1962$d.962$x.2862$d.1862$d.862$d.2762$x.1762$x.762.Ltmp2662$x.2662$x.1662$d.662$d.2562$x.1562$x.562$x.2462$d.1462$x.462$d.3362$d.2362$d.1362$x.362$d.3262$d.2262$x.1262$d.262$d.3162$x.2162$x.1162$d.162$d.3062$x.2062$d.1062$x.62$d.2952$d.1952$d.952$x.2852$d.1852$d.852$d.2752$x.1752$d.752$d.2652$x.1652$d.652$x.2552$d.1552$d.552$d.2452$d.1452$x.452$d.3352$d.2352$x.1352$x.352$d.3252$x.2252$d.1252$d.252$d.3152$d.2152$d.1152$d.152$d.3052$x.2052$d.1052$d.52$d.2942$d.1942$d.942$x.2842$x.1842$x.842$x.2742$d.1742$d.742$x.2642$d.1642$d.642$x.2542$d.1542$x.542$d.2442$d.1442$x.442$d.3342$x.2342$x.1342$x.342$d.3242$d.2242$x.1242$x.242$d.3142$d.2142.Ltmp1142$x.1142$x.142$d.3042$x.2042$d.1042$x.42dw3000_reg_modify32trace_raw_output_dw3000_return_int_u32__tracepoint_dw3000_return_int_u32trace_event_raw_event_dw3000_return_int_u32__event_dw3000_return_int_u32print_fmt_dw3000_return_int_u32event_class_dw3000_return_int_u32trace_event_fields_dw3000_return_int_u32trace_event_type_funcs_dw3000_return_int_u32__traceiter_dw3000_return_int_u32__bpf_trace_tp_map_dw3000_return_int_u32perf_trace_dw3000_return_int_u32__bpf_trace_dw3000_return_int_u32__SCK__tp_func_dw3000_return_int_u32__tpstrtab_dw3000_return_int_u32dw3000_otp_write32dw3000_reg_write32dw3000_otp_read32dw3000_reg_read32$d.2932$x.1932$d.932$x.2832$x.1832$x.832$x.2732$d.1732$d.732$x.2632$d.1632$x.632$d.2532$d.1532$x.532$x.2432$x.1432$x.432$d.3332.Ltmp2332$d.2332$x.1332$x.332$d.3232$d.2232$d.1232$x.232$d.3132$x.2132$x.1132$x.132$d.3032$d.2032$d.1032$x.32$d.2922$x.1922$d.922$x.2822$x.1822$x.822$x.2722$x.1722$d.722$d.2622$x.1622$x.622$x.2522$x.1522$x.522$d.3422$d.2422$x.1422$x.422$d.3322$d.2322$d.1322$d.322$d.3222$x.2222$d.1222$x.222$d.3122$d.2122$x.1122$x.122$d.3022$d.2022$x.1022$d.22$d.2912$x.1912$d.912.Ltmp812$x.2812.Ltmp1812$x.1812$d.812$x.2712$x.1712$d.712$x.2612$x.1612$x.612$x.2512.Ltmp1512$d.1512$x.512$d.2412$x.1412$x.412$d.3312$x.2312$x.1312$d.312$d.3212$d.2212$x.1212$x.212$d.3112$d.2112$x.1112$x.112$d.3012$x.2012$x.1012$d.12$d.2902$d.1902$x.902$x.2802$x.1802$d.802$x.2702$x.1702$d.702$x.2602$x.1602$x.602$d.2502$x.1502$x.502$d.3402$x.2402$x.1402$d.402$d.3302$d.2302$x.1302$x.302$d.3202$d.2202$x.1202$d.202$d.3102$x.2102$d.1102$x.102$d.3002$x.2002$x.1002$x.2perf_hw_evt.2$d.2bpf_trace_run1$d.2991$d.1991$d.991$x.2891$x.1891$d.891$x.2791$d.1791$d.791$x.2691$d.1691$d.691__UNIQUE_ID_spitests591$x.2591$x.1591$d.591$x.2491$d.1491$d.491$d.3391$x.2391$x.1391$x.391$d.3291$x.2291$d.1291$d.291$d.3191$x.2191$d.1191$x.191$d.3091$x.2091$x.1091$x.91$d.2981$x.1981$x.981$x.2881$x.1881$d.881$x.2781$x.1781$d.781$x.2681$x.1681$d.681$x.2581$d.1581$x.581$d.2481$d.1481$d.481$d.3381$x.2381$d.1381$x.381$d.3281$x.2281$d.1281$d.281$d.3181$x.2181$d.1181$d.181$d.3081$x.2081$d.1081$x.81$d.2971.Ltmp1971$x.1971$x.971$x.2871$d.1871$d.871$x.2771$x.1771$d.771$x.2671$x.1671$x.671$d.2571$d.1571$x.571$x.2471$x.1471$x.471.Ltmp371$d.3371$x.2371$d.1371$x.371$d.3271$x.2271$d.1271$d.271$d.3171$x.2171$d.1171$d.171$d.3071$x.2071$x.1071$x.71$d.2961$x.1961$x.961$x.2861$x.1861$x.861$x.2761$d.1761$d.761$d.2661$d.1661$x.661$x.2561$d.1561$x.561$x.2461$x.1461$x.461$d.3361$x.2361$x.1361$d.361$d.3261$x.2261$x.1261$x.261$d.3161$x.2161$x.1161$x.161$d.3061$x.2061$x.1061$x.61$d.2951$x.1951$x.951$x.2851$x.1851$x.851$x.2751$d.1751$x.751$x.2651$d.1651$x.651$x.2551$x.1551$x.551$x.2451$x.1451$d.451$d.3351$x.2351$x.1351$d.351$d.3251$x.2251$x.1251$x.251$d.3151$x.2151$x.1151$x.151$d.3051$x.2051$x.1051$x.51.Ltmp41$d.2941$x.1941$x.941.Ltmp2841$x.2841$d.1841$x.841$x.2741$x.1741$x.741$x.2641$x.1641$x.641$d.2541$x.1541$d.541$x.2441$x.1441$d.441$d.3341$x.2341$d.1341$d.341$d.3241$x.2241.Ltmp1241$x.1241$d.241$d.3141$x.2141$d.1141$d.141$d.3041$x.2041$x.1041$d.41$d.2931$d.1931$x.931$x.2831$d.1831$d.831$x.2731$x.1731$x.731$d.2631$x.1631$d.631$x.2531$x.1531$d.531.Ltmp2431$x.2431$x.1431$x.431$d.3331$x.2331$x.1331$d.331$d.3231$x.2231$x.1231$d.231$d.3131$x.2131$d.1131$d.131$d.3031$x.2031$x.1031$d.31$d.2921$x.1921$x.921$x.2821$d.1821$x.821$x.2721$d.1721$x.721$x.2621$d.1621$d.621$x.2521$x.1521$d.521$d.3421$x.2421$d.1421$x.421$d.3321$x.2321$x.1321$x.321$d.3221$x.2221$x.1221$d.221$d.3121$x.2121$d.1121$d.121$d.3021$x.2021$x.1021$x.21.Ltmp911$d.2911.Ltmp1911$x.1911$x.911$x.2811$d.1811$x.811$x.2711$d.1711$x.711$x.2611$x.1611$x.611$d.2511$x.1511$x.511$x.2411$x.1411$x.411$d.3311$x.2311$x.1311$x.311$d.3211$x.2211$x.1211$d.211$d.3111$x.2111$d.1111$d.111$d.3011$d.2011$x.1011$x.11$d.2901$x.1901$d.901$x.2801$d.1801$x.801$x.2701$d.1701$x.701$d.2601$d.1601$d.601$x.2501$d.1501$x.501$d.3401$x.2401$d.1401$x.401$d.3301$x.2301$d.1301$d.301$d.3201$x.2201$d.1201$x.201$d.3101$x.2101$x.1101$x.101$d.3001$d.2001$d.1001perf_hw_evt.1$d.1__TRACE_SYSTEM_DW3000_NFCC_COEX_TLV_TYPE_SESSION_TIME0$d.2990$x.1990$x.990$x.2890$d.1890$x.890$x.2790$x.1790$x.790$x.2690$x.1690$x.690__UNIQUE_ID_spiteststype590$x.2590$x.1590$x.590$d.2490$x.1490$x.490$d.3390$x.2390$x.1390$d.390$d.3290$d.2290$x.1290$x.290$d.3190$d.2190$x.1190$d.190$d.3090$x.2090$x.1090$d.90$d.2980.Ltmp1980$d.1980$d.980$x.2880$d.1880$x.880$x.2780$d.1780$x.780.Ltmp680$x.2680.Ltmp1680$d.1680$x.680$d.2580$x.1580$d.580$x.2480$x.1480$x.480$d.3380$d.2380$x.1380$d.380$d.3280$d.2280$x.1280$x.280$d.3180$x.2180$x.1180$x.180$d.3080$x.2080$x.1080$d.80$d.2970$d.1970$d.970$x.2870$x.1870$x.870.Ltmp2770$x.2770$d.1770$x.770$d.2670$d.1670$d.670$x.2570$x.1570$d.570.Ltmp470$x.2470$d.1470$x.470$d.3370$d.2370$x.1370$d.370__UNIQUE_ID_scmversion270$d.3270$x.2270$x.1270$x.270$d.3170$d.2170$x.1170$x.170$d.3070$x.2070$x.1070$d.70$d.2960$d.1960$d.960$x.2860$d.1860$d.860$d.2760$x.1760$x.760$x.2660$x.1660$d.660$x.2560$x.1560$d.560$d.2460$x.1460$x.460$d.3360$x.2360$x.1360$x.360$d.3260$d.2260$d.1260$d.260$d.3160$d.2160$d.1160$d.160$d.3060$x.2060$d.1060$d.60$d.2950$d.1950$d.950$x.2850$d.1850$d.850$d.2750$x.1750$d.750$x.2650$x.1650$d.650$d.2550$x.1550$d.550$x.2450$d.1450$x.450$d.3350$d.2350$x.1350$x.350$d.3250$d.2250$d.1250$d.250$d.3150$x.2150$d.1150$d.150$d.3050$x.2050$x.1050$d.50$d.2940$x.1940$d.940$x.2840$x.1840$x.840$x.2740$d.1740$d.740$d.2640$d.1640$d.640$x.2540$x.1540$x.540$d.2440$x.1440$x.440$d.3340$d.2340.Ltmp1340$x.1340$x.340$d.3240$x.2240$x.1240$x.240.Ltmp140$d.3140$d.2140$x.1140$x.140$d.3040$d.2040$d.1040$x.40$d.2930$x.1930$d.930$x.2830$x.1830$x.830$x.2730$d.1730$d.730$x.2630$x.1630$x.630.Ltmp2530$x.2530$x.1530$x.530$d.2430$x.1430$x.430$d.3330$x.2330$d.1330$x.330$d.3230$d.2230$d.1230$x.230$d.3130$d.2130$x.1130$x.130$d.3030$x.2030$x.1030$x.30$d.2920$d.1920$d.920$x.2820$x.1820$x.820$x.2720$x.1720$d.720$x.2620$x.1620$x.620$d.2520$d.1520$x.520$d.3420$x.2420$x.1420$x.420$d.3320$d.2320$d.1320$d.320$d.3220$d.2220$d.1220$x.220$d.3120$x.2120$x.1120$x.120$d.3020$d.2020$x.1020$d.20$d.2910$x.1910$d.910$x.2810$x.1810$d.810$x.2710$x.1710$d.710.Ltmp610$d.2610$x.1610$x.610$x.2510$d.1510$x.510$d.2410$x.1410trace_dw3000_power_stats.410$d.410$d.3310$d.2310$x.1310$d.310$d.3210$x.2210$x.1210$x.210$d.3110$d.2110$x.1110$x.110$d.3010$x.2010.Ltmp1010$x.1010$d.10$d.2900$d.1900$x.900$x.2800$x.1800$d.800$x.2700$x.1700$d.700$x.2600$x.1600$x.600$x.2500$x.1500$x.500$d.3400$d.2400$x.1400$d.400$d.3300$x.2300$x.1300$x.300$d.3200$d.2200$x.1200$d.200$d.3100$x.2100$x.1100$d.100$d.3000$x.2000$x.1000perf_hw_evt.0@|&&P+ 2b 2lA2gbM a\8@zP1 A@XV1@81@1@А01H,C@x18 $3@xH10 @1  @@/1g@L1  kf@x!1Nx+I@h7@1.@<1 ^.PY@H?+1"~H?py@jP1$A @r1&S03LoV^'KK@@01+@P)y$y #9P 3'8 h1 5{