| /art/compiler/optimizing/ |
| D | code_generator_vector_arm64_sve.cc | 641 __ And(dst.VnB(), p_reg, lhs.VnB(), rhs.VnB()); in VisitVecAnd() local
645 __ And(dst.VnH(), p_reg, lhs.VnH(), rhs.VnH()); in VisitVecAnd() local
649 __ And(dst.VnS(), p_reg, lhs.VnS(), rhs.VnS()); in VisitVecAnd() local
653 __ And(dst.VnD(), p_reg, lhs.VnD(), rhs.VnD()); in VisitVecAnd() local
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| D | intrinsics_riscv64.cc | 412 __ And(out, in, temp1); in GenerateReverse() local
413 __ And(temp2, temp2, temp1); in GenerateReverse() local
420 __ And(out, out, temp1); in GenerateReverse() local
421 __ And(temp2, temp2, temp1); in GenerateReverse() local
428 __ And(out, out, temp1); in GenerateReverse() local
429 __ And(temp2, temp2, temp1); in GenerateReverse() local
513 __ And(rd, rs1, tmp2); // Make sure the result is zero if the input is zero. in VisitIntegerHighestOneBit() local
530 __ And(rd, rs1, tmp2); // Make sure the result is zero if the input is zero. in VisitLongHighestOneBit() local
544 __ And(rd, rs1, tmp); in VisitIntegerLowestOneBit() local
558 __ And(rd, rs1, tmp); in VisitLongLowestOneBit() local
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| D | code_generator_arm_vixl.cc | 1139 __ And(out, first, second); in GenerateDataProcInstruction() local
4560 __ And(out, dividend, abs_imm - 1); in DivRemByPowerOfTwo() local
5077 __ And(temp1, temp1, temp2); in GenerateMinMaxFloat() local
5347 __ And(shift_right, RegisterFrom(rhs), 0x1F); in HandleLongRotate() local
5479 __ And(out_reg, second_reg, kMaxIntShiftDistance); in HandleShift() local
5515 __ And(o_l, second_reg, kMaxLongShiftDistance); in HandleShift() local
5534 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
5553 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
8905 __ And(out, first, value); in GenerateAndConst() local
9023 __ And(out_reg, first_reg, second_reg); in HandleBitwiseOperation() local
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| D | intrinsics_arm_vixl.cc | 753 __ And(temp2, temp2, temp3); in GenerateStringCompareToLoop() local
754 __ And(out, out, temp3); in GenerateStringCompareToLoop() local
2069 __ And(out_reg_hi, out_reg_hi, in_reg_hi); in GenLowestOneBit() local
2093 __ And(out, temp, in); in GenLowestOneBit() local
3830 __ And(LowRegisterFrom(new_value), LowRegisterFrom(loaded_value), LowRegisterFrom(arg)); in GenerateGetAndUpdate() local
3831 __ And(HighRegisterFrom(new_value), HighRegisterFrom(loaded_value), HighRegisterFrom(arg)); in GenerateGetAndUpdate() local
3833 __ And(RegisterFrom(new_value), RegisterFrom(loaded_value), RegisterFrom(arg)); in GenerateGetAndUpdate() local
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| D | code_generator_arm64.cc | 2383 __ And(dst, lhs, rhs); in HandleBinaryOp() local
2585 __ And(out, left, right_operand); in VisitDataProcWithShifterOp() local
6171 __ And(out, dividend, abs_imm - 1); in GenerateIntRemForPower2Denom() local
6175 __ And(out, dividend, 1); in GenerateIntRemForPower2Denom() local
6182 __ And(out, dividend, abs_imm - 1); in GenerateIntRemForPower2Denom() local
6183 __ And(temp, temp, abs_imm - 1); in GenerateIntRemForPower2Denom() local
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| D | code_generator_vector_arm64_neon.cc | 800 __ And(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecAnd() local
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| D | code_generator_riscv64.cc | 1500 __ And(tmp, tmp, tmp2); in DivRemByPowerOfTwo() local
2168 __ And(rd, rs1, rs2); in HandleBinaryOp() local
5206 __ And(tmp, tmp, xor_reg); in VisitSelect() local
5375 __ And(dst, dst, tmp); // Cleared for NaN. in VisitTypeConversion() local
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| D | intrinsics_arm64.cc | 476 __ And(dst, temp, src); in GenLowestOneBit() local
1684 __ And(new_value, old_value_reg, arg.IsX() ? arg.X() : arg.W()); in GenerateGetAndUpdate() local
2216 __ And(temp1, temp, Operand(1)); // Extract compression flag. in VisitStringEquals() local
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| /art/test/953-invoke-polymorphic-compiler/src/ |
| D | Main.java | 182 private static boolean And(boolean lhs, boolean rhs) { in And() method in Main
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 704 ___ And(reg.X(), reg.X(), ~kIndirectRefKindMask); in DecodeJNITransitionOrLocalJObject() local
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 2604 TEST_F(AssemblerRISCV64Test, And) { in TEST_F() argument
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| D | assembler_riscv64.cc | 503 void Riscv64Assembler::And(XRegister rd, XRegister rs1, XRegister rs2) { in And() function in art::riscv64::Riscv64Assembler
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