1 /*
2 * Copyright (C) 2023 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "gtest/gtest.h"
18
19 #include <malloc.h> // memalign
20 #include <sys/mman.h>
21 #include <unistd.h>
22
23 #include <algorithm> // copy_n, fill_n
24 #include <cfenv>
25 #include <csignal>
26 #include <cstdint>
27 #include <cstring>
28 #include <memory>
29
30 #include "berberis/base/bit_util.h"
31 #include "berberis/base/checks.h"
32 #include "berberis/guest_os_primitives/guest_thread.h"
33 #include "berberis/guest_state/guest_addr.h"
34 #include "berberis/guest_state/guest_state.h"
35 #include "berberis/interpreter/riscv64/interpreter.h"
36 #include "berberis/intrinsics/guest_cpu_flags.h" // GuestModeFromHostRounding
37 #include "berberis/intrinsics/guest_rounding_modes.h" // ScopedRoundingMode
38 #include "berberis/intrinsics/simd_register.h"
39 #include "berberis/intrinsics/vector_intrinsics.h"
40 #include "berberis/runtime_primitives/memory_region_reservation.h"
41 #include "faulty_memory_accesses.h"
42
43 namespace berberis {
44
45 namespace {
46
47 #if defined(__i386__)
48 constexpr size_t kRegIP = REG_EIP;
49 #elif defined(__x86_64__)
50 constexpr size_t kRegIP = REG_RIP;
51 #else
52 #error "Unsupported arch"
53 #endif
54
55 bool sighandler_called = false;
56
FaultHandler(int,siginfo_t *,void * ctx)57 void FaultHandler(int /* sig */, siginfo_t* /* info */, void* ctx) {
58 ucontext_t* ucontext = reinterpret_cast<ucontext_t*>(ctx);
59 static_assert(sizeof(void*) == sizeof(greg_t), "Unsupported type sizes");
60 void* fault_addr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[kRegIP]);
61 void* recovery_addr = FindFaultyMemoryAccessRecoveryAddrForTesting(fault_addr);
62 sighandler_called = true;
63 CHECK(recovery_addr);
64 ucontext->uc_mcontext.gregs[kRegIP] = reinterpret_cast<greg_t>(recovery_addr);
65 }
66
67 class ScopedFaultySigaction {
68 public:
ScopedFaultySigaction()69 ScopedFaultySigaction() {
70 struct sigaction sa;
71 sa.sa_flags = SA_SIGINFO;
72 sigemptyset(&sa.sa_mask);
73 sa.sa_sigaction = FaultHandler;
74 CHECK_EQ(sigaction(SIGSEGV, &sa, &old_sa_), 0);
75 }
76
~ScopedFaultySigaction()77 ~ScopedFaultySigaction() { CHECK_EQ(sigaction(SIGSEGV, &old_sa_, nullptr), 0); }
78
79 private:
80 struct sigaction old_sa_;
81 };
82
83 // Interpreter decodes the size itself, but we need to accept this template parameter to share
84 // tests with translators.
85 template <uint8_t kInsnSize = 4>
RunOneInstruction(ThreadState * state,GuestAddr stop_pc)86 bool RunOneInstruction(ThreadState* state, GuestAddr stop_pc) {
87 InterpretInsn(state);
88 return state->cpu.insn_addr == stop_pc;
89 }
90
91 class Riscv64InterpreterTest : public ::testing::Test {
92 public:
93 // Non-Compressed Instructions.
Riscv64InterpreterTest()94 Riscv64InterpreterTest()
95 : state_{
96 .cpu = {.vtype = uint64_t{1} << 63, .frm = intrinsics::GuestModeFromHostRounding()}} {}
97
InterpretFence(uint32_t insn_bytes)98 void InterpretFence(uint32_t insn_bytes) {
99 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
100 InterpretInsn(&state_);
101 }
102
103 // Vector instructions.
104 template <typename ElementType>
TestFPExceptions(uint32_t insn_bytes)105 void TestFPExceptions(uint32_t insn_bytes) {
106 // Install the following arguments: NaN, 1.0, 1.0, NaN.
107 // Then try to mask out NaNs with vstart, vl, and mask.
108 state_.cpu.v[24] = state_.cpu.v[16] = state_.cpu.v[8] =
109 SIMD128Register{__v2du{0x7ff4'0000'0000'0000, 0x3ff0'0000'0000'0000}}.Get<__uint128_t>();
110 state_.cpu.v[25] = state_.cpu.v[17] = state_.cpu.v[9] =
111 SIMD128Register{__v2du{0x3ff0'0000'0000'0000, 0x7ff4'0000'0000'0000}}.Get<__uint128_t>();
112 state_.cpu.v[26] = state_.cpu.v[18] = state_.cpu.v[10] = SIMD128Register{
113 __v4su{
114 0x7fa0'0000, 0x3f80'0000, 0x3f80'0000, 0x7fa0'0000}}.Get<__uint128_t>();
115 state_.cpu.f[1] = 0xffff'ffff'3f80'0000;
116 state_.cpu.f[2] = 0x3ff0'0000'0000'0000;
117 ;
118 state_.cpu.vtype = (BitUtilLog2(sizeof(ElementType)) << 3) | /*vlmul=*/1;
119 // First clear exceptions and execute the instruction with vstart = 0, vl = 4.
120 // This should produce FE_INVALID with most floating point instructions.
121 EXPECT_EQ(feclearexcept(FE_ALL_EXCEPT), 0);
122 state_.cpu.vstart = 0;
123 state_.cpu.vl = 4;
124 state_.cpu.v[0] = 0b1111;
125 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
126 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
127 EXPECT_TRUE(bool(fetestexcept(FE_ALL_EXCEPT)));
128 // Mask NaNs using vstart and vl.
129 EXPECT_EQ(feclearexcept(FE_ALL_EXCEPT), 0);
130 state_.cpu.vstart = 1;
131 state_.cpu.vl = 3;
132 state_.cpu.v[0] = 0b1111;
133 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
134 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
135 EXPECT_FALSE(bool(fetestexcept(FE_ALL_EXCEPT)));
136 // Mask NaNs using mask.
137 EXPECT_EQ(feclearexcept(FE_ALL_EXCEPT), 0);
138 state_.cpu.vstart = 0;
139 state_.cpu.vl = 4;
140 state_.cpu.v[0] = 0b0110;
141 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
142 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
143 EXPECT_FALSE(bool(fetestexcept(FE_ALL_EXCEPT)));
144 }
145
146 template <size_t kNFfields>
TestVlXreXX(uint32_t insn_bytes)147 void TestVlXreXX(uint32_t insn_bytes) {
148 const auto kUndisturbedValue = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
149 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
150 SetXReg<1>(state_.cpu, ToGuestAddr(&kVectorComparisonSource));
151 for (size_t index = 0; index < 8; index++) {
152 state_.cpu.v[8 + index] = kUndisturbedValue;
153 }
154 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
155 for (size_t index = 0; index < 8; index++) {
156 EXPECT_EQ(state_.cpu.v[8 + index],
157 (index >= kNFfields
158 ? kUndisturbedValue
159 : SIMD128Register{kVectorComparisonSource[index]}.Get<__uint128_t>()));
160 }
161 }
162
163 template <typename ElementType, size_t kNFfields, size_t kLmul>
VlxsegXeiXX(uint32_t insn_bytes,const ElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (sizeof (SIMD128Register)/sizeof (ElementType))])164 void VlxsegXeiXX(
165 uint32_t insn_bytes,
166 const ElementType::BaseType (&expected_results)[kNFfields * kLmul][static_cast<int>(
167 sizeof(SIMD128Register) / sizeof(ElementType))]) {
168 VlxsegXeiXX<ElementType, UInt8, kNFfields, kLmul>(insn_bytes, expected_results);
169 VlxsegXeiXX<ElementType, UInt8, kNFfields, kLmul>(insn_bytes | 0x8000000, expected_results);
170 VlxsegXeiXX<ElementType, UInt16, kNFfields, kLmul>(insn_bytes | 0x5000, expected_results);
171 VlxsegXeiXX<ElementType, UInt16, kNFfields, kLmul>(insn_bytes | 0x8005000, expected_results);
172 VlxsegXeiXX<ElementType, UInt32, kNFfields, kLmul>(insn_bytes | 0x6000, expected_results);
173 VlxsegXeiXX<ElementType, UInt32, kNFfields, kLmul>(insn_bytes | 0x8006000, expected_results);
174 VlxsegXeiXX<ElementType, UInt64, kNFfields, kLmul>(insn_bytes | 0x7000, expected_results);
175 VlxsegXeiXX<ElementType, UInt64, kNFfields, kLmul>(insn_bytes | 0x8007000, expected_results);
176 }
177
178 template <typename DataElementType, typename IndexElementType, size_t kNFfields, size_t kLmul>
VlxsegXeiXX(uint32_t insn_bytes,const DataElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (sizeof (SIMD128Register)/sizeof (DataElementType))])179 void VlxsegXeiXX(
180 uint32_t insn_bytes,
181 const DataElementType::BaseType (&expected_results)[kNFfields * kLmul][static_cast<int>(
182 sizeof(SIMD128Register) / sizeof(DataElementType))]) {
183 constexpr size_t kElementsCount = sizeof(SIMD128Register) / sizeof(IndexElementType);
184 constexpr size_t kTotalElements =
185 sizeof(SIMD128Register) / sizeof(DataElementType) * kLmul * kNFfields;
186 // If we need more indexes than may fit into 8 vector registers then such operation is
187 // impossible on RISC-V and we should skip that combination.
188 if constexpr (sizeof(IndexElementType) * kTotalElements <= sizeof(SIMD128Register) * 8) {
189 TestVectorLoad<DataElementType, kNFfields, kLmul>(insn_bytes, expected_results, [this] {
190 for (size_t reg_no = 0; reg_no < AlignUp<kElementsCount>(kTotalElements) / kElementsCount;
191 ++reg_no) {
192 SIMD128Register index_register;
193 for (size_t index = 0; index < kElementsCount; ++index) {
194 index_register.Set(IndexElementType{static_cast<typename IndexElementType::BaseType>(
195 kPermutedIndexes[index + reg_no * kElementsCount] *
196 sizeof(DataElementType) * kNFfields)},
197 index);
198 }
199 state_.cpu.v[16 + reg_no] = index_register.Get<__uint128_t>();
200 }
201 });
202 }
203 }
204
205 template <typename ElementType, size_t kNFfields, size_t kLmul>
TestVlsegXeXX(uint32_t insn_bytes,const ElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (16/sizeof (ElementType))])206 void TestVlsegXeXX(
207 uint32_t insn_bytes,
208 const ElementType::BaseType (
209 &expected_results)[kNFfields * kLmul][static_cast<int>(16 / sizeof(ElementType))]) {
210 TestVectorLoad<ElementType, kNFfields, kLmul>(insn_bytes, expected_results, [] {});
211 // Turn Vector Unit-Stride Segment Loads and Stores into Fault-Only-First Load.
212 TestVectorLoad<ElementType, kNFfields, kLmul>(insn_bytes | 0x1000000, expected_results, [] {});
213 }
214
215 template <typename ElementType, size_t kNFfields, size_t kLmul>
TestVlssegXeXX(uint32_t insn_bytes,uint64_t stride,const ElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (16/sizeof (ElementType))])216 void TestVlssegXeXX(
217 uint32_t insn_bytes,
218 uint64_t stride,
219 const ElementType::BaseType (
220 &expected_results)[kNFfields * kLmul][static_cast<int>(16 / sizeof(ElementType))]) {
221 TestVectorLoad<ElementType, kNFfields, kLmul>(
222 insn_bytes, expected_results, [stride, this] { SetXReg<2>(state_.cpu, stride); });
223 }
224
225 template <typename ElementType, size_t kNFfields, size_t kLmul, typename ExtraCPUInitType>
TestVectorLoad(uint32_t insn_bytes,const ElementType::BaseType (& expected_results)[kNFfields * kLmul][static_cast<int> (16/sizeof (ElementType))],ExtraCPUInitType ExtraCPUInit)226 void TestVectorLoad(
227 uint32_t insn_bytes,
228 const ElementType::BaseType (
229 &expected_results)[kNFfields * kLmul][static_cast<int>(16 / sizeof(ElementType))],
230 ExtraCPUInitType ExtraCPUInit) {
231 constexpr int kElementsCount = static_cast<int>(16 / sizeof(ElementType));
232 const auto kUndisturbedValue = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
233 for (uint8_t vstart = 0; vstart <= kElementsCount * kLmul; ++vstart) {
234 for (uint8_t vl = 0; vl <= kElementsCount * kLmul; ++vl) {
235 for (uint8_t vta = 0; vta < 2; ++vta) {
236 // Handle three masking cases:
237 // no masking (vma == 0), agnostic (vma == 1), undisturbed (vma == 2)
238 for (uint8_t vma = 0; vma < 3; ++vma) {
239 state_.cpu.vtype = (vma & 1) << 7 | (vta << 6) |
240 (BitUtilLog2(sizeof(ElementType)) << 3) | BitUtilLog2(kLmul);
241 state_.cpu.vstart = vstart;
242 state_.cpu.vl = vl;
243 uint32_t insn_bytes_with_vm = insn_bytes;
244 // If masking is supposed to be disabled then we need to set vm bit (#25).
245 if (!vma) {
246 insn_bytes_with_vm |= (1 << 25);
247 }
248 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes_with_vm);
249 SetXReg<1>(state_.cpu, ToGuestAddr(&kVectorCalculationsSource));
250 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
251 for (size_t index = 0; index < 8; index++) {
252 state_.cpu.v[8 + index] = kUndisturbedValue;
253 }
254 ExtraCPUInit();
255 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
256 EXPECT_EQ(state_.cpu.vstart, 0);
257 EXPECT_EQ(state_.cpu.vl, vl);
258 for (size_t field = 0; field < kNFfields; field++) {
259 for (size_t index = 0; index < kLmul; index++) {
260 for (size_t element = 0; element < kElementsCount; ++element) {
261 ElementType expected_element;
262 if (vstart >= vl) {
263 // When vstart ⩾ vl, there are no body elements, and no elements are updated in
264 // any destinationvector register group, including that no tail elements are
265 // updated with agnostic values.
266 expected_element =
267 SIMD128Register{kUndisturbedResult}.Get<ElementType>(element);
268 } else if (element + index * kElementsCount < std::min(vstart, vl)) {
269 // Elements before vstart are undisturbed if vstart is less than vl.
270 expected_element =
271 SIMD128Register{kUndisturbedResult}.Get<ElementType>(element);
272 } else if (element + index * kElementsCount >= vl) {
273 // Element after vl have to be processed with vta policy.
274 if (vta == 1) {
275 expected_element = ~ElementType{0};
276 } else {
277 expected_element =
278 SIMD128Register{kUndisturbedResult}.Get<ElementType>(element);
279 }
280 } else if (vma &&
281 (~(state_.cpu.v[0]) >> (element + index * kElementsCount)) & 1) {
282 // If element is inactive it's processed with vma policy.
283 if (vma == 1) {
284 expected_element = ~ElementType{0};
285 } else {
286 expected_element =
287 SIMD128Register{kUndisturbedResult}.Get<ElementType>(element);
288 }
289 } else {
290 expected_element =
291 ElementType{expected_results[index + field * kLmul][element]};
292 }
293 EXPECT_EQ(
294 SIMD128Register{state_.cpu.v[8 + index + field * kLmul]}.Get<ElementType>(
295 element),
296 expected_element);
297 }
298 }
299 }
300 for (size_t index = kNFfields * kLmul; index < 8; index++) {
301 EXPECT_EQ(state_.cpu.v[8 + index], kUndisturbedValue);
302 }
303 }
304 }
305 }
306 }
307 }
308
TestVlm(uint32_t insn_bytes,__v16qu expected_results)309 void TestVlm(uint32_t insn_bytes, __v16qu expected_results) {
310 const auto kUndisturbedValue = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
311 // Vlm.v is special form of normal vector load which mostly ignores vtype.
312 // The only bit that it honors is vill: https://github.com/riscv/riscv-v-spec/pull/877
313 // Verify that changes to vtype don't affect the execution (but vstart and vl do).
314 for (uint8_t sew = 0; sew < 4; ++sew) {
315 for (uint8_t vlmul = 0; vlmul < 4; ++vlmul) {
316 const uint8_t kElementsCount = (16 >> sew) << vlmul;
317 for (uint8_t vstart = 0; vstart <= kElementsCount; ++vstart) {
318 for (uint8_t vl = 0; vl <= kElementsCount; ++vl) {
319 const uint8_t kVlmVl = AlignUp<CHAR_BIT>(vl) / CHAR_BIT;
320 for (uint8_t vta = 0; vta < 2; ++vta) {
321 for (uint8_t vma = 0; vma < 2; ++vma) {
322 state_.cpu.vtype = (vma << 7) | (vta << 6) | (sew << 3) | vlmul;
323 state_.cpu.vstart = vstart;
324 state_.cpu.vl = vl;
325 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
326 SetXReg<1>(state_.cpu, ToGuestAddr(&kVectorCalculationsSource));
327 state_.cpu.v[8] = kUndisturbedValue;
328 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
329 EXPECT_EQ(state_.cpu.vstart, 0);
330 EXPECT_EQ(state_.cpu.vl, vl);
331 for (size_t element = 0; element < 16; ++element) {
332 UInt8 expected_element;
333 if (element < vstart || vstart >= kVlmVl) {
334 expected_element = SIMD128Register{kUndisturbedResult}.Get<UInt8>(element);
335 } else if (element >= kVlmVl) {
336 expected_element = ~UInt8{0};
337 } else {
338 expected_element = UInt8{expected_results[element]};
339 }
340 EXPECT_EQ(SIMD128Register{state_.cpu.v[8]}.Get<UInt8>(element), expected_element);
341 }
342 }
343 }
344 }
345 }
346 }
347 }
348 }
349
350 template <typename ElementType, size_t kNFfields, size_t kLmul, size_t kResultSize>
VsxsegXeiXX(uint32_t insn_bytes,const uint64_t (& expected_results)[kResultSize])351 void VsxsegXeiXX(uint32_t insn_bytes, const uint64_t (&expected_results)[kResultSize]) {
352 VsxsegXeiXX<ElementType, UInt8, kNFfields, kLmul>(insn_bytes, expected_results);
353 VsxsegXeiXX<ElementType, UInt8, kNFfields, kLmul>(insn_bytes | 0x8000000, expected_results);
354 VsxsegXeiXX<ElementType, UInt16, kNFfields, kLmul>(insn_bytes | 0x5000, expected_results);
355 VsxsegXeiXX<ElementType, UInt16, kNFfields, kLmul>(insn_bytes | 0x8005000, expected_results);
356 VsxsegXeiXX<ElementType, UInt32, kNFfields, kLmul>(insn_bytes | 0x6000, expected_results);
357 VsxsegXeiXX<ElementType, UInt32, kNFfields, kLmul>(insn_bytes | 0x8006000, expected_results);
358 VsxsegXeiXX<ElementType, UInt64, kNFfields, kLmul>(insn_bytes | 0x7000, expected_results);
359 VsxsegXeiXX<ElementType, UInt64, kNFfields, kLmul>(insn_bytes | 0x8007000, expected_results);
360 }
361
362 template <typename DataElementType,
363 typename IndexElementType,
364 size_t kNFfields,
365 size_t kLmul,
366 size_t kResultSize>
VsxsegXeiXX(uint32_t insn_bytes,const uint64_t (& expected_results)[kResultSize])367 void VsxsegXeiXX(uint32_t insn_bytes, const uint64_t (&expected_results)[kResultSize]) {
368 constexpr size_t kElementsCount = sizeof(SIMD128Register) / sizeof(IndexElementType);
369 constexpr size_t kTotalElements =
370 sizeof(SIMD128Register) / sizeof(DataElementType) * kLmul * kNFfields;
371 // If we need more indexes than may fit into 8 vector registers then such operation is
372 // impossible on RISC-V and we should skip that combination.
373 if constexpr (sizeof(IndexElementType) * kTotalElements <= sizeof(SIMD128Register) * 8) {
374 TestVectorStore<DataElementType, kNFfields, kLmul>(insn_bytes, expected_results, [this] {
375 for (size_t reg_no = 0; reg_no < AlignUp<kElementsCount>(kTotalElements) / kElementsCount;
376 ++reg_no) {
377 SIMD128Register index_register;
378 for (size_t index = 0; index < kElementsCount; ++index) {
379 index_register.Set(IndexElementType{static_cast<typename IndexElementType::BaseType>(
380 kPermutedIndexes[index + reg_no * kElementsCount] *
381 sizeof(DataElementType) * kNFfields)},
382 index);
383 }
384 state_.cpu.v[16 + reg_no] = index_register.Get<__uint128_t>();
385 }
386 });
387 }
388 }
389
390 template <typename ElementType, size_t kNFfields, size_t kLmul, size_t kResultSize>
TestVssegXeXX(uint32_t insn_bytes,const uint64_t (& expected_results)[kResultSize])391 void TestVssegXeXX(uint32_t insn_bytes, const uint64_t (&expected_results)[kResultSize]) {
392 TestVectorStore<ElementType, kNFfields, kLmul>(insn_bytes, expected_results, [] {});
393 }
394
395 template <typename ElementType, size_t kNFfields, size_t kLmul, size_t kResultSize>
TestVsssegXeXX(uint32_t insn_bytes,uint64_t stride,const uint64_t (& expected_results)[kResultSize])396 void TestVsssegXeXX(uint32_t insn_bytes,
397 uint64_t stride,
398 const uint64_t (&expected_results)[kResultSize]) {
399 TestVectorStore<ElementType, kNFfields, kLmul>(
400 insn_bytes, expected_results, [stride, this] { SetXReg<2>(state_.cpu, stride); });
401 }
402
403 template <typename ElementType,
404 size_t kNFfields,
405 size_t kLmul,
406 size_t kResultSize,
407 typename ExtraCPUInitType>
TestVectorStore(uint32_t insn_bytes,const uint64_t (& expected_results)[kResultSize],ExtraCPUInitType ExtraCPUInit)408 void TestVectorStore(uint32_t insn_bytes,
409 const uint64_t (&expected_results)[kResultSize],
410 ExtraCPUInitType ExtraCPUInit) {
411 constexpr size_t kElementsCount = 16 / sizeof(ElementType);
412 const SIMD128Register kUndisturbedValue = SIMD128Register{kUndisturbedResult};
413 state_.cpu.vtype = (BitUtilLog2(sizeof(ElementType)) << 3) | BitUtilLog2(kLmul);
414 state_.cpu.vstart = 0;
415 state_.cpu.vl = kElementsCount * kLmul;
416 // First verify that store works with no inactive elements and no masking.
417 uint32_t insn_bytes_with_vm = insn_bytes | (1 << 25);
418 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes_with_vm);
419 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
420 for (size_t index = 0; index < 8; ++index) {
421 state_.cpu.v[8 + index] =
422 SIMD128Register{kVectorCalculationsSource[index]}.Get<__uint128_t>();
423 }
424 for (uint64_t& element : store_area_) {
425 element = kUndisturbedResult[0];
426 }
427 ExtraCPUInit();
428 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
429 for (size_t index = 0; index < std::size(store_area_); ++index) {
430 if (index >= std::size(expected_results)) {
431 EXPECT_EQ(store_area_[index], static_cast<uint64_t>(kUndisturbedResult[0]));
432 } else {
433 EXPECT_EQ(store_area_[index], expected_results[index]);
434 }
435 }
436 // Most vector instruction apply masks to *target* operands which means we may apply the exact
437 // same, well-tested logic to verify how they work. But store instructions apply masks to *data
438 // source* operand which makes generation of expected target problematic (especially for
439 // complicated store with segments and strides and/or indexes). To sidestep the issue we are
440 // first testing that full version with all elements active works (above) and then reuse it to
441 // verify that `vstart`, `vl` ������ `mask` operands work as expected. This wouldn't work if some
442 // elements are overlapping, but these instructions, while technically permitted, already are
443 // allowed to produce many possible different results, thus we are not testing them.
444 for (uint8_t vstart = 0; vstart <= kElementsCount * kLmul; ++vstart) {
445 for (uint8_t vl = 0; vl <= kElementsCount * kLmul; ++vl) {
446 for (uint8_t vta = 0; vta < 2; ++vta) {
447 // Handle three masking cases:
448 // no masking (vma == 0), agnostic (vma == 1), undisturbed (vma == 2)
449 // Note: vta and vma settings are ignored by store instructions, we are just verifying
450 // this is what actually happens.
451 for (uint8_t vma = 0; vma < 3; ++vma) {
452 // Use instruction in the mode tested above to generate expected results.
453 state_.cpu.vtype = (BitUtilLog2(sizeof(ElementType)) << 3) | BitUtilLog2(kLmul);
454 state_.cpu.vstart = 0;
455 state_.cpu.vl = kElementsCount * kLmul;
456 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes_with_vm);
457 decltype(store_area_) expected_store_area;
458 SetXReg<1>(state_.cpu, ToGuestAddr(&expected_store_area));
459 for (size_t index = 0; index < kLmul; ++index) {
460 for (size_t field = 0; field < kNFfields; ++field) {
461 SIMD128Register register_value =
462 SIMD128Register{kVectorCalculationsSource[index + field * kLmul]};
463 if (vma) {
464 auto ApplyMask = [®ister_value, &kUndisturbedValue, index](auto mask) {
465 register_value =
466 (register_value & mask[index]) | (kUndisturbedValue & ~mask[index]);
467 };
468 if constexpr (sizeof(ElementType) == sizeof(Int8)) {
469 ApplyMask(kMaskInt8);
470 } else if constexpr (sizeof(ElementType) == sizeof(Int16)) {
471 ApplyMask(kMaskInt16);
472 } else if constexpr (sizeof(ElementType) == sizeof(Int32)) {
473 ApplyMask(kMaskInt32);
474 } else if constexpr (sizeof(ElementType) == sizeof(Int64)) {
475 ApplyMask(kMaskInt64);
476 } else {
477 static_assert(kDependentTypeFalse<ElementType>);
478 }
479 }
480 if (vstart > kElementsCount * index) {
481 for (size_t prefix_id = 0;
482 prefix_id < std::min(kElementsCount, vstart - kElementsCount * index);
483 ++prefix_id) {
484 register_value.Set(kUndisturbedValue.Get<ElementType>(0), prefix_id);
485 }
486 }
487 if (vl <= kElementsCount * index) {
488 register_value = kUndisturbedValue.Get<__uint128_t>();
489 } else if (vl < kElementsCount * (index + 1)) {
490 for (size_t suffix_id = vl - kElementsCount * index; suffix_id < kElementsCount;
491 ++suffix_id) {
492 register_value.Set(kUndisturbedValue.Get<ElementType>(0), suffix_id);
493 }
494 }
495 state_.cpu.v[8 + index + field * kLmul] = register_value.Get<__uint128_t>();
496 }
497 }
498 for (uint64_t& element : expected_store_area) {
499 element = kUndisturbedResult[0];
500 }
501 ExtraCPUInit();
502 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
503 // Now execute instruction with mode that we want to actually test.
504 state_.cpu.vtype = (vma & 1) << 7 | (vta << 6) |
505 (BitUtilLog2(sizeof(ElementType)) << 3) | BitUtilLog2(kLmul);
506 state_.cpu.vstart = vstart;
507 state_.cpu.vl = vl;
508 uint32_t insn_bytes_with_vm = insn_bytes;
509 // If masking is supposed to be disabled then we need to set vm bit (#25).
510 if (!vma) {
511 insn_bytes_with_vm |= (1 << 25);
512 }
513 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes_with_vm);
514 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
515 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
516 for (size_t index = 0; index < 8; ++index) {
517 state_.cpu.v[8 + index] =
518 SIMD128Register{kVectorCalculationsSource[index]}.Get<__uint128_t>();
519 }
520 for (uint64_t& element : store_area_) {
521 element = kUndisturbedResult[0];
522 }
523 ExtraCPUInit();
524 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
525 for (size_t index = 0; index < std::size(store_area_); ++index) {
526 EXPECT_EQ(store_area_[index], expected_store_area[index]);
527 }
528 }
529 }
530 }
531 }
532 }
533
TestVsm(uint32_t insn_bytes,__v16qu expected_results)534 void TestVsm(uint32_t insn_bytes, __v16qu expected_results) {
535 const auto kUndisturbedValue = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
536 // Vlm.v is special form of normal vector load which mostly ignores vtype.
537 // The only bit that it honors is vill: https://github.com/riscv/riscv-v-spec/pull/877
538 // Verify that changes to vtype don't affect the execution (but vstart and vl do).
539 for (uint8_t sew = 0; sew < 4; ++sew) {
540 for (uint8_t vlmul = 0; vlmul < 4; ++vlmul) {
541 const uint8_t kElementsCount = (16 >> sew) << vlmul;
542 for (uint8_t vstart = 0; vstart <= kElementsCount; ++vstart) {
543 for (uint8_t vl = 0; vl <= kElementsCount; ++vl) {
544 const uint8_t kVlmVl = AlignUp<CHAR_BIT>(vl) / CHAR_BIT;
545 for (uint8_t vta = 0; vta < 2; ++vta) {
546 for (uint8_t vma = 0; vma < 2; ++vma) {
547 state_.cpu.vtype = (vma << 7) | (vta << 6) | (sew << 3) | vlmul;
548 state_.cpu.vstart = vstart;
549 state_.cpu.vl = vl;
550 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
551 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
552 store_area_[0] = kUndisturbedResult[0];
553 store_area_[1] = kUndisturbedResult[1];
554 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
555 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
556 EXPECT_EQ(state_.cpu.vstart, 0);
557 EXPECT_EQ(state_.cpu.vl, vl);
558 SIMD128Register memory_result =
559 SIMD128Register{__v2du{store_area_[0], store_area_[1]}};
560 for (size_t element = 0; element < 16; ++element) {
561 UInt8 expected_element;
562 if (element < vstart || element >= kVlmVl) {
563 expected_element = SIMD128Register{kUndisturbedResult}.Get<UInt8>(element);
564 } else {
565 expected_element = UInt8{expected_results[element]};
566 }
567 EXPECT_EQ(memory_result.Get<UInt8>(element), expected_element);
568 }
569 }
570 }
571 }
572 }
573 }
574 }
575 }
576
577 // Vector instructions.
TestVleXXff(uint32_t insn_bytes,uint8_t loadable_bytes,uint8_t vsew,uint8_t expected_vl,bool fail_on_first=false)578 void TestVleXXff(uint32_t insn_bytes,
579 uint8_t loadable_bytes,
580 uint8_t vsew,
581 uint8_t expected_vl,
582 bool fail_on_first = false) {
583 ScopedFaultySigaction scoped_sa;
584 sighandler_called = false;
585 char* buffer;
586 const size_t kPageSize = sysconf(_SC_PAGE_SIZE);
587 buffer = (char*)memalign(kPageSize, 2 * kPageSize);
588 mprotect(buffer, kPageSize * 2, PROT_WRITE);
589 char* p = buffer + kPageSize - loadable_bytes;
590 std::memcpy(p, &kVectorCalculationsSource[0], 128);
591 mprotect(buffer + kPageSize, kPageSize, PROT_NONE);
592
593 auto [vlmax, vtype] = intrinsics::Vsetvl(~0ULL, (vsew << 3) | 3);
594 state_.cpu.vstart = 0;
595 state_.cpu.vl = vlmax;
596 state_.cpu.vtype = vtype;
597 insn_bytes = insn_bytes | (1 << 25);
598 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
599 SetXReg<1>(state_.cpu, ToGuestAddr(p));
600
601 if (fail_on_first) {
602 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr));
603 } else {
604 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
605 }
606 if (loadable_bytes < 128) {
607 EXPECT_TRUE(sighandler_called);
608 } else {
609 EXPECT_FALSE(sighandler_called);
610 }
611 EXPECT_EQ(state_.cpu.vl, expected_vl);
612 }
613
614 // Vector instructions.
TestVleXX(uint32_t insn_bytes,const __v16qu (& expected_result_int8)[8],const __v8hu (& expected_result_int16)[8],const __v4su (& expected_result_int32)[8],const __v2du (& expected_result_int64)[8],uint8_t veew,const __v2du (& source)[16])615 void TestVleXX(uint32_t insn_bytes,
616 const __v16qu (&expected_result_int8)[8],
617 const __v8hu (&expected_result_int16)[8],
618 const __v4su (&expected_result_int32)[8],
619 const __v2du (&expected_result_int64)[8],
620 uint8_t veew,
621 const __v2du (&source)[16]) {
622 auto Verify = [this, &source](uint32_t insn_bytes,
623 uint8_t vsew,
624 uint8_t veew,
625 uint8_t vlmul_max,
626 const auto& expected_result,
627 auto mask) {
628 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
629 for (uint8_t vlmul = 0; vlmul < vlmul_max; ++vlmul) {
630 int vemul = SignExtend<3>(vlmul);
631 vemul += vsew; // Multiply by SEW.
632 vemul -= veew; // Divide by EEW.
633 if (vemul < -3 || vemul > 3) {
634 // Incompatible vlmul
635 continue;
636 }
637
638 for (uint8_t vta = 0; vta < 2; ++vta) {
639 for (uint8_t vma = 0; vma < 2; ++vma) {
640 auto [vlmax, vtype] =
641 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
642 if (vlmax == 0) {
643 continue;
644 }
645 // Test vstart/vl changes with only with vemul == 2 (4 registers)
646 if (vemul == 2) {
647 state_.cpu.vstart = vlmax / 8;
648 state_.cpu.vl = (vlmax * 5) / 8;
649 } else {
650 state_.cpu.vstart = 0;
651 state_.cpu.vl = vlmax;
652 }
653 state_.cpu.vtype = vtype;
654
655 // Set expected_result vector registers into 0b01010101… pattern.
656 for (size_t index = 0; index < 8; ++index) {
657 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
658 }
659 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
660 SetXReg<1>(state_.cpu, ToGuestAddr(&source));
661 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
662 // Values for inactive elements (i.e. corresponding mask bit is 0).
663 const size_t n = std::size(source);
664 __m128i expected_inactive[n];
665 std::fill_n(expected_inactive, n, (vma ? kAgnosticResult : kUndisturbedResult));
666 if (vemul >= 0) {
667 for (size_t index = 0; index < 1 << vemul; ++index) {
668 if (index == 0 && vemul == 2) {
669 EXPECT_EQ(state_.cpu.v[8 + index],
670 SIMD128Register{
671 (kUndisturbedResult & kFractionMaskInt8[3]) |
672 (expected_result[index] & mask[index] & ~kFractionMaskInt8[3]) |
673 (expected_inactive[index] & ~mask[index] & ~kFractionMaskInt8[3])}
674 .Get<__uint128_t>());
675 } else if (index == 2 && vemul == 2) {
676 EXPECT_EQ(
677 state_.cpu.v[8 + index],
678 SIMD128Register{
679 (expected_result[index] & mask[index] & kFractionMaskInt8[3]) |
680 (expected_inactive[index] & ~mask[index] & kFractionMaskInt8[3]) |
681 ((vta ? kAgnosticResult : kUndisturbedResult) & ~kFractionMaskInt8[3])}
682 .Get<__uint128_t>());
683 } else if (index == 3 && vemul == 2 && vta) {
684 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
685 } else if (index == 3 && vemul == 2) {
686 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kUndisturbedResult});
687 } else {
688 EXPECT_EQ(state_.cpu.v[8 + index],
689 SIMD128Register{(expected_result[index] & mask[index]) |
690 (expected_inactive[index] & ~mask[index])}
691 .Get<__uint128_t>());
692 }
693 }
694
695 } else {
696 EXPECT_EQ(state_.cpu.v[8],
697 SIMD128Register{
698 (expected_result[0] & mask[0] & kFractionMaskInt8[(vemul + 4)]) |
699 (expected_inactive[0] & ~mask[0] & kFractionMaskInt8[(vemul + 4)]) |
700 ((vta ? kAgnosticResult : kUndisturbedResult) &
701 ~kFractionMaskInt8[(vemul + 4)])}
702 .Get<__uint128_t>());
703 }
704 }
705 }
706 }
707 };
708 switch (veew) {
709 case 0:
710 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int8, kNoMask);
711 Verify(insn_bytes, veew, veew, 8, expected_result_int8, kMaskInt8);
712 break;
713 case 1:
714 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int16, kNoMask);
715 Verify(insn_bytes, veew, veew, 8, expected_result_int16, kMaskInt16);
716 break;
717 case 2:
718 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int32, kNoMask);
719 Verify(insn_bytes, veew, veew, 8, expected_result_int32, kMaskInt32);
720 break;
721 case 3:
722 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int64, kNoMask);
723 Verify(insn_bytes, veew, veew, 8, expected_result_int64, kMaskInt64);
724 break;
725 default:
726 break;
727 }
728 }
729
730 // Vector instructions.
TestVseXX(uint32_t insn_bytes,const __v16qu (& expected_result_int8)[8],const __v8hu (& expected_result_int16)[8],const __v4su (& expected_result_int32)[8],const __v2du (& expected_result_int64)[8],uint8_t veew,const __v2du (& source)[16])731 void TestVseXX(uint32_t insn_bytes,
732 const __v16qu (&expected_result_int8)[8],
733 const __v8hu (&expected_result_int16)[8],
734 const __v4su (&expected_result_int32)[8],
735 const __v2du (&expected_result_int64)[8],
736 uint8_t veew,
737 const __v2du (&source)[16]) {
738 auto Verify = [this, &source](uint32_t insn_bytes,
739 uint8_t vsew,
740 uint8_t veew,
741 uint8_t vlmul_max,
742 const auto& expected_result,
743 auto mask) {
744 SIMD128Register expected_result_in_register;
745 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
746 for (uint8_t vlmul = 0; vlmul < vlmul_max; ++vlmul) {
747 int vemul = SignExtend<3>(vlmul);
748 vemul += vsew; // Multiply by SEW.
749 vemul -= veew; // Divide by EEW.
750 if (vemul < -3 || vemul > 3) {
751 // Incompatible vlmul
752 continue;
753 }
754
755 for (uint8_t vma = 0; vma < 2; ++vma) {
756 auto [vlmax, vtype] = intrinsics::Vsetvl(~0ULL, (vma << 7) | (vsew << 3) | vlmul);
757 if (vlmax == 0) {
758 continue;
759 }
760 // Test vstart/vl changes with only with vemul == 2 (4 registers)
761 if (vemul == 2) {
762 state_.cpu.vstart = vlmax / 8;
763 state_.cpu.vl = (vlmax * 5) / 8;
764 } else {
765 state_.cpu.vstart = 0;
766 state_.cpu.vl = vlmax;
767 }
768 state_.cpu.vtype = vtype;
769
770 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
771 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
772 for (size_t index = 0; index < 8; index++) {
773 state_.cpu.v[8 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
774 store_area_[index * 2] = kUndisturbedResult[0];
775 store_area_[index * 2 + 1] = kUndisturbedResult[1];
776 }
777 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
778 // Values for inactive elements (i.e. corresponding mask bit is 0).
779 const size_t n = std::size(source);
780 __m128i expected_inactive[n];
781 std::fill_n(expected_inactive, n, kUndisturbedResult);
782 if (vemul >= 0) {
783 for (size_t index = 0; index < 1 << vemul; ++index) {
784 if (index == 0 && vemul == 2) {
785 expected_result_in_register = SIMD128Register{
786 (kUndisturbedResult & kFractionMaskInt8[3]) |
787 (expected_result[index] & mask[index] & ~kFractionMaskInt8[3]) |
788 (expected_inactive[index] & ~mask[index] & ~kFractionMaskInt8[3])};
789 } else if (index == 2 && vemul == 2) {
790 expected_result_in_register = SIMD128Register{
791 (expected_result[index] & mask[index] & kFractionMaskInt8[3]) |
792 (expected_inactive[index] & ~mask[index] & kFractionMaskInt8[3]) |
793 ((kUndisturbedResult) & ~kFractionMaskInt8[3])};
794 } else if (index == 3 && vemul == 2) {
795 expected_result_in_register = SIMD128Register{kUndisturbedResult};
796 } else {
797 expected_result_in_register =
798 SIMD128Register{(expected_result[index] & mask[index]) |
799 (expected_inactive[index] & ~mask[index])};
800 }
801
802 EXPECT_EQ(store_area_[index * 2], expected_result_in_register.Get<uint64_t>(0));
803 EXPECT_EQ(store_area_[index * 2 + 1], expected_result_in_register.Get<uint64_t>(1));
804 }
805
806 } else {
807 expected_result_in_register =
808 SIMD128Register{(expected_result[0] & mask[0] & kFractionMaskInt8[(vemul + 4)]) |
809 (expected_inactive[0] & ~mask[0] & kFractionMaskInt8[(vemul + 4)]) |
810 ((kUndisturbedResult) & ~kFractionMaskInt8[(vemul + 4)])};
811 EXPECT_EQ(store_area_[0], expected_result_in_register.Get<uint64_t>(0));
812 EXPECT_EQ(store_area_[1], expected_result_in_register.Get<uint64_t>(1));
813 }
814 }
815 }
816 };
817 switch (veew) {
818 case 0:
819 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int8, kNoMask);
820 Verify(insn_bytes, veew, veew, 8, expected_result_int8, kMaskInt8);
821 break;
822 case 1:
823 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int16, kNoMask);
824 Verify(insn_bytes, veew, veew, 8, expected_result_int16, kMaskInt16);
825 break;
826 case 2:
827 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int32, kNoMask);
828 Verify(insn_bytes, veew, veew, 8, expected_result_int32, kMaskInt32);
829 break;
830 case 3:
831 Verify(insn_bytes | (1 << 25), veew, veew, 8, expected_result_int64, kNoMask);
832 Verify(insn_bytes, veew, veew, 8, expected_result_int64, kMaskInt64);
833 break;
834 default:
835 break;
836 }
837 }
838
839 template <int kNFfields>
TestVmvXr(uint32_t insn_bytes)840 void TestVmvXr(uint32_t insn_bytes) {
841 TestVmvXr<Int8, kNFfields>(insn_bytes);
842 TestVmvXr<Int16, kNFfields>(insn_bytes);
843 TestVmvXr<Int32, kNFfields>(insn_bytes);
844 TestVmvXr<Int64, kNFfields>(insn_bytes);
845 }
846
847 template <typename ElementType, int kNFfields>
TestVmvXr(uint32_t insn_bytes)848 void TestVmvXr(uint32_t insn_bytes) {
849 // Note that VmvXr actually DOES depend on vtype, contrary to what RISC-V V 1.0 manual says:
850 // https://github.com/riscv/riscv-v-spec/pull/872
851 state_.cpu.vtype = BitUtilLog2(sizeof(ElementType)) << 3;
852 state_.cpu.vl = 0;
853 constexpr int kElementsCount = static_cast<int>(sizeof(SIMD128Register) / sizeof(ElementType));
854 for (int vstart = 0; vstart <= kElementsCount * kNFfields; ++vstart) {
855 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
856 state_.cpu.vstart = vstart;
857 for (size_t index = 0; index < 16; ++index) {
858 state_.cpu.v[8 + index] =
859 SIMD128Register{kVectorComparisonSource[index]}.Get<__uint128_t>();
860 }
861 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
862 for (int index = 0; index < 8; ++index) {
863 SIMD128Register expected_state{kVectorComparisonSource[index]};
864 SIMD128Register source_value{kVectorComparisonSource[index + 8]};
865 if ((vstart < kElementsCount * kNFfields) && index < kNFfields) {
866 // The usual property that no elements are written if vstart >= vl does not apply to these
867 // instructions. Instead, no elements are written if vstart >= evl.
868 for (int element_index = 0; element_index < kElementsCount; ++element_index) {
869 if (element_index + index * kElementsCount >= vstart) {
870 expected_state.Set(source_value.Get<ElementType>(element_index), element_index);
871 }
872 }
873 }
874 EXPECT_EQ(state_.cpu.v[8 + index], expected_state.Get<__uint128_t>());
875 }
876 EXPECT_EQ(state_.cpu.vstart, 0);
877 }
878 }
879
880 template <typename ElementType>
TestVfmvfs(uint32_t insn_bytes,uint64_t expected_result)881 void TestVfmvfs(uint32_t insn_bytes, uint64_t expected_result) {
882 state_.cpu.vtype = BitUtilLog2(sizeof(ElementType)) << 3;
883 state_.cpu.vstart = 0;
884 state_.cpu.vl = 0;
885 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
886 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
887 SetFReg<1>(state_.cpu, 0x5555'5555'5555'5555);
888 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
889 EXPECT_EQ(GetFReg<1>(state_.cpu), expected_result);
890 }
891
892 template <typename ElementType>
TestVfmvsf(uint32_t insn_bytes,uint64_t boxed_value,ElementType unboxed_value)893 void TestVfmvsf(uint32_t insn_bytes, uint64_t boxed_value, ElementType unboxed_value) {
894 for (uint8_t vstart = 0; vstart < 2; ++vstart) {
895 for (uint8_t vl = 0; vl < 2; ++vl) {
896 for (uint8_t vta = 0; vta < 2; ++vta) {
897 state_.cpu.vtype = (vta << 6) | (BitUtilLog2(sizeof(ElementType)) << 3);
898 state_.cpu.vstart = vstart;
899 state_.cpu.vl = vl;
900 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
901 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
902 SetFReg<1>(state_.cpu, boxed_value);
903 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
904 if (vstart == 0 && vl != 0) {
905 SIMD128Register expected_result =
906 vta ? ~SIMD128Register{} : SIMD128Register{kVectorCalculationsSource[0]};
907 expected_result.Set<ElementType>(unboxed_value, 0);
908 EXPECT_EQ(state_.cpu.v[8], expected_result);
909 } else {
910 EXPECT_EQ(state_.cpu.v[8],
911 SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>());
912 }
913 }
914 }
915 }
916 }
917
918 template <typename ElementType>
TestVmvsx(uint32_t insn_bytes)919 void TestVmvsx(uint32_t insn_bytes) {
920 for (uint8_t vstart = 0; vstart < 2; ++vstart) {
921 for (uint8_t vl = 0; vl < 2; ++vl) {
922 for (uint8_t vta = 0; vta < 2; ++vta) {
923 state_.cpu.vtype = (vta << 6) | (BitUtilLog2(sizeof(ElementType)) << 3);
924 state_.cpu.vstart = vstart;
925 state_.cpu.vl = vl;
926 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
927 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
928 SetXReg<1>(state_.cpu, 0x5555'5555'5555'5555);
929 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
930 if (vstart == 0 && vl != 0) {
931 SIMD128Register expected_result =
932 vta ? ~SIMD128Register{} : SIMD128Register{kVectorCalculationsSource[0]};
933 expected_result.Set<ElementType>(MaybeTruncateTo<ElementType>(0x5555'5555'5555'5555),
934 0);
935 EXPECT_EQ(state_.cpu.v[8], expected_result);
936 } else {
937 EXPECT_EQ(state_.cpu.v[8],
938 SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>());
939 }
940 }
941 }
942 }
943 }
944
945 template <typename ElementType>
TestVmvxs(uint32_t insn_bytes,uint64_t expected_result)946 void TestVmvxs(uint32_t insn_bytes, uint64_t expected_result) {
947 state_.cpu.vtype = BitUtilLog2(sizeof(ElementType)) << 3;
948 state_.cpu.vstart = 0;
949 state_.cpu.vl = 0;
950 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
951 state_.cpu.v[8] = SIMD128Register{kVectorCalculationsSource[0]}.Get<__uint128_t>();
952 SetXReg<1>(state_.cpu, 0x5555'5555'5555'5555);
953 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
954 EXPECT_EQ(GetXReg<1>(state_.cpu), expected_result);
955 }
956
957 template <size_t kNFfields>
TestVsX(uint32_t insn_bytes)958 void TestVsX(uint32_t insn_bytes) {
959 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
960 SetXReg<1>(state_.cpu, ToGuestAddr(&store_area_));
961 for (size_t index = 0; index < 8; index++) {
962 state_.cpu.v[8 + index] = SIMD128Register{kVectorComparisonSource[index]}.Get<__uint128_t>();
963 store_area_[index * 2] = kUndisturbedResult[0];
964 store_area_[index * 2 + 1] = kUndisturbedResult[1];
965 }
966 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
967 for (size_t index = 0; index < 8; index++) {
968 EXPECT_EQ(
969 store_area_[index * 2],
970 (index >= kNFfields ? kUndisturbedResult[0]
971 : SIMD128Register{kVectorComparisonSource[index]}.Get<uint64_t>(0)));
972 EXPECT_EQ(
973 store_area_[index * 2 + 1],
974 (index >= kNFfields ? kUndisturbedResult[1]
975 : SIMD128Register{kVectorComparisonSource[index]}.Get<uint64_t>(1)));
976 }
977 }
978
TestVectorRegisterGather(uint32_t insn_bytes,const __v16qu (& expected_result_int8)[8],const __v8hu (& expected_result_int16)[8],const __v4su (& expected_result_int32)[8],const __v2du (& expected_result_int64)[8],const uint8_t vlmul,const __v2du (& source)[16])979 void TestVectorRegisterGather(uint32_t insn_bytes,
980 const __v16qu (&expected_result_int8)[8],
981 const __v8hu (&expected_result_int16)[8],
982 const __v4su (&expected_result_int32)[8],
983 const __v2du (&expected_result_int64)[8],
984 const uint8_t vlmul,
985 const __v2du (&source)[16]) {
986 auto Verify = [this, &source, &vlmul](
987 uint32_t insn_bytes, uint8_t vsew, const auto& expected_result, auto mask) {
988 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
989 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
990 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
991 for (size_t index = 0; index < 8; ++index) {
992 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
993 }
994
995 for (uint8_t vta = 0; vta < 2; ++vta) {
996 for (uint8_t vma = 0; vma < 2; ++vma) {
997 auto [vlmax, vtype] =
998 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
999 // Incompatible vsew and vlmax. Skip it.
1000 if (vlmax == 0) {
1001 continue;
1002 }
1003
1004 // Make sure indexes in src2 fall within vlmax.
1005 uint64_t src2_mask{0};
1006 const size_t kElementSize = 8 << vsew;
1007 const uint64_t kIndexMask = (1 << BitUtilLog2(vlmax)) - 1;
1008 for (uint8_t index = 0; index < 64 / kElementSize; index++) {
1009 src2_mask |= kIndexMask << (kElementSize * index);
1010 }
1011 for (size_t index = 0; index < 8; ++index) {
1012 __v2du masked_register = {source[8 + index][0] & src2_mask, source[8 + index][1]};
1013 state_.cpu.v[24 + index] = SIMD128Register{masked_register}.Get<__uint128_t>();
1014 }
1015 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaaULL & kIndexMask);
1016
1017 // To make tests quick enough we don't test vstart and vl change with small register
1018 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of
1019 // first
1020 // register and half of last register.
1021 if (vlmul == 2) {
1022 state_.cpu.vstart = vlmax / 8;
1023 state_.cpu.vl = (vlmax * 5) / 8;
1024 } else {
1025 state_.cpu.vstart = 0;
1026 state_.cpu.vl = vlmax;
1027 }
1028 state_.cpu.vtype = vtype;
1029
1030 // Set expected_result vector registers into 0b01010101… pattern.
1031 for (size_t index = 0; index < 8; ++index) {
1032 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1033 }
1034
1035 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1036 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1037
1038 // Values for inactive elements (i.e. corresponding mask bit is 0).
1039 const size_t n = std::size(source) * 2;
1040 __m128i expected_inactive[n];
1041 // For most instructions, follow basic inactive processing rules based on vma flag.
1042 std::fill_n(expected_inactive, n, (vma ? kAgnosticResult : kUndisturbedResult));
1043
1044 if (vlmul < 4) {
1045 for (size_t index = 0; index < 1 << vlmul; ++index) {
1046 if (index == 0 && vlmul == 2) {
1047 EXPECT_EQ(state_.cpu.v[8 + index],
1048 SIMD128Register{
1049 (kUndisturbedResult & kFractionMaskInt8[3]) |
1050 (expected_result[index] & mask[index] & ~kFractionMaskInt8[3]) |
1051 (expected_inactive[index] & ~mask[index] & ~kFractionMaskInt8[3])}
1052 .Get<__uint128_t>());
1053 } else if (index == 2 && vlmul == 2) {
1054 EXPECT_EQ(
1055 state_.cpu.v[8 + index],
1056 SIMD128Register{
1057 (expected_result[index] & mask[index] & kFractionMaskInt8[3]) |
1058 (expected_inactive[index] & ~mask[index] & kFractionMaskInt8[3]) |
1059 ((vta ? kAgnosticResult : kUndisturbedResult) & ~kFractionMaskInt8[3])}
1060 .Get<__uint128_t>());
1061 } else if (index == 3 && vlmul == 2 && vta) {
1062 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
1063 } else if (index == 3 && vlmul == 2) {
1064 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kUndisturbedResult});
1065 } else {
1066 EXPECT_EQ(state_.cpu.v[8 + index],
1067 SIMD128Register{(expected_result[index] & mask[index]) |
1068 (expected_inactive[index] & ~mask[index])}
1069 .Get<__uint128_t>());
1070 }
1071 }
1072 } else {
1073 EXPECT_EQ(
1074 state_.cpu.v[8],
1075 SIMD128Register{
1076 (expected_result[0] & mask[0] & kFractionMaskInt8[vlmul - 4]) |
1077 (expected_inactive[0] & ~mask[0] & kFractionMaskInt8[vlmul - 4]) |
1078 ((vta ? kAgnosticResult : kUndisturbedResult) & ~kFractionMaskInt8[vlmul - 4])}
1079 .Get<__uint128_t>());
1080 }
1081
1082 if (vlmul == 2) {
1083 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1084 EXPECT_EQ(state_.cpu.vstart, 0);
1085 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1086 }
1087 }
1088 }
1089 };
1090 Verify(insn_bytes, 0, expected_result_int8, kMaskInt8);
1091 Verify(insn_bytes | (1 << 25), 0, expected_result_int8, kNoMask);
1092 Verify(insn_bytes, 1, expected_result_int16, kMaskInt16);
1093 Verify(insn_bytes | (1 << 25), 1, expected_result_int16, kNoMask);
1094 Verify(insn_bytes, 2, expected_result_int32, kMaskInt32);
1095 Verify(insn_bytes | (1 << 25), 2, expected_result_int32, kNoMask);
1096 Verify(insn_bytes, 3, expected_result_int64, kMaskInt64);
1097 Verify(insn_bytes | (1 << 25), 3, expected_result_int64, kNoMask);
1098 }
1099
TestVectorFloatInstruction(uint32_t insn_bytes,const uint32_t (& expected_result_int32)[8][4],const uint64_t (& expected_result_int64)[8][2],const __v2du (& source)[16])1100 void TestVectorFloatInstruction(uint32_t insn_bytes,
1101 const uint32_t (&expected_result_int32)[8][4],
1102 const uint64_t (&expected_result_int64)[8][2],
1103 const __v2du (&source)[16]) {
1104 TestVectorInstruction<TestVectorInstructionKind::kFloat, TestVectorInstructionMode::kDefault>(
1105 insn_bytes, source, expected_result_int32, expected_result_int64);
1106 }
1107
TestVectorInstruction(uint32_t insn_bytes,const uint8_t (& expected_result_int8)[8][16],const uint16_t (& expected_result_int16)[8][8],const uint32_t (& expected_result_int32)[8][4],const uint64_t (& expected_result_int64)[8][2],const __v2du (& source)[16])1108 void TestVectorInstruction(uint32_t insn_bytes,
1109 const uint8_t (&expected_result_int8)[8][16],
1110 const uint16_t (&expected_result_int16)[8][8],
1111 const uint32_t (&expected_result_int32)[8][4],
1112 const uint64_t (&expected_result_int64)[8][2],
1113 const __v2du (&source)[16]) {
1114 TestVectorInstruction<TestVectorInstructionKind::kInteger, TestVectorInstructionMode::kDefault>(
1115 insn_bytes,
1116 source,
1117 expected_result_int8,
1118 expected_result_int16,
1119 expected_result_int32,
1120 expected_result_int64);
1121 }
1122
TestVectorMergeFloatInstruction(uint32_t insn_bytes,const uint32_t (& expected_result_int32)[8][4],const uint64_t (& expected_result_int64)[8][2],const __v2du (& source)[16])1123 void TestVectorMergeFloatInstruction(uint32_t insn_bytes,
1124 const uint32_t (&expected_result_int32)[8][4],
1125 const uint64_t (&expected_result_int64)[8][2],
1126 const __v2du (&source)[16]) {
1127 TestVectorInstruction<TestVectorInstructionKind::kFloat, TestVectorInstructionMode::kVMerge>(
1128 insn_bytes, source, expected_result_int32, expected_result_int64);
1129 }
1130
TestVectorMergeInstruction(uint32_t insn_bytes,const uint8_t (& expected_result_int8)[8][16],const uint16_t (& expected_result_int16)[8][8],const uint32_t (& expected_result_int32)[8][4],const uint64_t (& expected_result_int64)[8][2],const __v2du (& source)[16])1131 void TestVectorMergeInstruction(uint32_t insn_bytes,
1132 const uint8_t (&expected_result_int8)[8][16],
1133 const uint16_t (&expected_result_int16)[8][8],
1134 const uint32_t (&expected_result_int32)[8][4],
1135 const uint64_t (&expected_result_int64)[8][2],
1136 const __v2du (&source)[16]) {
1137 TestVectorInstruction<TestVectorInstructionKind::kInteger, TestVectorInstructionMode::kVMerge>(
1138 insn_bytes,
1139 source,
1140 expected_result_int8,
1141 expected_result_int16,
1142 expected_result_int32,
1143 expected_result_int64);
1144 }
1145
TestWideningVectorFloatInstruction(uint32_t insn_bytes,const uint64_t (& expected_result_int64)[8][2],const __v2du (& source)[16],__m128i dst_result=kUndisturbedResult)1146 void TestWideningVectorFloatInstruction(uint32_t insn_bytes,
1147 const uint64_t (&expected_result_int64)[8][2],
1148 const __v2du (&source)[16],
1149 __m128i dst_result = kUndisturbedResult) {
1150 TestVectorInstructionInternal<TestVectorInstructionKind::kFloat,
1151 TestVectorInstructionMode::kWidening>(
1152 insn_bytes, dst_result, source, expected_result_int64);
1153 }
1154
TestWideningVectorFloatInstruction(uint32_t insn_bytes,const uint32_t (& expected_result_int32)[8][4],const uint64_t (& expected_result_int64)[8][2],const __v2du (& source)[16])1155 void TestWideningVectorFloatInstruction(uint32_t insn_bytes,
1156 const uint32_t (&expected_result_int32)[8][4],
1157 const uint64_t (&expected_result_int64)[8][2],
1158 const __v2du (&source)[16]) {
1159 TestVectorInstruction<TestVectorInstructionKind::kFloat, TestVectorInstructionMode::kWidening>(
1160 insn_bytes, source, expected_result_int32, expected_result_int64);
1161 }
1162
1163 enum class TestVectorInstructionKind { kInteger, kFloat };
1164 enum class TestVectorInstructionMode { kDefault, kWidening, kNarrowing, kVMerge };
1165
1166 template <TestVectorInstructionKind kTestVectorInstructionKind,
1167 TestVectorInstructionMode kTestVectorInstructionMode,
1168 typename... ElementType,
1169 size_t... kResultsCount,
1170 size_t... kElementCount>
TestVectorInstruction(uint32_t insn_bytes,const __v2du (& source)[16],const ElementType (&...expected_result)[kResultsCount][kElementCount])1171 void TestVectorInstruction(
1172 uint32_t insn_bytes,
1173 const __v2du (&source)[16],
1174 const ElementType (&... expected_result)[kResultsCount][kElementCount]) {
1175 TestVectorInstructionInternal<kTestVectorInstructionKind, kTestVectorInstructionMode>(
1176 insn_bytes, kUndisturbedResult, source, expected_result...);
1177 }
1178
1179 template <TestVectorInstructionKind kTestVectorInstructionKind,
1180 TestVectorInstructionMode kTestVectorInstructionMode,
1181 typename... ElementType,
1182 size_t... kResultsCount,
1183 size_t... kElementCount>
TestVectorInstructionInternal(uint32_t insn_bytes,__m128i dst_result,const __v2du (& source)[16],const ElementType (&...expected_result)[kResultsCount][kElementCount])1184 void TestVectorInstructionInternal(
1185 uint32_t insn_bytes,
1186 __m128i dst_result,
1187 const __v2du (&source)[16],
1188 const ElementType (&... expected_result)[kResultsCount][kElementCount]) {
1189 auto Verify = [this, &source, dst_result](uint32_t insn_bytes,
1190 uint8_t vsew,
1191 uint8_t vlmul_max,
1192 const auto& expected_result,
1193 auto mask) {
1194 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
1195 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
1196 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1197 for (size_t index = 0; index < std::size(source); ++index) {
1198 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
1199 }
1200 if (kTestVectorInstructionKind == TestVectorInstructionKind::kInteger) {
1201 // Set x1 for vx instructions.
1202 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaa);
1203 } else {
1204 // We only support Float32/Float64 for float instructions, but there are conversion
1205 // instructions that work with double width floats.
1206 // These instructions never use float registers though and thus we don't need to store
1207 // anything into f1 register, if they are used.
1208 // For Float32/Float64 case we load 5.625 of the appropriate type into f1.
1209 ASSERT_LE(vsew, 3);
1210 if (vsew == 2) {
1211 SetFReg<1>(state_.cpu, 0xffff'ffff'40b4'0000); // float 5.625
1212 } else if (vsew == 3) {
1213 SetFReg<1>(state_.cpu, 0x4016'8000'0000'0000); // double 5.625
1214 }
1215 }
1216 for (uint8_t vlmul = 0; vlmul < vlmul_max; ++vlmul) {
1217 if constexpr (kTestVectorInstructionMode == TestVectorInstructionMode::kNarrowing ||
1218 kTestVectorInstructionMode == TestVectorInstructionMode::kWidening) {
1219 // Incompatible vlmul for narrowing.
1220 if (vlmul == 3) {
1221 continue;
1222 }
1223 }
1224 for (uint8_t vta = 0; vta < 2; ++vta) {
1225 for (uint8_t vma = 0; vma < 2; ++vma) {
1226 auto [vlmax, vtype] =
1227 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1228 // Incompatible vsew and vlmax. Skip it.
1229 if (vlmax == 0) {
1230 continue;
1231 }
1232 uint8_t emul =
1233 (vlmul + (kTestVectorInstructionMode == TestVectorInstructionMode::kWidening)) &
1234 0b111;
1235
1236 // To make tests quick enough we don't test vstart and vl change with small register
1237 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of first
1238 // register, last register and half of next-to last register.
1239 // Don't use vlmul == 3 because that one may not be supported if instruction widens the
1240 // result.
1241 if (emul == 2) {
1242 state_.cpu.vstart = vlmax / 8;
1243 state_.cpu.vl = (vlmax * 5) / 8;
1244 } else {
1245 state_.cpu.vstart = 0;
1246 state_.cpu.vl = vlmax;
1247 }
1248 state_.cpu.vtype = vtype;
1249
1250 // Set expected_result vector registers into 0b01010101… pattern.
1251 for (size_t index = 0; index < 8; ++index) {
1252 state_.cpu.v[8 + index] = SIMD128Register{dst_result}.Get<__uint128_t>();
1253 }
1254
1255 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1256 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1257
1258 // Values for inactive elements (i.e. corresponding mask bit is 0).
1259 __m128i expected_inactive[8];
1260 if constexpr (kTestVectorInstructionMode == TestVectorInstructionMode::kVMerge) {
1261 // vs2 is the start of the source vector register group.
1262 // Note: copy_n input/output args are backwards compared to fill_n below.
1263 std::copy_n(source, 8, expected_inactive);
1264 } else {
1265 // For most instructions, follow basic inactive processing rules based on vma flag.
1266 std::fill_n(expected_inactive, 8, (vma ? kAgnosticResult : dst_result));
1267 }
1268
1269 if (emul < 4) {
1270 for (size_t index = 0; index < 1 << emul; ++index) {
1271 if (index == 0 && emul == 2) {
1272 EXPECT_EQ(state_.cpu.v[8 + index],
1273 ((dst_result & kFractionMaskInt8[3]) |
1274 (SIMD128Register{expected_result[index]} & mask[index] &
1275 ~kFractionMaskInt8[3]) |
1276 (expected_inactive[index] & ~mask[index] & ~kFractionMaskInt8[3]))
1277 .template Get<__uint128_t>());
1278 } else if (index == 2 && emul == 2) {
1279 EXPECT_EQ(state_.cpu.v[8 + index],
1280 ((SIMD128Register{expected_result[index]} & mask[index] &
1281 kFractionMaskInt8[3]) |
1282 (expected_inactive[index] & ~mask[index] & kFractionMaskInt8[3]) |
1283 ((vta ? kAgnosticResult : dst_result) & ~kFractionMaskInt8[3]))
1284 .template Get<__uint128_t>());
1285 } else if (index == 3 && emul == 2 && vta) {
1286 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
1287 } else if (index == 3 && emul == 2) {
1288 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{dst_result});
1289 } else {
1290 EXPECT_EQ(state_.cpu.v[8 + index],
1291 ((SIMD128Register{expected_result[index]} & mask[index]) |
1292 ((expected_inactive[index] & ~mask[index])))
1293 .template Get<__uint128_t>());
1294 }
1295 }
1296 } else {
1297 EXPECT_EQ(
1298 state_.cpu.v[8],
1299 ((SIMD128Register{expected_result[0]} & mask[0] & kFractionMaskInt8[emul - 4]) |
1300 (expected_inactive[0] & ~mask[0] & kFractionMaskInt8[emul - 4]) |
1301 ((vta ? kAgnosticResult : dst_result) & ~kFractionMaskInt8[emul - 4]))
1302 .template Get<__uint128_t>());
1303 }
1304
1305 if (emul == 2) {
1306 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1307 EXPECT_EQ(state_.cpu.vstart, 0);
1308 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1309 }
1310 }
1311 }
1312 }
1313 };
1314
1315 // Some instructions don't support use of mask register, but in these instructions bit
1316 // #25 is set. This function doesn't support these. Verify that vm bit is not set.
1317 EXPECT_EQ(insn_bytes & (1 << 25), 0U);
1318 // Every insruction is tested with vm bit not set (and mask register used) and with vm bit
1319 // set (and mask register is not used).
1320 ((Verify(insn_bytes,
1321 BitUtilLog2(sizeof(ElementType)) -
1322 (kTestVectorInstructionMode == TestVectorInstructionMode::kWidening),
1323 8,
1324 expected_result,
1325 MaskForElem<ElementType>()),
1326 Verify((insn_bytes &
1327 ~(0x01f00000 * (kTestVectorInstructionMode == TestVectorInstructionMode::kVMerge))) |
1328 (1 << 25),
1329 BitUtilLog2(sizeof(ElementType)) -
1330 (kTestVectorInstructionMode == TestVectorInstructionMode::kWidening),
1331 8,
1332 expected_result,
1333 kNoMask)),
1334 ...);
1335 }
1336
TestVectorMaskInstruction(uint8_t max_vstart,intrinsics::InactiveProcessing vma,uint32_t insn_bytes,const __v2du expected_result)1337 void TestVectorMaskInstruction(uint8_t max_vstart,
1338 intrinsics::InactiveProcessing vma,
1339 uint32_t insn_bytes,
1340 const __v2du expected_result) {
1341 // Mask instructions don't look on vtype directly, but they still require valid one because it
1342 // affects vlmax;
1343 auto [vlmax, vtype] = intrinsics::Vsetvl(~0ULL, 3 | (static_cast<uint8_t>(vma) << 7));
1344 // We need mask with a few bits set for Vmsₓf instructions. Inverse of normal kMask works.
1345 const __uint128_t mask = SIMD128Register{~kMask}.Get<__uint128_t>();
1346 const __uint128_t undisturbed = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1347 const __uint128_t src1 = SIMD128Register{kVectorCalculationsSourceLegacy[0]}.Get<__uint128_t>();
1348 const __uint128_t src2 = SIMD128Register{kVectorCalculationsSourceLegacy[8]}.Get<__uint128_t>();
1349 const __uint128_t expected = SIMD128Register{expected_result}.Get<__uint128_t>();
1350 state_.cpu.vtype = vtype;
1351 for (uint8_t vl = 0; vl <= vlmax; ++vl) {
1352 state_.cpu.vl = vl;
1353 for (uint8_t vstart = 0; vstart <= max_vstart; ++vstart) {
1354 state_.cpu.vstart = vstart;
1355 // Set expected_result vector registers into 0b01010101… pattern.
1356 state_.cpu.v[0] = mask;
1357 state_.cpu.v[8] = undisturbed;
1358 state_.cpu.v[16] = src1;
1359 state_.cpu.v[24] = src2;
1360
1361 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1362 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1363
1364 for (uint8_t bit_pos = 0; bit_pos < 128; ++bit_pos) {
1365 __uint128_t bit = __uint128_t{1} << bit_pos;
1366 // When vstart ⩾ vl, there are no body elements, and no elements are updated in any
1367 // destinationvector register group, including that no tail elements are updated with
1368 // agnostic values.
1369 if (bit_pos < vstart || vstart >= vl) {
1370 EXPECT_EQ(state_.cpu.v[8] & bit, undisturbed & bit);
1371 } else if (bit_pos >= vl) {
1372 EXPECT_EQ(state_.cpu.v[8] & bit, bit);
1373 } else {
1374 EXPECT_EQ(state_.cpu.v[8] & bit, expected & bit);
1375 }
1376 }
1377 }
1378 }
1379 }
1380
1381 template <typename ElementType>
MaskForElem()1382 auto MaskForElem() {
1383 if constexpr (std::is_same_v<ElementType, uint8_t>) {
1384 return kMaskInt8;
1385 } else if constexpr (std::is_same_v<ElementType, uint16_t>) {
1386 return kMaskInt16;
1387 } else if constexpr (std::is_same_v<ElementType, uint32_t>) {
1388 return kMaskInt32;
1389 } else if constexpr (std::is_same_v<ElementType, uint64_t>) {
1390 return kMaskInt64;
1391 } else {
1392 static_assert(kDependentTypeFalse<ElementType>);
1393 }
1394 }
1395
TestVectorMaskTargetInstruction(uint32_t insn_bytes,const uint32_t expected_result_int32,const uint16_t expected_result_int64,const __v2du (& source)[16])1396 void TestVectorMaskTargetInstruction(uint32_t insn_bytes,
1397 const uint32_t expected_result_int32,
1398 const uint16_t expected_result_int64,
1399 const __v2du (&source)[16]) {
1400 TestVectorMaskTargetInstruction(
1401 insn_bytes, source, expected_result_int32, expected_result_int64);
1402 }
1403
TestVectorMaskTargetInstruction(uint32_t insn_bytes,const uint8_t (& expected_result_int8)[16],const uint64_t expected_result_int16,const uint32_t expected_result_int32,const uint16_t expected_result_int64,const __v2du (& source)[16])1404 void TestVectorMaskTargetInstruction(uint32_t insn_bytes,
1405 const uint8_t (&expected_result_int8)[16],
1406 const uint64_t expected_result_int16,
1407 const uint32_t expected_result_int32,
1408 const uint16_t expected_result_int64,
1409 const __v2du (&source)[16]) {
1410 TestVectorMaskTargetInstruction(insn_bytes,
1411 source,
1412 expected_result_int8,
1413 expected_result_int16,
1414 expected_result_int32,
1415 expected_result_int64);
1416 }
1417
1418 template <typename... ExpectedResultType>
TestVectorMaskTargetInstruction(uint32_t insn_bytes,const __v2du (& source)[16],const ExpectedResultType (&...expected_result))1419 void TestVectorMaskTargetInstruction(uint32_t insn_bytes,
1420 const __v2du (&source)[16],
1421 const ExpectedResultType(&... expected_result)) {
1422 auto Verify = [this, &source](
1423 uint32_t insn_bytes, uint8_t vsew, const auto& expected_result, auto mask) {
1424 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
1425 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
1426 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1427 for (size_t index = 0; index < std::size(source); ++index) {
1428 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
1429 }
1430 // Set x1 for vx instructions.
1431 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaa);
1432 // Set f1 for vf instructions.
1433 if (vsew == 2) {
1434 SetFReg<1>(state_.cpu, 0xffff'ffff'40b4'0000); // float 5.625
1435 } else if (vsew == 3) {
1436 SetFReg<1>(state_.cpu, 0x4016'8000'0000'0000); // double 5.625
1437 }
1438 for (uint8_t vlmul = 0; vlmul < 8; ++vlmul) {
1439 for (uint8_t vta = 0; vta < 2; ++vta) { // vta should be ignored but we test both values!
1440 for (uint8_t vma = 0; vma < 2; ++vma) {
1441 auto [vlmax, vtype] =
1442 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1443 // Incompatible vsew and vlmax. Skip it.
1444 if (vlmax == 0) {
1445 continue;
1446 }
1447
1448 // To make tests quick enough we don't test vstart and vl change with small register
1449 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of first
1450 // register, last register and half of next-to last register.
1451 // Don't use vlmul == 3 because that one may not be supported if instruction widens the
1452 // result.
1453 if (vlmul == 2) {
1454 state_.cpu.vstart = vlmax / 8;
1455 state_.cpu.vl = (vlmax * 5) / 8;
1456 } else {
1457 state_.cpu.vstart = 0;
1458 state_.cpu.vl = vlmax;
1459 }
1460 state_.cpu.vtype = vtype;
1461
1462 // Set expected_result vector registers into 0b01010101… pattern.
1463 for (size_t index = 0; index < 8; ++index) {
1464 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1465 }
1466
1467 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1468 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1469
1470 SIMD128Register expected_result_in_register(expected_result);
1471 if (vma == 0) {
1472 expected_result_in_register = (expected_result_in_register & SIMD128Register{mask}) |
1473 (kUndisturbedResult & ~SIMD128Register{mask});
1474 } else {
1475 expected_result_in_register = expected_result_in_register | ~SIMD128Register{mask};
1476 }
1477 // Mask registers are always processing tail like vta is set.
1478 if (vlmax != 128)
1479 expected_result_in_register |= std::get<0>(
1480 intrinsics::MakeBitmaskFromVl((vlmul == 2) ? (vlmax * 5) / 8 : vlmax));
1481 if (vlmul == 2) {
1482 const auto [start_mask] = intrinsics::MakeBitmaskFromVl(vlmax / 8);
1483 expected_result_in_register = (SIMD128Register{kUndisturbedResult} & ~start_mask) |
1484 (expected_result_in_register & start_mask);
1485 }
1486 EXPECT_EQ(state_.cpu.v[8], expected_result_in_register);
1487
1488 if (vlmul == 2) {
1489 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1490 EXPECT_EQ(state_.cpu.vstart, 0);
1491 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1492 }
1493 }
1494 }
1495 }
1496 };
1497
1498 ((Verify(insn_bytes,
1499 BitUtilLog2(sizeof(SIMD128Register) / sizeof(ExpectedResultType)),
1500 expected_result,
1501 kMask),
1502 Verify(insn_bytes | (1 << 25),
1503 BitUtilLog2(sizeof(SIMD128Register) / sizeof(ExpectedResultType)),
1504 expected_result,
1505 kNoMask[0])),
1506 ...);
1507 }
1508
TestVXmXXsInstruction(uint32_t insn_bytes,const uint64_t (& expected_result_no_mask)[129],const uint64_t (& expected_result_with_mask)[129],const __v2du source)1509 void TestVXmXXsInstruction(uint32_t insn_bytes,
1510 const uint64_t (&expected_result_no_mask)[129],
1511 const uint64_t (&expected_result_with_mask)[129],
1512 const __v2du source) {
1513 auto Verify = [this, &source](uint32_t insn_bytes,
1514 const uint64_t (&expected_result)[129]) {
1515 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1516
1517 auto [vlmax, vtype] = intrinsics::Vsetvl(~0ULL, 3);
1518 state_.cpu.vtype = vtype;
1519 state_.cpu.vstart = 0;
1520 state_.cpu.v[16] = SIMD128Register{source}.Get<__uint128_t>();
1521
1522 for (uint8_t vl = 0; vl <= vlmax; ++vl) {
1523 state_.cpu.vl = vl;
1524 SetXReg<1>(state_.cpu, 0xaaaa'aaaa'aaaa'aaaa);
1525
1526 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1527 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1528 EXPECT_EQ(GetXReg<1>(state_.cpu), expected_result[vl]) << std::to_string(vl);
1529 }
1530 };
1531
1532 Verify(insn_bytes, expected_result_with_mask);
1533 Verify(insn_bytes | (1 << 25), expected_result_no_mask);
1534 }
1535
TestVectorReductionInstruction(uint32_t insn_bytes,const uint32_t (& expected_result_vd0_int32)[8],const uint64_t (& expected_result_vd0_int64)[8],const uint32_t (& expected_result_vd0_with_mask_int32)[8],const uint64_t (& expected_result_vd0_with_mask_int64)[8],const __v2du (& source)[16])1536 void TestVectorReductionInstruction(uint32_t insn_bytes,
1537 const uint32_t (&expected_result_vd0_int32)[8],
1538 const uint64_t (&expected_result_vd0_int64)[8],
1539 const uint32_t (&expected_result_vd0_with_mask_int32)[8],
1540 const uint64_t (&expected_result_vd0_with_mask_int64)[8],
1541 const __v2du (&source)[16]) {
1542 TestVectorReductionInstruction(
1543 insn_bytes,
1544 source,
1545 std::tuple<const uint32_t(&)[8], const uint32_t(&)[8]>{expected_result_vd0_int32,
1546 expected_result_vd0_with_mask_int32},
1547 std::tuple<const uint64_t(&)[8], const uint64_t(&)[8]>{
1548 expected_result_vd0_int64, expected_result_vd0_with_mask_int64});
1549 }
1550
TestVectorReductionInstruction(uint32_t insn_bytes,const uint8_t (& expected_result_vd0_int8)[8],const uint16_t (& expected_result_vd0_int16)[8],const uint32_t (& expected_result_vd0_int32)[8],const uint64_t (& expected_result_vd0_int64)[8],const uint8_t (& expected_result_vd0_with_mask_int8)[8],const uint16_t (& expected_result_vd0_with_mask_int16)[8],const uint32_t (& expected_result_vd0_with_mask_int32)[8],const uint64_t (& expected_result_vd0_with_mask_int64)[8],const __v2du (& source)[16])1551 void TestVectorReductionInstruction(uint32_t insn_bytes,
1552 const uint8_t (&expected_result_vd0_int8)[8],
1553 const uint16_t (&expected_result_vd0_int16)[8],
1554 const uint32_t (&expected_result_vd0_int32)[8],
1555 const uint64_t (&expected_result_vd0_int64)[8],
1556 const uint8_t (&expected_result_vd0_with_mask_int8)[8],
1557 const uint16_t (&expected_result_vd0_with_mask_int16)[8],
1558 const uint32_t (&expected_result_vd0_with_mask_int32)[8],
1559 const uint64_t (&expected_result_vd0_with_mask_int64)[8],
1560 const __v2du (&source)[16]) {
1561 TestVectorReductionInstruction(
1562 insn_bytes,
1563 source,
1564 std::tuple<const uint8_t(&)[8], const uint8_t(&)[8]>{expected_result_vd0_int8,
1565 expected_result_vd0_with_mask_int8},
1566 std::tuple<const uint16_t(&)[8], const uint16_t(&)[8]>{expected_result_vd0_int16,
1567 expected_result_vd0_with_mask_int16},
1568 std::tuple<const uint32_t(&)[8], const uint32_t(&)[8]>{expected_result_vd0_int32,
1569 expected_result_vd0_with_mask_int32},
1570 std::tuple<const uint64_t(&)[8], const uint64_t(&)[8]>{
1571 expected_result_vd0_int64, expected_result_vd0_with_mask_int64});
1572 }
1573
1574 template <typename... ExpectedResultType>
TestVectorReductionInstruction(uint32_t insn_bytes,const __v2du (& source)[16],std::tuple<const ExpectedResultType (&)[8],const ExpectedResultType (&)[8]>...expected_result)1575 void TestVectorReductionInstruction(
1576 uint32_t insn_bytes,
1577 const __v2du (&source)[16],
1578 std::tuple<const ExpectedResultType (&)[8],
1579 const ExpectedResultType (&)[8]>... expected_result) {
1580 // Each expected_result input to this function is the vd[0] value of the reduction, for each
1581 // of the possible vlmul, i.e. expected_result_vd0_int8[n] = vd[0], int8, no mask, vlmul=n.
1582 //
1583 // As vlmul=4 is reserved, expected_result_vd0_*[4] is ignored.
1584 auto Verify = [this, &source](uint32_t insn_bytes,
1585 uint8_t vsew,
1586 uint8_t vlmul,
1587 const auto& expected_result) {
1588 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
1589 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
1590 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1591 for (size_t index = 0; index < std::size(source); ++index) {
1592 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
1593 }
1594 for (uint8_t vta = 0; vta < 2; ++vta) {
1595 for (uint8_t vma = 0; vma < 2; ++vma) {
1596 auto [vlmax, vtype] =
1597 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1598 // Incompatible vsew and vlmax. Skip it.
1599 if (vlmax == 0) {
1600 continue;
1601 }
1602
1603 // Vector reduction instructions must always have a vstart=0.
1604 state_.cpu.vstart = 0;
1605 state_.cpu.vl = vlmax;
1606 state_.cpu.vtype = vtype;
1607
1608 // Set expected_result vector registers into 0b01010101… pattern.
1609 for (size_t index = 0; index < 8; ++index) {
1610 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1611 }
1612
1613 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1614 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1615
1616 // Reduction instructions are unique in that they produce a scalar
1617 // output to a single vector register as opposed to a register group.
1618 // This allows us to take some short-cuts when validating:
1619 //
1620 // - The mask setting is only useful during computation, as the body
1621 // of the destination is always only element 0, which will always be
1622 // written to, regardless of mask setting.
1623 // - The tail is guaranteed to be 1..VLEN/SEW, so the vlmul setting
1624 // does not affect the elements that the tail policy applies to in the
1625 // destination register.
1626
1627 // Verify that the destination register holds the reduction in the
1628 // first element and the tail policy applies to the remaining.
1629 size_t vsew_bits = 8 << vsew;
1630 __uint128_t expected_result_register =
1631 SIMD128Register{vta ? kAgnosticResult : kUndisturbedResult}.Get<__uint128_t>();
1632 expected_result_register = (expected_result_register >> vsew_bits) << vsew_bits;
1633 expected_result_register |= expected_result;
1634 EXPECT_EQ(state_.cpu.v[8], expected_result_register);
1635
1636 // Verify all non-destination registers are undisturbed.
1637 for (size_t index = 1; index < 8; ++index) {
1638 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kUndisturbedResult}.Get<__uint128_t>());
1639 }
1640
1641 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1642 EXPECT_EQ(state_.cpu.vstart, 0);
1643 EXPECT_EQ(state_.cpu.vl, vlmax);
1644 }
1645 }
1646 };
1647
1648 for (int vlmul = 0; vlmul < 8; vlmul++) {
1649 ((Verify(insn_bytes,
1650 BitUtilLog2(sizeof(ExpectedResultType)),
1651 vlmul,
1652 std::get<1>(expected_result)[vlmul]),
1653 Verify(insn_bytes | (1 << 25),
1654 BitUtilLog2(sizeof(ExpectedResultType)),
1655 vlmul,
1656 std::get<0>(expected_result)[vlmul])),
1657 ...);
1658 }
1659 }
1660
TestVectorFloatPermutationInstruction(uint32_t insn_bytes,const uint32_t (& expected_result_int32)[8][4],const uint64_t (& expected_result_int64)[8][2],const __v2du (& source)[16],uint8_t vlmul,uint64_t skip=0,bool ignore_vma_for_last=false,bool last_elem_is_f1=false)1661 void TestVectorFloatPermutationInstruction(uint32_t insn_bytes,
1662 const uint32_t (&expected_result_int32)[8][4],
1663 const uint64_t (&expected_result_int64)[8][2],
1664 const __v2du (&source)[16],
1665 uint8_t vlmul,
1666 uint64_t skip = 0,
1667 bool ignore_vma_for_last = false,
1668 bool last_elem_is_f1 = false) {
1669 TestVectorPermutationInstruction<TestVectorInstructionKind::kFloat>(insn_bytes,
1670 source,
1671 vlmul,
1672 skip,
1673 ignore_vma_for_last,
1674 last_elem_is_f1,
1675 /* regx1 */ 0x0,
1676 expected_result_int32,
1677 expected_result_int64);
1678 }
1679
TestVectorPermutationInstruction(uint32_t insn_bytes,const uint8_t (& expected_result_int8)[8][16],const uint16_t (& expected_result_int16)[8][8],const uint32_t (& expected_result_int32)[8][4],const uint64_t (& expected_result_int64)[8][2],const __v2du (& source)[16],uint8_t vlmul,uint64_t regx1=0x0,uint64_t skip=0,bool ignore_vma_for_last=false,bool last_elem_is_x1=false)1680 void TestVectorPermutationInstruction(uint32_t insn_bytes,
1681 const uint8_t (&expected_result_int8)[8][16],
1682 const uint16_t (&expected_result_int16)[8][8],
1683 const uint32_t (&expected_result_int32)[8][4],
1684 const uint64_t (&expected_result_int64)[8][2],
1685 const __v2du (&source)[16],
1686 uint8_t vlmul,
1687 uint64_t regx1 = 0x0,
1688 uint64_t skip = 0,
1689 bool ignore_vma_for_last = false,
1690 bool last_elem_is_x1 = false) {
1691 TestVectorPermutationInstruction<TestVectorInstructionKind::kInteger>(insn_bytes,
1692 source,
1693 vlmul,
1694 skip,
1695 ignore_vma_for_last,
1696 last_elem_is_x1,
1697 regx1,
1698 expected_result_int8,
1699 expected_result_int16,
1700 expected_result_int32,
1701 expected_result_int64);
1702 }
1703
1704 // Unlike regular arithmetic instructions, the result of a permutation
1705 // instruction depends also on vlmul. Also, the vslideup specs mention that
1706 // the destination vector remains unchanged the first |offset| elements (in
1707 // effect, the offset acts akin to vstart), in those cases skip can be used
1708 // to specify how many elements' mask will be skipped (counting from the
1709 // beginning, should be the same as the offset).
1710 //
1711 // If |ignore_vma_for_last| is true, an inactive element at vl-1 will be
1712 // treated as if vma=0 (Undisturbed).
1713 // If |last_elem_is_reg1| is true, the last element of the vector in
1714 // expected_result (that is, at vl-1) will be expected to be the same as
1715 // |regx1| when VL < VMAX and said element is active.
1716 template <TestVectorInstructionKind kTestVectorInstructionKind,
1717 typename... ElementType,
1718 size_t... kResultsCount,
1719 size_t... kElementCount>
TestVectorPermutationInstruction(uint32_t insn_bytes,const __v2du (& source)[16],uint8_t vlmul,uint64_t skip,bool ignore_vma_for_last,bool last_elem_is_reg1,uint64_t regx1,const ElementType (&...expected_result)[kResultsCount][kElementCount])1720 void TestVectorPermutationInstruction(
1721 uint32_t insn_bytes,
1722 const __v2du (&source)[16],
1723 uint8_t vlmul,
1724 uint64_t skip,
1725 bool ignore_vma_for_last,
1726 bool last_elem_is_reg1,
1727 uint64_t regx1,
1728 const ElementType (&... expected_result)[kResultsCount][kElementCount]) {
1729 auto Verify = [this, &source, vlmul, regx1, skip, ignore_vma_for_last, last_elem_is_reg1](
1730 uint32_t insn_bytes,
1731 uint8_t vsew,
1732 const auto& expected_result_raw,
1733 auto mask) {
1734 // Mask register is, unconditionally, v0, and we need 8, 16, or 24 to handle full 8-registers
1735 // inputs thus we use v8..v15 for destination and place sources into v16..v23 and v24..v31.
1736 state_.cpu.v[0] = SIMD128Register{kMask}.Get<__uint128_t>();
1737 for (size_t index = 0; index < std::size(source); ++index) {
1738 state_.cpu.v[16 + index] = SIMD128Register{source[index]}.Get<__uint128_t>();
1739 }
1740
1741 if constexpr (kTestVectorInstructionKind == TestVectorInstructionKind::kFloat) {
1742 UNUSED(regx1);
1743 // We only support Float32/Float64 for float instructions, but there are conversion
1744 // instructions that work with double width floats.
1745 // These instructions never use float registers though and thus we don't need to store
1746 // anything into f1 register, if they are used.
1747 // For Float32/Float64 case we load 5.625 of the appropriate type into f1.
1748 ASSERT_LE(vsew, 3);
1749 if (vsew == 2) {
1750 SetFReg<1>(state_.cpu, 0xffff'ffff'40b4'0000); // float 5.625
1751 } else if (vsew == 3) {
1752 SetFReg<1>(state_.cpu, 0x4016'8000'0000'0000); // double 5.625
1753 }
1754 } else {
1755 // Set x1 for vx instructions.
1756 SetXReg<1>(state_.cpu, regx1);
1757 }
1758
1759 const size_t kElementSize = 1 << vsew;
1760 size_t num_regs = 1 << vlmul;
1761 if (vlmul > 3) {
1762 num_regs = 1;
1763 }
1764 // Values for which the mask is not applied due to being before the offset when doing
1765 // vslideup.
1766 SIMD128Register skip_mask[num_regs];
1767 int64_t toskip = skip;
1768 for (size_t index = 0; index < num_regs && toskip > 0; ++index) {
1769 size_t skip_bits = toskip * kElementSize * 8;
1770 skip_mask[index] =
1771 ~std::get<0>(intrinsics::MakeBitmaskFromVl(skip_bits > 128 ? 128 : skip_bits));
1772 toskip -= 16 / kElementSize;
1773 }
1774
1775 for (uint8_t vta = 0; vta < 2; ++vta) {
1776 for (uint8_t vma = 0; vma < 2; ++vma) {
1777 auto [vlmax, vtype] =
1778 intrinsics::Vsetvl(~0ULL, (vma << 7) | (vta << 6) | (vsew << 3) | vlmul);
1779 // Incompatible vsew and vlmax. Skip it.
1780 if (vlmax == 0) {
1781 continue;
1782 }
1783
1784 // To make tests quick enough we don't test vstart and vl change with small register
1785 // sets. Only with vlmul == 2 (4 registers) we set vstart and vl to skip half of first
1786 // register, last register and half of next-to last register.
1787 // Don't use vlmul == 3 because that one may not be supported if instruction widens the
1788 // result.
1789 if (vlmul == 2) {
1790 state_.cpu.vstart = vlmax / 8;
1791 state_.cpu.vl = (vlmax * 5) / 8;
1792 } else {
1793 state_.cpu.vstart = 0;
1794 state_.cpu.vl = vlmax;
1795 }
1796 state_.cpu.vtype = vtype;
1797
1798 // Set dst vector registers into 0b01010101… pattern.
1799 for (size_t index = 0; index < 8; ++index) {
1800 state_.cpu.v[8 + index] = SIMD128Register{kUndisturbedResult}.Get<__uint128_t>();
1801 }
1802
1803 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
1804 EXPECT_TRUE(RunOneInstruction(&state_, state_.cpu.insn_addr + 4));
1805
1806 const size_t n = std::size(source);
1807 // Values for inactive elements (i.e. corresponding mask bit is 0).
1808 __m128i expected_inactive[n];
1809 // For most instructions, follow basic inactive processing rules based on vma flag.
1810 std::fill_n(expected_inactive, n, (vma ? kAgnosticResult : kUndisturbedResult));
1811
1812 const size_t kElementsPerRegister = 16 / kElementSize;
1813 const size_t last_reg = (state_.cpu.vl - 1) / kElementsPerRegister;
1814 const size_t last_elem = (state_.cpu.vl - 1) % kElementsPerRegister;
1815 const auto [mask_for_vl] = intrinsics::MakeBitmaskFromVl(last_elem * kElementSize * 8);
1816 if (vma && ignore_vma_for_last) {
1817 // Set expected value for inactive element at vl-1 to Undisturbed.
1818 expected_inactive[last_reg] =
1819 ((expected_inactive[last_reg] & ~mask_for_vl) | (kUndisturbedResult & mask_for_vl))
1820 .Get<__m128i>();
1821 }
1822
1823 SIMD128Register expected_result[std::size(expected_result_raw)];
1824 for (size_t index = 0; index < std::size(expected_result_raw); ++index) {
1825 expected_result[index] = SIMD128Register{expected_result_raw[index]};
1826 }
1827
1828 if (vlmul == 2 && last_elem_is_reg1) {
1829 switch (kElementSize) {
1830 case 1:
1831 expected_result[last_reg].template Set<uint8_t>(
1832 static_cast<uint8_t>(GetXReg<1>(state_.cpu)), last_elem);
1833 break;
1834 case 2:
1835 expected_result[last_reg].template Set<uint16_t>(
1836 static_cast<uint16_t>(GetXReg<1>(state_.cpu)), last_elem);
1837 break;
1838 case 4:
1839 if constexpr (kTestVectorInstructionKind == TestVectorInstructionKind::kFloat) {
1840 expected_result[last_reg].template Set<uint32_t>(
1841 static_cast<uint32_t>(GetFReg<1>(state_.cpu)), last_elem);
1842 } else {
1843 expected_result[last_reg].template Set<uint32_t>(
1844 static_cast<uint32_t>(GetXReg<1>(state_.cpu)), last_elem);
1845 }
1846 break;
1847 case 8:
1848 if constexpr (kTestVectorInstructionKind == TestVectorInstructionKind::kFloat) {
1849 expected_result[last_reg].template Set<uint64_t>(
1850 static_cast<uint64_t>(GetFReg<1>(state_.cpu)), last_elem);
1851 } else {
1852 expected_result[last_reg].template Set<uint64_t>(
1853 static_cast<uint64_t>(GetXReg<1>(state_.cpu)), last_elem);
1854 }
1855 break;
1856 default:
1857 FAIL() << "Element size is " << kElementSize;
1858 }
1859 }
1860
1861 if (vlmul < 4) {
1862 for (size_t index = 0; index < num_regs; ++index) {
1863 if (index == 0 && vlmul == 2) {
1864 EXPECT_EQ(
1865 state_.cpu.v[8 + index],
1866 SIMD128Register{(kUndisturbedResult & kFractionMaskInt8[3]) |
1867 (expected_result[index] & (mask[index] | skip_mask[index]) &
1868 ~kFractionMaskInt8[3]) |
1869 (expected_inactive[index] & ~mask[index] & ~skip_mask[index] &
1870 ~kFractionMaskInt8[3])}
1871 .Get<__uint128_t>());
1872 } else if (index == 2 && vlmul == 2) {
1873 EXPECT_EQ(
1874 state_.cpu.v[8 + index],
1875 SIMD128Register{
1876 (expected_result[index] & (mask[index] | skip_mask[index]) &
1877 kFractionMaskInt8[3]) |
1878 (expected_inactive[index] & ~mask[index] & ~skip_mask[index] &
1879 kFractionMaskInt8[3]) |
1880 ((vta ? kAgnosticResult : kUndisturbedResult) & ~kFractionMaskInt8[3])}
1881 .Get<__uint128_t>());
1882 } else if (index == 3 && vlmul == 2 && vta) {
1883 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kAgnosticResult});
1884 } else if (index == 3 && vlmul == 2) {
1885 EXPECT_EQ(state_.cpu.v[8 + index], SIMD128Register{kUndisturbedResult});
1886 } else {
1887 EXPECT_EQ(
1888 state_.cpu.v[8 + index],
1889 SIMD128Register{(expected_result[index] & (mask[index] | skip_mask[index])) |
1890 (expected_inactive[index] & ~(mask[index] | skip_mask[index]))}
1891 .Get<__uint128_t>());
1892 }
1893 }
1894 } else {
1895 __uint128_t v8 = state_.cpu.v[8];
1896 SIMD128Register affected_part{expected_result[0] &
1897 (mask[0] & kFractionMaskInt8[vlmul - 4] | skip_mask[0])};
1898 SIMD128Register masked_part{expected_inactive[0] & ~mask[0] & ~skip_mask[0] &
1899 kFractionMaskInt8[vlmul - 4]};
1900 SIMD128Register tail_part{(vta ? kAgnosticResult : kUndisturbedResult) &
1901 ~kFractionMaskInt8[vlmul - 4]};
1902
1903 EXPECT_EQ(v8, (affected_part | masked_part | tail_part).Get<__uint128_t>());
1904 }
1905
1906 if (vlmul == 2) {
1907 // Every vector instruction must set vstart to 0, but shouldn't touch vl.
1908 EXPECT_EQ(state_.cpu.vstart, 0);
1909 EXPECT_EQ(state_.cpu.vl, (vlmax * 5) / 8);
1910 }
1911 }
1912 }
1913 };
1914
1915 // Test with and without masking enabled.
1916 (Verify(
1917 insn_bytes, BitUtilLog2(sizeof(ElementType)), expected_result, MaskForElem<ElementType>()),
1918 ...);
1919 (Verify(insn_bytes | (1 << 25), BitUtilLog2(sizeof(ElementType)), expected_result, kNoMask),
1920 ...);
1921 }
1922
1923 protected:
1924 static constexpr __v2du kVectorCalculationsSource[16] = {
1925 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
1926 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
1927 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
1928 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
1929 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
1930 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
1931 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
1932 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978},
1933
1934 {0x9e0c'9a09'9604'9200, 0x8e1c'8a18'8614'8211},
1935 {0xbe2c'ba29'b624'b220, 0xae3c'aa38'a634'a231},
1936 {0xde4c'da49'd644'd240, 0xce5c'ca58'c654'c251},
1937 {0xfe6c'fa69'f664'f260, 0xee7c'ea78'e674'e271},
1938 {0x1e8c'1a89'1684'1280, 0x0e9c'0a98'0694'0291},
1939 {0x3eac'3aa9'36a4'32a0, 0x2ebc'2ab8'26b4'22b1},
1940 {0x5ecc'5ac9'56c4'52c0, 0x4edc'4ad8'46d4'42d1},
1941 {0x7eec'7ae9'76e4'72e0, 0x6efc'6af8'66f4'62f1},
1942 };
1943
1944 static constexpr __v2du kVfClassSource[16] = {
1945 {0x8000'0000'0000'0000, 0x8e1c'8a18'8614'8211},
1946 {0x0000'0000'0000'0000, 0xae3c'aa38'a634'a231},
1947 {0x7ff0'0000'0000'0000, 0xff80'0000'7f80'0000},
1948 {0xfff0'0000'0000'0000, 0xee7c'ea78'e674'e271},
1949 {0x1e8c'1a89'1684'1280, 0x0e9c'0a98'0694'0291},
1950 {0x3eac'3aa9'36a4'32a0, 0x2ebc'2ab8'26b4'22b1},
1951 {0x5ecc'5ac9'56c4'52c0, 0x4edc'4ad8'46d4'42d1},
1952 {0x7fb7'ffff'7fb7'ffff, 0x7ff7'ffff'ffff'ffff},
1953
1954 {0x8000'0000'0000'0000, 0x8e1c'8a18'8614'8211},
1955 {0x0000'0000'0000'0000, 0xae3c'aa38'a634'a231},
1956 {0x7ff0'0000'0000'0000, 0xff80'0000'7f80'0000},
1957 {0xfff0'0000'0000'0000, 0xee7c'ea78'e674'e271},
1958 {0x1e8c'1a89'1684'1280, 0x0e9c'0a98'0694'0291},
1959 {0x3eac'3aa9'36a4'32a0, 0x2ebc'2ab8'26b4'22b1},
1960 {0x5ecc'5ac9'56c4'52c0, 0x4edc'4ad8'46d4'42d1},
1961 {0x7fb7'ffff'7fb7'ffff, 0x7ff7'ffff'ffff'ffff},
1962 };
1963
1964 static constexpr __v2du kVectorCalculationsSourceLegacy[16] = {
1965 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
1966 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
1967 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
1968 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
1969 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
1970 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
1971 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
1972 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978},
1973
1974 {0x0e0c'0a09'0604'0200, 0x1e1c'1a18'1614'1211},
1975 {0x2e2c'2a29'2624'2220, 0x3e3c'3a38'3634'3231},
1976 {0x4e4c'4a49'4644'4240, 0x5e5c'5a58'5654'5251},
1977 {0x6e6c'6a69'6664'6260, 0x7e7c'7a78'7674'7271},
1978 {0x8e8c'8a89'8684'8280, 0x9e9c'9a98'9694'9291},
1979 {0xaeac'aaa9'a6a4'a2a0, 0xbebc'bab8'b6b4'b2b1},
1980 {0xcecc'cac9'c6c4'c2c0, 0xdedc'dad8'd6d4'd2d1},
1981 {0xeeec'eae9'e6e4'e2e0, 0xfefc'faf8'f6f4'f2f1},
1982 };
1983
1984 static constexpr __v2du kVectorComparisonSource[16] = {
1985 {0xf005'f005'f005'f005, 0xffff'ffff'4040'4040},
1986 {0xffff'ffff'40b4'40b4, 0xffff'ffff'40b4'0000},
1987 {0x4016'4016'4016'4016, 0x4016'8000'0000'0000},
1988 {0xaaaa'aaaa'aaaa'aaaa, 0x1111'1111'1111'1111},
1989 {0xfff4'fff4'fff4'fff4, 0xfff6'fff6'fff6'fff6},
1990 {0xfff8'fff8'fff4'fff4, 0xfff5'fff5'fff5'fff5},
1991 {0xa9bb'bbbb'a9bb'bbbb, 0xa9bb'bbbb'a9bb'bbbb},
1992 {0xa9a9'a9a9'a9a9'a9a9, 0xa9a9'a9a9'a9a9'a9a9},
1993
1994 {0xf005'f005'f005'f005, 0xffff'ffff'4040'4040},
1995 {0x1111'1111'1111'1111, 0x1111'1111'1111'1111},
1996 {0xfff1'fff1'fff1'fff1, 0xfff1'fff1'fff1'fff1},
1997 {0x6e6c'6a69'6664'6260, 0x7e7c'7a78'7674'7271},
1998 {0x8e8c'8a89'8684'8280, 0x9e9c'9a98'9694'9291},
1999 {0xaeac'aaa9'a6a4'a2a0, 0xbebc'bab8'b6b4'b2b1},
2000 {0xcecc'cac9'c6c4'c2c0, 0xdedc'dad8'd6d4'd2d1},
2001 {0xeeec'eae9'e6e4'e2e0, 0xfefc'faf8'f6f4'f2f1},
2002 };
2003
2004 // Mask in form suitable for storing in v0 and use in v0.t form.
2005 static constexpr __v2du kMask = {0xd5ad'd6b5'ad6b'b5ad, 0x6af7'57bb'deed'7bb5};
2006 // Mask used with vsew = 0 (8bit) elements.
2007 static constexpr __v16qu kMaskInt8[8] = {
2008 {255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255},
2009 {255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255},
2010 {255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 255},
2011 {255, 0, 255, 255, 0, 255, 0, 255, 255, 0, 255, 0, 255, 0, 255, 255},
2012 {255, 0, 255, 0, 255, 255, 0, 255, 255, 255, 0, 255, 255, 255, 255, 0},
2013 {255, 0, 255, 255, 0, 255, 255, 255, 0, 255, 255, 255, 255, 0, 255, 255},
2014 {255, 255, 0, 255, 255, 255, 0, 255, 255, 255, 255, 0, 255, 0, 255, 0},
2015 {255, 255, 255, 0, 255, 255, 255, 255, 0, 255, 0, 255, 0, 255, 255, 0},
2016 };
2017 // Mask used with vsew = 1 (16bit) elements.
2018 static constexpr __v8hu kMaskInt16[8] = {
2019 {0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff},
2020 {0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff},
2021 {0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff, 0x0000},
2022 {0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff},
2023 {0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff},
2024 {0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff},
2025 {0xffff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff},
2026 {0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0x0000, 0xffff, 0xffff},
2027 };
2028 // Mask used with vsew = 2 (32bit) elements.
2029 static constexpr __v4su kMaskInt32[8] = {
2030 {0xffff'ffff, 0x0000'0000, 0xffff'ffff, 0xffff'ffff},
2031 {0x0000'0000, 0xffff'ffff, 0x0000'0000, 0xffff'ffff},
2032 {0xffff'ffff, 0x0000'0000, 0xffff'ffff, 0x0000'0000},
2033 {0xffff'ffff, 0xffff'ffff, 0x0000'0000, 0xffff'ffff},
2034 {0xffff'ffff, 0xffff'ffff, 0x0000'0000, 0xffff'ffff},
2035 {0x0000'0000, 0xffff'ffff, 0xffff'ffff, 0x0000'0000},
2036 {0xffff'ffff, 0x0000'0000, 0xffff'ffff, 0xffff'ffff},
2037 {0x0000'0000, 0xffff'ffff, 0x0000'0000, 0xffff'ffff},
2038 };
2039 // Mask used with vsew = 3 (64bit) elements.
2040 static constexpr __v2du kMaskInt64[8] = {
2041 {0xffff'ffff'ffff'ffff, 0x0000'0000'0000'0000},
2042 {0xffff'ffff'ffff'ffff, 0xffff'ffff'ffff'ffff},
2043 {0x0000'0000'0000'0000, 0xffff'ffff'ffff'ffff},
2044 {0x0000'0000'0000'0000, 0xffff'ffff'ffff'ffff},
2045 {0xffff'ffff'ffff'ffff, 0x0000'0000'0000'0000},
2046 {0xffff'ffff'ffff'ffff, 0x0000'0000'0000'0000},
2047 {0xffff'ffff'ffff'ffff, 0xffff'ffff'ffff'ffff},
2048 {0x0000'0000'0000'0000, 0xffff'ffff'ffff'ffff},
2049 };
2050 // To verify operations without masking.
2051 static constexpr __v16qu kNoMask[8] = {
2052 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2053 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2054 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2055 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2056 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2057 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2058 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2059 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
2060 };
2061 // Half of sub-register lmul.
2062 static constexpr __v16qu kFractionMaskInt8[5] = {
2063 {255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Half of ⅛ reg = ¹⁄₁₆
2064 {255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Half of ¼ reg = ⅛
2065 {255, 255, 255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Half of ½ reg = ¼
2066 {255, 255, 255, 255, 255, 255, 255, 255, 0, 0, 0, 0, 0, 0, 0, 0}, // Half of full reg = ½
2067 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255}, // Full reg
2068 };
2069 // Agnostic result is -1 on RISC-V, not 0.
2070 static constexpr __m128i kAgnosticResult = {-1, -1};
2071 // Undisturbed result is put in registers v8, v9, …, v15 and is expected to get read back.
2072 static constexpr __m128i kUndisturbedResult = {0x5555'5555'5555'5555, 0x5555'5555'5555'5555};
2073 // Note: permutation of indexes here is not entirely random. First 32 indexes are limited to 31
2074 // maximum and first 64 indexes are limited to 63. That way we can guarantee that 8byte elements
2075 // and 4byte elements wouldn't need to access area outside of our 256-byte buffer.
2076 static constexpr uint8_t kPermutedIndexes[128] = {
2077 1, 0, 3, 2, 7, 5, 4, 6, 9, 14, 15, 11, 13, 12, 8, 10, 30, 31, 17,
2078 22, 18, 26, 25, 19, 29, 28, 16, 21, 27, 24, 20, 23, 44, 50, 52, 34, 61, 38,
2079 54, 43, 42, 63, 57, 40, 36, 46, 39, 47, 35, 41, 62, 59, 60, 51, 55, 53, 33,
2080 32, 58, 49, 56, 37, 45, 48, 124, 92, 78, 101, 114, 89, 75, 64, 98, 112, 111, 118,
2081 121, 102, 73, 105, 109, 68, 103, 72, 110, 79, 119, 96, 123, 85, 90, 126, 66, 69, 120,
2082 97, 113, 76, 100, 67, 125, 117, 65, 84, 104, 122, 71, 81, 99, 70, 91, 86, 115, 127,
2083 77, 107, 74, 93, 80, 106, 87, 94, 83, 95, 116, 108, 82, 88};
2084
2085 // Store area for store instructions. We need at least 16 uint64_t to handle 8×128bit registers,
2086 // plus 2× of that to test strided instructions.
2087 alignas(16) uint64_t store_area_[32];
2088
2089 ThreadState state_;
2090 };
2091
2092 #define TESTSUITE Riscv64InterpretInsnTest
2093 #define TESTING_INTERPRETER
2094
2095 #include "berberis/test_utils/insn_tests_riscv64-inl.h"
2096
2097 #undef TESTING_INTERPRETER
2098 #undef TESTSUITE
2099
2100 // Tests for Non-Compressed Instructions.
2101
TEST_F(Riscv64InterpreterTest,FenceInstructions)2102 TEST_F(Riscv64InterpreterTest, FenceInstructions) {
2103 // Fence
2104 InterpretFence(0x0ff0000f);
2105 // FenceTso
2106 InterpretFence(0x8330000f);
2107
2108 // FenceI explicitly not supported.
2109 }
2110
TEST_F(Riscv64InterpreterTest,SyscallWrite)2111 TEST_F(Riscv64InterpreterTest, SyscallWrite) {
2112 const char message[] = "Hello";
2113 // Prepare a pipe to write to.
2114 int pipefd[2];
2115 ASSERT_EQ(0, pipe(pipefd));
2116
2117 // Only ecall instruction needs guest thread, since it involves pending signals manipulations.
2118 std::unique_ptr<GuestThread, decltype(&GuestThread::Destroy)> guest_thread(
2119 GuestThread::CreateForTest(&state_), GuestThread::Destroy);
2120 state_.thread = guest_thread.get();
2121
2122 // SYS_write
2123 SetXReg<17>(state_.cpu, 0x40);
2124 // File descriptor
2125 SetXReg<10>(state_.cpu, pipefd[1]);
2126 // String
2127 SetXReg<11>(state_.cpu, bit_cast<uint64_t>(&message[0]));
2128 // Size
2129 SetXReg<12>(state_.cpu, sizeof(message));
2130
2131 uint32_t insn_bytes = 0x00000073;
2132 state_.cpu.insn_addr = ToGuestAddr(&insn_bytes);
2133 InterpretInsn(&state_);
2134
2135 // Check number of bytes written.
2136 EXPECT_EQ(GetXReg<10>(state_.cpu), sizeof(message));
2137
2138 // Check the message was written to the pipe.
2139 char buf[sizeof(message)] = {};
2140 ssize_t read_size = read(pipefd[0], &buf, sizeof(buf));
2141 EXPECT_NE(read_size, -1);
2142 EXPECT_EQ(0, strcmp(message, buf));
2143 close(pipefd[0]);
2144 close(pipefd[1]);
2145 }
2146
TEST_F(Riscv64InterpreterTest,TestFPExceptions)2147 TEST_F(Riscv64InterpreterTest, TestFPExceptions) {
2148 // Keep the same sort as Section 19 "Vector Instruction Listing".
2149 TestFPExceptions<intrinsics::Float32>(0x012d1557); // Vfadd.vv v10, v18, v26, v0.t
2150 TestFPExceptions<intrinsics::Float64>(0x010c1457); // Vfadd.vv v8, v16, v24, v0.t
2151 TestFPExceptions<intrinsics::Float32>(0x0120d557); // Vfadd.vf v10, v18, f1, v0.t
2152 TestFPExceptions<intrinsics::Float64>(0x01015457); // Vfadd.vf v8, v16, f2, v0.t
2153 TestFPExceptions<intrinsics::Float32>(0x092d1557); // Vfsub.vv v10, v18, v26, v0.t
2154 TestFPExceptions<intrinsics::Float64>(0x090c1457); // Vfsub.vv v8, v16, v24, v0.t
2155 TestFPExceptions<intrinsics::Float32>(0x0920d557); // Vfsub.vf v10, v18, f1, v0.t
2156 TestFPExceptions<intrinsics::Float64>(0x09015457); // Vfsub.vf v8, v16, f2, v0.t
2157 TestFPExceptions<intrinsics::Float32>(0x812d1557); // Vfdiv.vv v10, v18, v26, v0.t
2158 TestFPExceptions<intrinsics::Float64>(0x810c1457); // Vfdiv.vv v8, v16, v24, v0.t
2159 TestFPExceptions<intrinsics::Float32>(0x8120d557); // Vfdiv.vf v10, v18, f1, v0.t
2160 TestFPExceptions<intrinsics::Float64>(0x81015457); // Vfdiv.vf v8, v16, f2, v0.t
2161 TestFPExceptions<intrinsics::Float32>(0x912d1557); // Vfmul.vv v10, v18, v26, v0.t
2162 TestFPExceptions<intrinsics::Float64>(0x910c1457); // Vfmul.vv v8, v16, v24, v0.t
2163 TestFPExceptions<intrinsics::Float32>(0x9120d557); // Vfmul.vf v10, v18, f1, v0.t
2164 TestFPExceptions<intrinsics::Float64>(0x91015457); // Vfmul.vf v8, v16, f2, v0.t
2165 TestFPExceptions<intrinsics::Float32>(0x9d20d557); // Vfrsub.vf v10, v18, f1, v0.t
2166 TestFPExceptions<intrinsics::Float64>(0x9d015457); // Vfrsub.vf v8, v16, f2, v0.t
2167 }
2168
TEST_F(Riscv64InterpreterTest,TestVlXreXX)2169 TEST_F(Riscv64InterpreterTest, TestVlXreXX) {
2170 TestVlXreXX<1>(0x2808407); // vl1re8.v v8, (x1)
2171 TestVlXreXX<2>(0x22808407); // vl2re8.v v8, (x1)
2172 TestVlXreXX<4>(0x62808407); // vl4re8.v v8, (x1)
2173 TestVlXreXX<8>(0xe2808407); // vl8re8.v v8, (x1)
2174
2175 TestVlXreXX<1>(0x280d407); // vl1re16.v v8, (x1)
2176 TestVlXreXX<2>(0x2280d407); // vl2re16.v v8, (x1)
2177 TestVlXreXX<4>(0x6280d407); // vl4re16.v v8, (x1)
2178 TestVlXreXX<8>(0xe280d407); // vl8re16.v v8, (x1)
2179
2180 TestVlXreXX<1>(0x280e407); // vl1re32.v v8, (x1)
2181 TestVlXreXX<2>(0x2280e407); // vl2re32.v v8, (x1)
2182 TestVlXreXX<4>(0x6280e407); // vl4re32.v v8, (x1)
2183 TestVlXreXX<8>(0xe280e407); // vl8re32.v v8, (x1)
2184
2185 TestVlXreXX<1>(0x280f407); // vl1re64.v v8, (x1)
2186 TestVlXreXX<2>(0x2280f407); // vl2re64.v v8, (x1)
2187 TestVlXreXX<4>(0x6280f407); // vl4re64.v v8, (x1)
2188 TestVlXreXX<8>(0xe280f407); // vl8re64.v v8, (x1)
2189 }
2190
TEST_F(Riscv64InterpreterTest,TestVmXr)2191 TEST_F(Riscv64InterpreterTest, TestVmXr) {
2192 TestVmvXr<1>(0x9f003457); // Vmv1r.v v8, v16
2193 TestVmvXr<2>(0x9f00b457); // Vmv2r.v v8, v16
2194 TestVmvXr<4>(0x9f01b457); // Vmv4r.v v8, v16
2195 TestVmvXr<8>(0x9f03b457); // Vmv8r.v v8, v16
2196 }
2197
TEST_F(Riscv64InterpreterTest,TestVfrsqrt7)2198 TEST_F(Riscv64InterpreterTest, TestVfrsqrt7) {
2199 TestVectorFloatInstruction(0x4d821457, // Vfrsqrt7.v v8, v24, v0.t
2200 {{0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000},
2201 {0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000},
2202 {0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000},
2203 {0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000, 0x7fc0'0000},
2204 {0x53fb'8000, 0x4ff4'8000, 0x5bed'8000, 0x57e7'8000},
2205 {0x43e2'0000, 0x3fdc'8000, 0x4bd7'8000, 0x47d3'0000},
2206 {0x33ce'8000, 0x2fca'8000, 0x3bc6'8000, 0x37c3'0000},
2207 {0x23bf'8000, 0x1fbc'8000, 0x2bb9'0000, 0x27b6'8000}},
2208 {{0x7ff8'0000'0000'0000, 0x7ff8'0000'0000'0000},
2209 {0x7ff8'0000'0000'0000, 0x7ff8'0000'0000'0000},
2210 {0x7ff8'0000'0000'0000, 0x7ff8'0000'0000'0000},
2211 {0x7ff8'0000'0000'0000, 0x7ff8'0000'0000'0000},
2212 {0x50a1'1000'0000'0000, 0x5898'3000'0000'0000},
2213 {0x4091'1000'0000'0000, 0x4888'2000'0000'0000},
2214 {0x3081'0000'0000'0000, 0x3878'1000'0000'0000},
2215 {0x2071'0000'0000'0000, 0x2868'0000'0000'0000}},
2216 kVectorCalculationsSource);
2217 }
2218
TEST_F(Riscv64InterpreterTest,TestVfclass)2219 TEST_F(Riscv64InterpreterTest, TestVfclass) {
2220 TestVectorFloatInstruction(0x4d881457, // Vfclass.v v8, v24, v0.t
2221 {{0x0000'0010, 0x0000'0008, 0x0000'0002, 0x0000'0002},
2222 {0x0000'0010, 0x0000'0010, 0x0000'0002, 0x0000'0002},
2223 {0x0000'0010, 0x0000'0200, 0x0000'0080, 0x0000'0001},
2224 {0x0000'0010, 0x0000'0200, 0x0000'0002, 0x0000'0002},
2225 {0x0000'0040, 0x0000'0040, 0x0000'0040, 0x0000'0040},
2226 {0x0000'0040, 0x0000'0040, 0x0000'0040, 0x0000'0040},
2227 {0x0000'0040, 0x0000'0040, 0x0000'0040, 0x0000'0040},
2228 {0x0000'0100, 0x0000'0100, 0x0000'0200, 0x0000'0200}},
2229 {{0x0000'0000'0000'0008, 0x0000'0000'0000'0002},
2230 {0x0000'0000'0000'0010, 0x0000'0000'0000'0002},
2231 {0x0000'0000'0000'0080, 0x0000'0000'0000'0002},
2232 {0x0000'0000'0000'0001, 0x0000'0000'0000'0002},
2233 {0x0000'0000'0000'0040, 0x0000'0000'0000'0040},
2234 {0x0000'0000'0000'0040, 0x0000'0000'0000'0040},
2235 {0x0000'0000'0000'0040, 0x0000'0000'0000'0040},
2236 {0x0000'0000'0000'0040, 0x0000'0000'0000'0100}},
2237 kVfClassSource);
2238 }
2239
TEST_F(Riscv64InterpreterTest,TestVfmvfs)2240 TEST_F(Riscv64InterpreterTest, TestVfmvfs) {
2241 TestVfmvfs<intrinsics::Float32>(0x428010d7, 0xffff'ffff'8302'8100); // Vfmv.f.s f1, v8
2242 TestVfmvfs<intrinsics::Float64>(0x428010d7, 0x8706'8504'8302'8100); // Vfmv.f.s f1, v8
2243 }
2244
TEST_F(Riscv64InterpreterTest,TestVfmvsf)2245 TEST_F(Riscv64InterpreterTest, TestVfmvsf) {
2246 TestVfmvsf<intrinsics::Float32>(0x4200d457, // Vfmv.s.f v8, f1
2247 0xffff'ffff'40b4'0000,
2248 intrinsics::Float32{5.625f});
2249 TestVfmvsf<intrinsics::Float64>(0x4200d457, // Vfmv.s.f v8, f1
2250 0x4016'8000'0000'0000,
2251 intrinsics::Float64{5.625});
2252 }
2253
TEST_F(Riscv64InterpreterTest,TestVmvsx)2254 TEST_F(Riscv64InterpreterTest, TestVmvsx) {
2255 TestVmvsx<Int8>(0x4200e457); // Vmv.s.x v8, x1
2256 TestVmvsx<Int16>(0x4200e457); // Vmv.s.x v8, x1
2257 TestVmvsx<Int32>(0x4200e457); // Vmv.s.x v8, x1
2258 TestVmvsx<Int64>(0x4200e457); // Vmv.s.x v8, x1
2259 }
2260
TEST_F(Riscv64InterpreterTest,TestVmvxs)2261 TEST_F(Riscv64InterpreterTest, TestVmvxs) {
2262 TestVmvxs<Int8>(0x428020d7, 0); // Vmv.x.s x1, v8
2263 TestVmvxs<Int16>(0x428020d7, 0xffff'ffff'ffff'8100); // Vmv.x.s x1, v8
2264 TestVmvxs<Int32>(0x428020d7, 0xffff'ffff'8302'8100); // Vmv.x.s x1, v8
2265 TestVmvxs<Int64>(0x428020d7, 0x8706'8504'8302'8100); // Vmv.x.s x1, v8
2266 }
2267
TEST_F(Riscv64InterpreterTest,TestVsX)2268 TEST_F(Riscv64InterpreterTest, TestVsX) {
2269 TestVsX<1>(0x2808427); // vs1r.v v8, (x1)
2270 TestVsX<2>(0x22808427); // vs2r.v v8, (x1)
2271 TestVsX<4>(0x62808427); // vs4r.v v8, (x1)
2272 TestVsX<8>(0xe2808427); // vs8r.v v8, (x1)
2273 }
2274
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew8_vlmul1)2275 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew8_vlmul1) {
2276 VlxsegXeiXX<UInt8, 1, 1>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2277 {{129, 0, 131, 2, 135, 133, 4, 6, 137, 14, 143, 139, 141, 12, 8, 10}});
2278 }
2279
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew8_vlmul2)2280 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew8_vlmul2) {
2281 VlxsegXeiXX<UInt8, 1, 2>(
2282 0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2283 {{129, 0, 131, 2, 135, 133, 4, 6, 137, 14, 143, 139, 141, 12, 8, 10},
2284 {30, 159, 145, 22, 18, 26, 153, 147, 157, 28, 16, 149, 155, 24, 20, 151}});
2285 }
2286
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew8_vlmul4)2287 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew8_vlmul4) {
2288 VlxsegXeiXX<UInt8, 1, 4>(
2289 0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2290 {{129, 0, 131, 2, 135, 133, 4, 6, 137, 14, 143, 139, 141, 12, 8, 10},
2291 {30, 159, 145, 22, 18, 26, 153, 147, 157, 28, 16, 149, 155, 24, 20, 151},
2292 {44, 50, 52, 34, 189, 38, 54, 171, 42, 191, 185, 40, 36, 46, 167, 175},
2293 {163, 169, 62, 187, 60, 179, 183, 181, 161, 32, 58, 177, 56, 165, 173, 48}});
2294 }
2295
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew8_vlmul8)2296 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew8_vlmul8) {
2297 VlxsegXeiXX<UInt8, 1, 8>(
2298 0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2299 {{129, 0, 131, 2, 135, 133, 4, 6, 137, 14, 143, 139, 141, 12, 8, 10},
2300 {30, 159, 145, 22, 18, 26, 153, 147, 157, 28, 16, 149, 155, 24, 20, 151},
2301 {44, 50, 52, 34, 189, 38, 54, 171, 42, 191, 185, 40, 36, 46, 167, 175},
2302 {163, 169, 62, 187, 60, 179, 183, 181, 161, 32, 58, 177, 56, 165, 173, 48},
2303 {124, 92, 78, 229, 114, 217, 203, 64, 98, 112, 239, 118, 249, 102, 201, 233},
2304 {237, 68, 231, 72, 110, 207, 247, 96, 251, 213, 90, 126, 66, 197, 120, 225},
2305 {241, 76, 100, 195, 253, 245, 193, 84, 104, 122, 199, 209, 227, 70, 219, 86},
2306 {243, 255, 205, 235, 74, 221, 80, 106, 215, 94, 211, 223, 116, 108, 82, 88}});
2307 }
2308
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew8_vlmul1)2309 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew8_vlmul1) {
2310 VlxsegXeiXX<UInt8, 2, 1>(
2311 0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2312 {{2, 0, 6, 4, 14, 10, 8, 12, 18, 28, 30, 22, 26, 24, 16, 20},
2313 {131, 129, 135, 133, 143, 139, 137, 141, 147, 157, 159, 151, 155, 153, 145, 149}});
2314 }
2315
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew8_vlmul2)2316 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew8_vlmul2) {
2317 VlxsegXeiXX<UInt8, 2, 2>(
2318 0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2319 {{2, 0, 6, 4, 14, 10, 8, 12, 18, 28, 30, 22, 26, 24, 16, 20},
2320 {60, 62, 34, 44, 36, 52, 50, 38, 58, 56, 32, 42, 54, 48, 40, 46},
2321 {131, 129, 135, 133, 143, 139, 137, 141, 147, 157, 159, 151, 155, 153, 145, 149},
2322 {189, 191, 163, 173, 165, 181, 179, 167, 187, 185, 161, 171, 183, 177, 169, 175}});
2323 }
2324
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew8_vlmul4)2325 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew8_vlmul4) {
2326 VlxsegXeiXX<UInt8, 2, 4>(
2327 0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2328 {{2, 0, 6, 4, 14, 10, 8, 12, 18, 28, 30, 22, 26, 24, 16, 20},
2329 {60, 62, 34, 44, 36, 52, 50, 38, 58, 56, 32, 42, 54, 48, 40, 46},
2330 {88, 100, 104, 68, 122, 76, 108, 86, 84, 126, 114, 80, 72, 92, 78, 94},
2331 {70, 82, 124, 118, 120, 102, 110, 106, 66, 64, 116, 98, 112, 74, 90, 96},
2332 {131, 129, 135, 133, 143, 139, 137, 141, 147, 157, 159, 151, 155, 153, 145, 149},
2333 {189, 191, 163, 173, 165, 181, 179, 167, 187, 185, 161, 171, 183, 177, 169, 175},
2334 {217, 229, 233, 197, 251, 205, 237, 215, 213, 255, 243, 209, 201, 221, 207, 223},
2335 {199, 211, 253, 247, 249, 231, 239, 235, 195, 193, 245, 227, 241, 203, 219, 225}});
2336 }
2337
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew8_vlmul1)2338 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew8_vlmul1) {
2339 VlxsegXeiXX<UInt8, 3, 1>(
2340 0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2341 {{131, 0, 137, 6, 149, 143, 12, 18, 155, 42, 173, 161, 167, 36, 24, 30},
2342 {4, 129, 10, 135, 22, 16, 141, 147, 28, 171, 46, 34, 40, 165, 153, 159},
2343 {133, 2, 139, 8, 151, 145, 14, 20, 157, 44, 175, 163, 169, 38, 26, 32}});
2344 }
2345
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew8_vlmul2)2346 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew8_vlmul2) {
2347 VlxsegXeiXX<UInt8, 3, 2>(
2348 0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2349 {{131, 0, 137, 6, 149, 143, 12, 18, 155, 42, 173, 161, 167, 36, 24, 30},
2350 {90, 221, 179, 66, 54, 78, 203, 185, 215, 84, 48, 191, 209, 72, 60, 197},
2351 {4, 129, 10, 135, 22, 16, 141, 147, 28, 171, 46, 34, 40, 165, 153, 159},
2352 {219, 94, 52, 195, 183, 207, 76, 58, 88, 213, 177, 64, 82, 201, 189, 70},
2353 {133, 2, 139, 8, 151, 145, 14, 20, 157, 44, 175, 163, 169, 38, 26, 32},
2354 {92, 223, 181, 68, 56, 80, 205, 187, 217, 86, 50, 193, 211, 74, 62, 199}});
2355 }
2356
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew8_vlmul1)2357 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew8_vlmul1) {
2358 VlxsegXeiXX<UInt8, 4, 1>(
2359 0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2360 {{4, 0, 12, 8, 28, 20, 16, 24, 36, 56, 60, 44, 52, 48, 32, 40},
2361 {133, 129, 141, 137, 157, 149, 145, 153, 165, 185, 189, 173, 181, 177, 161, 169},
2362 {6, 2, 14, 10, 30, 22, 18, 26, 38, 58, 62, 46, 54, 50, 34, 42},
2363 {135, 131, 143, 139, 159, 151, 147, 155, 167, 187, 191, 175, 183, 179, 163, 171}});
2364 }
2365
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew4_vlmul2)2366 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew4_vlmul2) {
2367 VlxsegXeiXX<UInt8, 4, 2>(
2368 0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2369 {{4, 0, 12, 8, 28, 20, 16, 24, 36, 56, 60, 44, 52, 48, 32, 40},
2370 {120, 124, 68, 88, 72, 104, 100, 76, 116, 112, 64, 84, 108, 96, 80, 92},
2371 {133, 129, 141, 137, 157, 149, 145, 153, 165, 185, 189, 173, 181, 177, 161, 169},
2372 {249, 253, 197, 217, 201, 233, 229, 205, 245, 241, 193, 213, 237, 225, 209, 221},
2373 {6, 2, 14, 10, 30, 22, 18, 26, 38, 58, 62, 46, 54, 50, 34, 42},
2374 {122, 126, 70, 90, 74, 106, 102, 78, 118, 114, 66, 86, 110, 98, 82, 94},
2375 {135, 131, 143, 139, 159, 151, 147, 155, 167, 187, 191, 175, 183, 179, 163, 171},
2376 {251, 255, 199, 219, 203, 235, 231, 207, 247, 243, 195, 215, 239, 227, 211, 223}});
2377 }
2378
TEST_F(Riscv64InterpreterTest,TestVlxseg5eiXX_sew8)2379 TEST_F(Riscv64InterpreterTest, TestVlxseg5eiXX_sew8) {
2380 VlxsegXeiXX<UInt8, 5, 1>(
2381 0x85008407, // Vluxseg5ei8.v v8, (x1), v16, v0.t
2382 {{133, 0, 143, 10, 163, 153, 20, 30, 173, 70, 203, 183, 193, 60, 40, 50},
2383 {6, 129, 16, 139, 36, 26, 149, 159, 46, 199, 76, 56, 66, 189, 169, 179},
2384 {135, 2, 145, 12, 165, 155, 22, 32, 175, 72, 205, 185, 195, 62, 42, 52},
2385 {8, 131, 18, 141, 38, 28, 151, 161, 48, 201, 78, 58, 68, 191, 171, 181},
2386 {137, 4, 147, 14, 167, 157, 24, 34, 177, 74, 207, 187, 197, 64, 44, 54}});
2387 }
2388
TEST_F(Riscv64InterpreterTest,TestVlxseg6eiXX_sew8)2389 TEST_F(Riscv64InterpreterTest, TestVlxseg6eiXX_sew8) {
2390 VlxsegXeiXX<UInt8, 6, 1>(
2391 0xa5008407, // Vluxseg6ei8.v v8, (x1), v16, v0.t
2392 {{6, 0, 18, 12, 42, 30, 24, 36, 54, 84, 90, 66, 78, 72, 48, 60},
2393 {135, 129, 147, 141, 171, 159, 153, 165, 183, 213, 219, 195, 207, 201, 177, 189},
2394 {8, 2, 20, 14, 44, 32, 26, 38, 56, 86, 92, 68, 80, 74, 50, 62},
2395 {137, 131, 149, 143, 173, 161, 155, 167, 185, 215, 221, 197, 209, 203, 179, 191},
2396 {10, 4, 22, 16, 46, 34, 28, 40, 58, 88, 94, 70, 82, 76, 52, 64},
2397 {139, 133, 151, 145, 175, 163, 157, 169, 187, 217, 223, 199, 211, 205, 181, 193}});
2398 }
2399
TEST_F(Riscv64InterpreterTest,TestVlxseg7eiXX_sew8)2400 TEST_F(Riscv64InterpreterTest, TestVlxseg7eiXX_sew8) {
2401 VlxsegXeiXX<UInt8, 7, 1>(
2402 0xc5008407, // Vluxseg7ei8.v v8, (x1), v16, v0.t
2403 {{135, 0, 149, 14, 177, 163, 28, 42, 191, 98, 233, 205, 219, 84, 56, 70},
2404 {8, 129, 22, 143, 50, 36, 157, 171, 64, 227, 106, 78, 92, 213, 185, 199},
2405 {137, 2, 151, 16, 179, 165, 30, 44, 193, 100, 235, 207, 221, 86, 58, 72},
2406 {10, 131, 24, 145, 52, 38, 159, 173, 66, 229, 108, 80, 94, 215, 187, 201},
2407 {139, 4, 153, 18, 181, 167, 32, 46, 195, 102, 237, 209, 223, 88, 60, 74},
2408 {12, 133, 26, 147, 54, 40, 161, 175, 68, 231, 110, 82, 96, 217, 189, 203},
2409 {141, 6, 155, 20, 183, 169, 34, 48, 197, 104, 239, 211, 225, 90, 62, 76}});
2410 }
2411
TEST_F(Riscv64InterpreterTest,TestVlxseg8eiXX_sew8)2412 TEST_F(Riscv64InterpreterTest, TestVlxseg8eiXX_sew8) {
2413 VlxsegXeiXX<UInt8, 8, 1>(
2414 0xe5008407, // Vluxseg8ei8.v v8, (x1), v16, v0.t
2415 {{8, 0, 24, 16, 56, 40, 32, 48, 72, 112, 120, 88, 104, 96, 64, 80},
2416 {137, 129, 153, 145, 185, 169, 161, 177, 201, 241, 249, 217, 233, 225, 193, 209},
2417 {10, 2, 26, 18, 58, 42, 34, 50, 74, 114, 122, 90, 106, 98, 66, 82},
2418 {139, 131, 155, 147, 187, 171, 163, 179, 203, 243, 251, 219, 235, 227, 195, 211},
2419 {12, 4, 28, 20, 60, 44, 36, 52, 76, 116, 124, 92, 108, 100, 68, 84},
2420 {141, 133, 157, 149, 189, 173, 165, 181, 205, 245, 253, 221, 237, 229, 197, 213},
2421 {14, 6, 30, 22, 62, 46, 38, 54, 78, 118, 126, 94, 110, 102, 70, 86},
2422 {143, 135, 159, 151, 191, 175, 167, 183, 207, 247, 255, 223, 239, 231, 199, 215}});
2423 }
2424
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew16_vlmul1)2425 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew16_vlmul1) {
2426 VlxsegXeiXX<UInt16, 1, 1>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2427 {{0x8302, 0x8100, 0x8706, 0x8504, 0x8f0e, 0x8b0a, 0x8908, 0x8d0c}});
2428 }
2429
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew16_vlmul2)2430 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew16_vlmul2) {
2431 VlxsegXeiXX<UInt16, 1, 2>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2432 {{0x8302, 0x8100, 0x8706, 0x8504, 0x8f0e, 0x8b0a, 0x8908, 0x8d0c},
2433 {0x9312, 0x9d1c, 0x9f1e, 0x9716, 0x9b1a, 0x9918, 0x9110, 0x9514}});
2434 }
2435
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew16_vlmul4)2436 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew16_vlmul4) {
2437 VlxsegXeiXX<UInt16, 1, 4>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2438 {{0x8302, 0x8100, 0x8706, 0x8504, 0x8f0e, 0x8b0a, 0x8908, 0x8d0c},
2439 {0x9312, 0x9d1c, 0x9f1e, 0x9716, 0x9b1a, 0x9918, 0x9110, 0x9514},
2440 {0xbd3c, 0xbf3e, 0xa322, 0xad2c, 0xa524, 0xb534, 0xb332, 0xa726},
2441 {0xbb3a, 0xb938, 0xa120, 0xab2a, 0xb736, 0xb130, 0xa928, 0xaf2e}});
2442 }
2443
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew16_vlmul8)2444 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew16_vlmul8) {
2445 VlxsegXeiXX<UInt16, 1, 8>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2446 {{0x8302, 0x8100, 0x8706, 0x8504, 0x8f0e, 0x8b0a, 0x8908, 0x8d0c},
2447 {0x9312, 0x9d1c, 0x9f1e, 0x9716, 0x9b1a, 0x9918, 0x9110, 0x9514},
2448 {0xbd3c, 0xbf3e, 0xa322, 0xad2c, 0xa524, 0xb534, 0xb332, 0xa726},
2449 {0xbb3a, 0xb938, 0xa120, 0xab2a, 0xb736, 0xb130, 0xa928, 0xaf2e},
2450 {0xd958, 0xe564, 0xe968, 0xc544, 0xfb7a, 0xcd4c, 0xed6c, 0xd756},
2451 {0xd554, 0xff7e, 0xf372, 0xd150, 0xc948, 0xdd5c, 0xcf4e, 0xdf5e},
2452 {0xc746, 0xd352, 0xfd7c, 0xf776, 0xf978, 0xe766, 0xef6e, 0xeb6a},
2453 {0xc342, 0xc140, 0xf574, 0xe362, 0xf170, 0xcb4a, 0xdb5a, 0xe160}});
2454 }
2455
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew16_vlmul1)2456 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew16_vlmul1) {
2457 VlxsegXeiXX<UInt16, 2, 1>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2458 {{0x8504, 0x8100, 0x8d0c, 0x8908, 0x9d1c, 0x9514, 0x9110, 0x9918},
2459 {0x8706, 0x8302, 0x8f0e, 0x8b0a, 0x9f1e, 0x9716, 0x9312, 0x9b1a}});
2460 }
2461
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew16_vlmul2)2462 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew16_vlmul2) {
2463 VlxsegXeiXX<UInt16, 2, 2>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2464 {{0x8504, 0x8100, 0x8d0c, 0x8908, 0x9d1c, 0x9514, 0x9110, 0x9918},
2465 {0xa524, 0xb938, 0xbd3c, 0xad2c, 0xb534, 0xb130, 0xa120, 0xa928},
2466 {0x8706, 0x8302, 0x8f0e, 0x8b0a, 0x9f1e, 0x9716, 0x9312, 0x9b1a},
2467 {0xa726, 0xbb3a, 0xbf3e, 0xaf2e, 0xb736, 0xb332, 0xa322, 0xab2a}});
2468 }
2469
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew16_vlmul4)2470 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew16_vlmul4) {
2471 VlxsegXeiXX<UInt16, 2, 4>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2472 {{0x8504, 0x8100, 0x8d0c, 0x8908, 0x9d1c, 0x9514, 0x9110, 0x9918},
2473 {0xa524, 0xb938, 0xbd3c, 0xad2c, 0xb534, 0xb130, 0xa120, 0xa928},
2474 {0xf978, 0xfd7c, 0xc544, 0xd958, 0xc948, 0xe968, 0xe564, 0xcd4c},
2475 {0xf574, 0xf170, 0xc140, 0xd554, 0xed6c, 0xe160, 0xd150, 0xdd5c},
2476 {0x8706, 0x8302, 0x8f0e, 0x8b0a, 0x9f1e, 0x9716, 0x9312, 0x9b1a},
2477 {0xa726, 0xbb3a, 0xbf3e, 0xaf2e, 0xb736, 0xb332, 0xa322, 0xab2a},
2478 {0xfb7a, 0xff7e, 0xc746, 0xdb5a, 0xcb4a, 0xeb6a, 0xe766, 0xcf4e},
2479 {0xf776, 0xf372, 0xc342, 0xd756, 0xef6e, 0xe362, 0xd352, 0xdf5e}});
2480 }
2481
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew16_vlmul1)2482 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew16_vlmul1) {
2483 VlxsegXeiXX<UInt16, 3, 1>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2484 {{0x8706, 0x8100, 0x9312, 0x8d0c, 0xab2a, 0x9f1e, 0x9918, 0xa524},
2485 {0x8908, 0x8302, 0x9514, 0x8f0e, 0xad2c, 0xa120, 0x9b1a, 0xa726},
2486 {0x8b0a, 0x8504, 0x9716, 0x9110, 0xaf2e, 0xa322, 0x9d1c, 0xa928}});
2487 }
2488
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew16_vlmul2)2489 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew16_vlmul2) {
2490 VlxsegXeiXX<UInt16, 3, 2>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2491 {{0x8706, 0x8100, 0x9312, 0x8d0c, 0xab2a, 0x9f1e, 0x9918, 0xa524},
2492 {0xb736, 0xd554, 0xdb5a, 0xc342, 0xcf4e, 0xc948, 0xb130, 0xbd3c},
2493 {0x8908, 0x8302, 0x9514, 0x8f0e, 0xad2c, 0xa120, 0x9b1a, 0xa726},
2494 {0xb938, 0xd756, 0xdd5c, 0xc544, 0xd150, 0xcb4a, 0xb332, 0xbf3e},
2495 {0x8b0a, 0x8504, 0x9716, 0x9110, 0xaf2e, 0xa322, 0x9d1c, 0xa928},
2496 {0xbb3a, 0xd958, 0xdf5e, 0xc746, 0xd352, 0xcd4c, 0xb534, 0xc140}});
2497 }
2498
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew16_vlmul1)2499 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew16_vlmul1) {
2500 VlxsegXeiXX<UInt16, 4, 1>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2501 {{0x8908, 0x8100, 0x9918, 0x9110, 0xb938, 0xa928, 0xa120, 0xb130},
2502 {0x8b0a, 0x8302, 0x9b1a, 0x9312, 0xbb3a, 0xab2a, 0xa322, 0xb332},
2503 {0x8d0c, 0x8504, 0x9d1c, 0x9514, 0xbd3c, 0xad2c, 0xa524, 0xb534},
2504 {0x8f0e, 0x8706, 0x9f1e, 0x9716, 0xbf3e, 0xaf2e, 0xa726, 0xb736}});
2505 }
2506
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew16_vlmul2)2507 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew16_vlmul2) {
2508 VlxsegXeiXX<UInt16, 4, 2>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2509 {{0x8908, 0x8100, 0x9918, 0x9110, 0xb938, 0xa928, 0xa120, 0xb130},
2510 {0xc948, 0xf170, 0xf978, 0xd958, 0xe968, 0xe160, 0xc140, 0xd150},
2511 {0x8b0a, 0x8302, 0x9b1a, 0x9312, 0xbb3a, 0xab2a, 0xa322, 0xb332},
2512 {0xcb4a, 0xf372, 0xfb7a, 0xdb5a, 0xeb6a, 0xe362, 0xc342, 0xd352},
2513 {0x8d0c, 0x8504, 0x9d1c, 0x9514, 0xbd3c, 0xad2c, 0xa524, 0xb534},
2514 {0xcd4c, 0xf574, 0xfd7c, 0xdd5c, 0xed6c, 0xe564, 0xc544, 0xd554},
2515 {0x8f0e, 0x8706, 0x9f1e, 0x9716, 0xbf3e, 0xaf2e, 0xa726, 0xb736},
2516 {0xcf4e, 0xf776, 0xff7e, 0xdf5e, 0xef6e, 0xe766, 0xc746, 0xd756}});
2517 }
2518
TEST_F(Riscv64InterpreterTest,TestVlxseg5eiXX_sew16)2519 TEST_F(Riscv64InterpreterTest, TestVlxseg5eiXX_sew16) {
2520 VlxsegXeiXX<UInt16, 5, 1>(0x85008407, // Vluxseg5ei8.v v8, (x1), v16, v0.t
2521 {{0x8b0a, 0x8100, 0x9f1e, 0x9514, 0xc746, 0xb332, 0xa928, 0xbd3c},
2522 {0x8d0c, 0x8302, 0xa120, 0x9716, 0xc948, 0xb534, 0xab2a, 0xbf3e},
2523 {0x8f0e, 0x8504, 0xa322, 0x9918, 0xcb4a, 0xb736, 0xad2c, 0xc140},
2524 {0x9110, 0x8706, 0xa524, 0x9b1a, 0xcd4c, 0xb938, 0xaf2e, 0xc342},
2525 {0x9312, 0x8908, 0xa726, 0x9d1c, 0xcf4e, 0xbb3a, 0xb130, 0xc544}});
2526 }
2527
TEST_F(Riscv64InterpreterTest,TestVlxseg6eiXX_sew16)2528 TEST_F(Riscv64InterpreterTest, TestVlxseg6eiXX_sew16) {
2529 VlxsegXeiXX<UInt16, 6, 1>(0xa5008407, // Vluxseg6ei8.v v8, (x1), v16, v0.t
2530 {{0x8d0c, 0x8100, 0xa524, 0x9918, 0xd554, 0xbd3c, 0xb130, 0xc948},
2531 {0x8f0e, 0x8302, 0xa726, 0x9b1a, 0xd756, 0xbf3e, 0xb332, 0xcb4a},
2532 {0x9110, 0x8504, 0xa928, 0x9d1c, 0xd958, 0xc140, 0xb534, 0xcd4c},
2533 {0x9312, 0x8706, 0xab2a, 0x9f1e, 0xdb5a, 0xc342, 0xb736, 0xcf4e},
2534 {0x9514, 0x8908, 0xad2c, 0xa120, 0xdd5c, 0xc544, 0xb938, 0xd150},
2535 {0x9716, 0x8b0a, 0xaf2e, 0xa322, 0xdf5e, 0xc746, 0xbb3a, 0xd352}});
2536 }
2537
TEST_F(Riscv64InterpreterTest,TestVlxseg7eiXX_sew16)2538 TEST_F(Riscv64InterpreterTest, TestVlxseg7eiXX_sew16) {
2539 VlxsegXeiXX<UInt16, 7, 1>(0xc5008407, // Vluxseg7ei8.v v8, (x1), v16, v0.t
2540 {{0x8f0e, 0x8100, 0xab2a, 0x9d1c, 0xe362, 0xc746, 0xb938, 0xd554},
2541 {0x9110, 0x8302, 0xad2c, 0x9f1e, 0xe564, 0xc948, 0xbb3a, 0xd756},
2542 {0x9312, 0x8504, 0xaf2e, 0xa120, 0xe766, 0xcb4a, 0xbd3c, 0xd958},
2543 {0x9514, 0x8706, 0xb130, 0xa322, 0xe968, 0xcd4c, 0xbf3e, 0xdb5a},
2544 {0x9716, 0x8908, 0xb332, 0xa524, 0xeb6a, 0xcf4e, 0xc140, 0xdd5c},
2545 {0x9918, 0x8b0a, 0xb534, 0xa726, 0xed6c, 0xd150, 0xc342, 0xdf5e},
2546 {0x9b1a, 0x8d0c, 0xb736, 0xa928, 0xef6e, 0xd352, 0xc544, 0xe160}});
2547 }
2548
TEST_F(Riscv64InterpreterTest,TestVlxseg8eiXX_sew16)2549 TEST_F(Riscv64InterpreterTest, TestVlxseg8eiXX_sew16) {
2550 VlxsegXeiXX<UInt16, 8, 1>(0xe5008407, // Vluxseg8ei8.v v8, (x1), v16, v0.t
2551 {{0x9110, 0x8100, 0xb130, 0xa120, 0xf170, 0xd150, 0xc140, 0xe160},
2552 {0x9312, 0x8302, 0xb332, 0xa322, 0xf372, 0xd352, 0xc342, 0xe362},
2553 {0x9514, 0x8504, 0xb534, 0xa524, 0xf574, 0xd554, 0xc544, 0xe564},
2554 {0x9716, 0x8706, 0xb736, 0xa726, 0xf776, 0xd756, 0xc746, 0xe766},
2555 {0x9918, 0x8908, 0xb938, 0xa928, 0xf978, 0xd958, 0xc948, 0xe968},
2556 {0x9b1a, 0x8b0a, 0xbb3a, 0xab2a, 0xfb7a, 0xdb5a, 0xcb4a, 0xeb6a},
2557 {0x9d1c, 0x8d0c, 0xbd3c, 0xad2c, 0xfd7c, 0xdd5c, 0xcd4c, 0xed6c},
2558 {0x9f1e, 0x8f0e, 0xbf3e, 0xaf2e, 0xff7e, 0xdf5e, 0xcf4e, 0xef6e}});
2559 }
2560
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew32_vlmul1)2561 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew32_vlmul1) {
2562 VlxsegXeiXX<UInt32, 1, 1>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2563 {{0x8706'8504, 0x8302'8100, 0x8f0e'8d0c, 0x8b0a'8908}});
2564 }
2565
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew32_vlmul2)2566 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew32_vlmul2) {
2567 VlxsegXeiXX<UInt32, 1, 2>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2568 {{0x8706'8504, 0x8302'8100, 0x8f0e'8d0c, 0x8b0a'8908},
2569 {0x9f1e'9d1c, 0x9716'9514, 0x9312'9110, 0x9b1a'9918}});
2570 }
2571
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew32_vlmul4)2572 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew32_vlmul4) {
2573 VlxsegXeiXX<UInt32, 1, 4>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2574 {{0x8706'8504, 0x8302'8100, 0x8f0e'8d0c, 0x8b0a'8908},
2575 {0x9f1e'9d1c, 0x9716'9514, 0x9312'9110, 0x9b1a'9918},
2576 {0xa726'a524, 0xbb3a'b938, 0xbf3e'bd3c, 0xaf2e'ad2c},
2577 {0xb736'b534, 0xb332'b130, 0xa322'a120, 0xab2a'a928}});
2578 }
2579
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew32_vlmul8)2580 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew32_vlmul8) {
2581 VlxsegXeiXX<UInt32, 1, 8>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2582 {{0x8706'8504, 0x8302'8100, 0x8f0e'8d0c, 0x8b0a'8908},
2583 {0x9f1e'9d1c, 0x9716'9514, 0x9312'9110, 0x9b1a'9918},
2584 {0xa726'a524, 0xbb3a'b938, 0xbf3e'bd3c, 0xaf2e'ad2c},
2585 {0xb736'b534, 0xb332'b130, 0xa322'a120, 0xab2a'a928},
2586 {0xfb7a'f978, 0xff7e'fd7c, 0xc746'c544, 0xdb5a'd958},
2587 {0xcb4a'c948, 0xeb6a'e968, 0xe766'e564, 0xcf4e'cd4c},
2588 {0xf776'f574, 0xf372'f170, 0xc342'c140, 0xd756'd554},
2589 {0xef6e'ed6c, 0xe362'e160, 0xd352'd150, 0xdf5e'dd5c}});
2590 }
2591
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew32_vlmul1)2592 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew32_vlmul1) {
2593 VlxsegXeiXX<UInt32, 2, 1>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2594 {{0x8b0a'8908, 0x8302'8100, 0x9b1a'9918, 0x9312'9110},
2595 {0x8f0e'8d0c, 0x8706'8504, 0x9f1e'9d1c, 0x9716'9514}});
2596 }
2597
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew32_vlmul2)2598 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew32_vlmul2) {
2599 VlxsegXeiXX<UInt32, 2, 2>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2600 {{0x8b0a'8908, 0x8302'8100, 0x9b1a'9918, 0x9312'9110},
2601 {0xbb3a'b938, 0xab2a'a928, 0xa322'a120, 0xb332'b130},
2602 {0x8f0e'8d0c, 0x8706'8504, 0x9f1e'9d1c, 0x9716'9514},
2603 {0xbf3e'bd3c, 0xaf2e'ad2c, 0xa726'a524, 0xb736'b534}});
2604 }
2605
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew32_vlmul4)2606 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew32_vlmul4) {
2607 VlxsegXeiXX<UInt32, 2, 4>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2608 {{0x8b0a'8908, 0x8302'8100, 0x9b1a'9918, 0x9312'9110},
2609 {0xbb3a'b938, 0xab2a'a928, 0xa322'a120, 0xb332'b130},
2610 {0xcb4a'c948, 0xf372'f170, 0xfb7a'f978, 0xdb5a'd958},
2611 {0xeb6a'e968, 0xe362'e160, 0xc342'c140, 0xd352'd150},
2612 {0x8f0e'8d0c, 0x8706'8504, 0x9f1e'9d1c, 0x9716'9514},
2613 {0xbf3e'bd3c, 0xaf2e'ad2c, 0xa726'a524, 0xb736'b534},
2614 {0xcf4e'cd4c, 0xf776'f574, 0xff7e'fd7c, 0xdf5e'dd5c},
2615 {0xef6e'ed6c, 0xe766'e564, 0xc746'c544, 0xd756'd554}});
2616 }
2617
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew32_vlmul1)2618 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew32_vlmul1) {
2619 VlxsegXeiXX<UInt32, 3, 1>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2620 {{0x8f0e'8d0c, 0x8302'8100, 0xa726'a524, 0x9b1a'9918},
2621 {0x9312'9110, 0x8706'8504, 0xab2a'a928, 0x9f1e'9d1c},
2622 {0x9716'9514, 0x8b0a'8908, 0xaf2e'ad2c, 0xa322'a120}});
2623 }
2624
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew32_vlmul2)2625 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew32_vlmul2) {
2626 VlxsegXeiXX<UInt32, 3, 2>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2627 {{0x8f0e'8d0c, 0x8302'8100, 0xa726'a524, 0x9b1a'9918},
2628 {0xd756'd554, 0xbf3e'bd3c, 0xb332'b130, 0xcb4a'c948},
2629 {0x9312'9110, 0x8706'8504, 0xab2a'a928, 0x9f1e'9d1c},
2630 {0xdb5a'd958, 0xc342'c140, 0xb736'b534, 0xcf4e'cd4c},
2631 {0x9716'9514, 0x8b0a'8908, 0xaf2e'ad2c, 0xa322'a120},
2632 {0xdf5e'dd5c, 0xc746'c544, 0xbb3a'b938, 0xd352'd150}});
2633 }
2634
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew32_vlmul1)2635 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew32_vlmul1) {
2636 VlxsegXeiXX<UInt32, 4, 1>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2637 {{0x9312'9110, 0x8302'8100, 0xb332'b130, 0xa322'a120},
2638 {0x9716'9514, 0x8706'8504, 0xb736'b534, 0xa726'a524},
2639 {0x9b1a'9918, 0x8b0a'8908, 0xbb3a'b938, 0xab2a'a928},
2640 {0x9f1e'9d1c, 0x8f0e'8d0c, 0xbf3e'bd3c, 0xaf2e'ad2c}});
2641 }
2642
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew32_vlmul2)2643 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew32_vlmul2) {
2644 VlxsegXeiXX<UInt32, 4, 2>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2645 {{0x9312'9110, 0x8302'8100, 0xb332'b130, 0xa322'a120},
2646 {0xf372'f170, 0xd352'd150, 0xc342'c140, 0xe362'e160},
2647 {0x9716'9514, 0x8706'8504, 0xb736'b534, 0xa726'a524},
2648 {0xf776'f574, 0xd756'd554, 0xc746'c544, 0xe766'e564},
2649 {0x9b1a'9918, 0x8b0a'8908, 0xbb3a'b938, 0xab2a'a928},
2650 {0xfb7a'f978, 0xdb5a'd958, 0xcb4a'c948, 0xeb6a'e968},
2651 {0x9f1e'9d1c, 0x8f0e'8d0c, 0xbf3e'bd3c, 0xaf2e'ad2c},
2652 {0xff7e'fd7c, 0xdf5e'dd5c, 0xcf4e'cd4c, 0xef6e'ed6c}});
2653 }
2654
TEST_F(Riscv64InterpreterTest,TestVlxseg5eiXX_sew32)2655 TEST_F(Riscv64InterpreterTest, TestVlxseg5eiXX_sew32) {
2656 VlxsegXeiXX<UInt32, 5, 1>(0x85008407, // Vluxseg5ei8.v v8, (x1), v16, v0.t
2657 {{0x9716'9514, 0x8302'8100, 0xbf3e'bd3c, 0xab2a'a928},
2658 {0x9b1a'9918, 0x8706'8504, 0xc342'c140, 0xaf2e'ad2c},
2659 {0x9f1e'9d1c, 0x8b0a'8908, 0xc746'c544, 0xb332'b130},
2660 {0xa322'a120, 0x8f0e'8d0c, 0xcb4a'c948, 0xb736'b534},
2661 {0xa726'a524, 0x9312'9110, 0xcf4e'cd4c, 0xbb3a'b938}});
2662 }
2663
TEST_F(Riscv64InterpreterTest,TestVlxseg6eiXX_sew32)2664 TEST_F(Riscv64InterpreterTest, TestVlxseg6eiXX_sew32) {
2665 VlxsegXeiXX<UInt32, 6, 1>(0xa5008407, // Vluxseg6ei8.v v8, (x1), v16, v0.t
2666 {{0x9b1a'9918, 0x8302'8100, 0xcb4a'c948, 0xb332'b130},
2667 {0x9f1e'9d1c, 0x8706'8504, 0xcf4e'cd4c, 0xb736'b534},
2668 {0xa322'a120, 0x8b0a'8908, 0xd352'd150, 0xbb3a'b938},
2669 {0xa726'a524, 0x8f0e'8d0c, 0xd756'd554, 0xbf3e'bd3c},
2670 {0xab2a'a928, 0x9312'9110, 0xdb5a'd958, 0xc342'c140},
2671 {0xaf2e'ad2c, 0x9716'9514, 0xdf5e'dd5c, 0xc746'c544}});
2672 }
2673
TEST_F(Riscv64InterpreterTest,TestVlxseg7eiXX_sew32)2674 TEST_F(Riscv64InterpreterTest, TestVlxseg7eiXX_sew32) {
2675 VlxsegXeiXX<UInt32, 7, 1>(0xc5008407, // Vluxseg7ei8.v v8, (x1), v16, v0.t
2676 {{0x9f1e'9d1c, 0x8302'8100, 0xd756'd554, 0xbb3a'b938},
2677 {0xa322'a120, 0x8706'8504, 0xdb5a'd958, 0xbf3e'bd3c},
2678 {0xa726'a524, 0x8b0a'8908, 0xdf5e'dd5c, 0xc342'c140},
2679 {0xab2a'a928, 0x8f0e'8d0c, 0xe362'e160, 0xc746'c544},
2680 {0xaf2e'ad2c, 0x9312'9110, 0xe766'e564, 0xcb4a'c948},
2681 {0xb332'b130, 0x9716'9514, 0xeb6a'e968, 0xcf4e'cd4c},
2682 {0xb736'b534, 0x9b1a'9918, 0xef6e'ed6c, 0xd352'd150}});
2683 }
2684
TEST_F(Riscv64InterpreterTest,TestVlxseg8eiXX_sew32)2685 TEST_F(Riscv64InterpreterTest, TestVlxseg8eiXX_sew32) {
2686 VlxsegXeiXX<UInt32, 8, 1>(0xe5008407, // Vluxseg8ei8.v v8, (x1), v16, v0.t
2687 {{0xa322'a120, 0x8302'8100, 0xe362'e160, 0xc342'c140},
2688 {0xa726'a524, 0x8706'8504, 0xe766'e564, 0xc746'c544},
2689 {0xab2a'a928, 0x8b0a'8908, 0xeb6a'e968, 0xcb4a'c948},
2690 {0xaf2e'ad2c, 0x8f0e'8d0c, 0xef6e'ed6c, 0xcf4e'cd4c},
2691 {0xb332'b130, 0x9312'9110, 0xf372'f170, 0xd352'd150},
2692 {0xb736'b534, 0x9716'9514, 0xf776'f574, 0xd756'd554},
2693 {0xbb3a'b938, 0x9b1a'9918, 0xfb7a'f978, 0xdb5a'd958},
2694 {0xbf3e'bd3c, 0x9f1e'9d1c, 0xff7e'fd7c, 0xdf5e'dd5c}});
2695 }
2696
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew64_vlmul1)2697 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew64_vlmul1) {
2698 VlxsegXeiXX<UInt64, 1, 1>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2699 {{0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100}});
2700 }
2701
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew64_vlmul2)2702 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew64_vlmul2) {
2703 VlxsegXeiXX<UInt64, 1, 2>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2704 {{0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100},
2705 {0x9f1e'9d1c'9b1a'9918, 0x9716'9514'9312'9110}});
2706 }
2707
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew64_vlmul4)2708 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew64_vlmul4) {
2709 VlxsegXeiXX<UInt64, 1, 4>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2710 {{0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100},
2711 {0x9f1e'9d1c'9b1a'9918, 0x9716'9514'9312'9110},
2712 {0xbf3e'bd3c'bb3a'b938, 0xaf2e'ad2c'ab2a'a928},
2713 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130}});
2714 }
2715
TEST_F(Riscv64InterpreterTest,TestVlxeiXX_sew64_vlmul8)2716 TEST_F(Riscv64InterpreterTest, TestVlxeiXX_sew64_vlmul8) {
2717 VlxsegXeiXX<UInt64, 1, 8>(0x05008407, // Vluxei8.v v8, (x1), v16, v0.t
2718 {{0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100},
2719 {0x9f1e'9d1c'9b1a'9918, 0x9716'9514'9312'9110},
2720 {0xbf3e'bd3c'bb3a'b938, 0xaf2e'ad2c'ab2a'a928},
2721 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130},
2722 {0xcf4e'cd4c'cb4a'c948, 0xf776'f574'f372'f170},
2723 {0xff7e'fd7c'fb7a'f978, 0xdf5e'dd5c'db5a'd958},
2724 {0xef6e'ed6c'eb6a'e968, 0xe766'e564'e362'e160},
2725 {0xc746'c544'c342'c140, 0xd756'd554'd352'd150}});
2726 }
2727
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew64_vlmul1)2728 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew64_vlmul1) {
2729 VlxsegXeiXX<UInt64, 2, 1>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2730 {{0x9716'9514'9312'9110, 0x8706'8504'8302'8100},
2731 {0x9f1e'9d1c'9b1a'9918, 0x8f0e'8d0c'8b0a'8908}});
2732 }
2733
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew64_vlmul2)2734 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew64_vlmul2) {
2735 VlxsegXeiXX<UInt64, 2, 2>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2736 {{0x9716'9514'9312'9110, 0x8706'8504'8302'8100},
2737 {0xb736'b534'b332'b130, 0xa726'a524'a322'a120},
2738 {0x9f1e'9d1c'9b1a'9918, 0x8f0e'8d0c'8b0a'8908},
2739 {0xbf3e'bd3c'bb3a'b938, 0xaf2e'ad2c'ab2a'a928}});
2740 }
2741
TEST_F(Riscv64InterpreterTest,TestVlxseg2eiXX_sew64_vlmul4)2742 TEST_F(Riscv64InterpreterTest, TestVlxseg2eiXX_sew64_vlmul4) {
2743 VlxsegXeiXX<UInt64, 2, 4>(0x25008407, // Vluxseg2ei8.v v8, (x1), v16, v0.t
2744 {{0x9716'9514'9312'9110, 0x8706'8504'8302'8100},
2745 {0xb736'b534'b332'b130, 0xa726'a524'a322'a120},
2746 {0xf776'f574'f372'f170, 0xd756'd554'd352'd150},
2747 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
2748 {0x9f1e'9d1c'9b1a'9918, 0x8f0e'8d0c'8b0a'8908},
2749 {0xbf3e'bd3c'bb3a'b938, 0xaf2e'ad2c'ab2a'a928},
2750 {0xff7e'fd7c'fb7a'f978, 0xdf5e'dd5c'db5a'd958},
2751 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968}});
2752 }
2753
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew64_vlmul1)2754 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew64_vlmul1) {
2755 VlxsegXeiXX<UInt64, 3, 1>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2756 {{0x9f1e'9d1c'9b1a'9918, 0x8706'8504'8302'8100},
2757 {0xa726'a524'a322'a120, 0x8f0e'8d0c'8b0a'8908},
2758 {0xaf2e'ad2c'ab2a'a928, 0x9716'9514'9312'9110}});
2759 }
2760
TEST_F(Riscv64InterpreterTest,TestVlxseg3eiXX_sew64_vlmul2)2761 TEST_F(Riscv64InterpreterTest, TestVlxseg3eiXX_sew64_vlmul2) {
2762 VlxsegXeiXX<UInt64, 3, 2>(0x45008407, // Vluxseg3ei8.v v8, (x1), v16, v0.t
2763 {{0x9f1e'9d1c'9b1a'9918, 0x8706'8504'8302'8100},
2764 {0xcf4e'cd4c'cb4a'c948, 0xb736'b534'b332'b130},
2765 {0xa726'a524'a322'a120, 0x8f0e'8d0c'8b0a'8908},
2766 {0xd756'd554'd352'd150, 0xbf3e'bd3c'bb3a'b938},
2767 {0xaf2e'ad2c'ab2a'a928, 0x9716'9514'9312'9110},
2768 {0xdf5e'dd5c'db5a'd958, 0xc746'c544'c342'c140}});
2769 }
2770
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew64_vlmul1)2771 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew64_vlmul1) {
2772 VlxsegXeiXX<UInt64, 4, 1>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2773 {{0xa726'a524'a322'a120, 0x8706'8504'8302'8100},
2774 {0xaf2e'ad2c'ab2a'a928, 0x8f0e'8d0c'8b0a'8908},
2775 {0xb736'b534'b332'b130, 0x9716'9514'9312'9110},
2776 {0xbf3e'bd3c'bb3a'b938, 0x9f1e'9d1c'9b1a'9918}});
2777 }
2778
TEST_F(Riscv64InterpreterTest,TestVlxseg4eiXX_sew64_vlmul2)2779 TEST_F(Riscv64InterpreterTest, TestVlxseg4eiXX_sew64_vlmul2) {
2780 VlxsegXeiXX<UInt64, 4, 2>(0x65008407, // Vluxseg4ei8.v v8, (x1), v16, v0.t
2781 {{0xa726'a524'a322'a120, 0x8706'8504'8302'8100},
2782 {0xe766'e564'e362'e160, 0xc746'c544'c342'c140},
2783 {0xaf2e'ad2c'ab2a'a928, 0x8f0e'8d0c'8b0a'8908},
2784 {0xef6e'ed6c'eb6a'e968, 0xcf4e'cd4c'cb4a'c948},
2785 {0xb736'b534'b332'b130, 0x9716'9514'9312'9110},
2786 {0xf776'f574'f372'f170, 0xd756'd554'd352'd150},
2787 {0xbf3e'bd3c'bb3a'b938, 0x9f1e'9d1c'9b1a'9918},
2788 {0xff7e'fd7c'fb7a'f978, 0xdf5e'dd5c'db5a'd958}});
2789 }
2790
TEST_F(Riscv64InterpreterTest,TestVlxseg5eiXX_sew64)2791 TEST_F(Riscv64InterpreterTest, TestVlxseg5eiXX_sew64) {
2792 VlxsegXeiXX<UInt64, 5, 1>(0x85008407, // Vluxseg5ei8.v v8, (x1), v16, v0.t
2793 {{0xaf2e'ad2c'ab2a'a928, 0x8706'8504'8302'8100},
2794 {0xb736'b534'b332'b130, 0x8f0e'8d0c'8b0a'8908},
2795 {0xbf3e'bd3c'bb3a'b938, 0x9716'9514'9312'9110},
2796 {0xc746'c544'c342'c140, 0x9f1e'9d1c'9b1a'9918},
2797 {0xcf4e'cd4c'cb4a'c948, 0xa726'a524'a322'a120}});
2798 }
2799
TEST_F(Riscv64InterpreterTest,TestVlxseg6eiXX_sew64)2800 TEST_F(Riscv64InterpreterTest, TestVlxseg6eiXX_sew64) {
2801 VlxsegXeiXX<UInt64, 6, 1>(0xa5008407, // Vluxseg6ei8.v v8, (x1), v16, v0.t
2802 {{0xb736'b534'b332'b130, 0x8706'8504'8302'8100},
2803 {0xbf3e'bd3c'bb3a'b938, 0x8f0e'8d0c'8b0a'8908},
2804 {0xc746'c544'c342'c140, 0x9716'9514'9312'9110},
2805 {0xcf4e'cd4c'cb4a'c948, 0x9f1e'9d1c'9b1a'9918},
2806 {0xd756'd554'd352'd150, 0xa726'a524'a322'a120},
2807 {0xdf5e'dd5c'db5a'd958, 0xaf2e'ad2c'ab2a'a928}});
2808 }
2809
TEST_F(Riscv64InterpreterTest,TestVlxseg7eiXX_sew64)2810 TEST_F(Riscv64InterpreterTest, TestVlxseg7eiXX_sew64) {
2811 VlxsegXeiXX<UInt64, 7, 1>(0xc5008407, // Vluxseg7ei8.v v8, (x1), v16, v0.t
2812 {{0xbf3e'bd3c'bb3a'b938, 0x8706'8504'8302'8100},
2813 {0xc746'c544'c342'c140, 0x8f0e'8d0c'8b0a'8908},
2814 {0xcf4e'cd4c'cb4a'c948, 0x9716'9514'9312'9110},
2815 {0xd756'd554'd352'd150, 0x9f1e'9d1c'9b1a'9918},
2816 {0xdf5e'dd5c'db5a'd958, 0xa726'a524'a322'a120},
2817 {0xe766'e564'e362'e160, 0xaf2e'ad2c'ab2a'a928},
2818 {0xef6e'ed6c'eb6a'e968, 0xb736'b534'b332'b130}});
2819 }
2820
TEST_F(Riscv64InterpreterTest,TestVlxseg8eiXX_sew64)2821 TEST_F(Riscv64InterpreterTest, TestVlxseg8eiXX_sew64) {
2822 VlxsegXeiXX<UInt64, 8, 1>(0xe5008407, // Vluxseg8ei8.v v8, (x1), v16, v0.t
2823 {{0xc746'c544'c342'c140, 0x8706'8504'8302'8100},
2824 {0xcf4e'cd4c'cb4a'c948, 0x8f0e'8d0c'8b0a'8908},
2825 {0xd756'd554'd352'd150, 0x9716'9514'9312'9110},
2826 {0xdf5e'dd5c'db5a'd958, 0x9f1e'9d1c'9b1a'9918},
2827 {0xe766'e564'e362'e160, 0xa726'a524'a322'a120},
2828 {0xef6e'ed6c'eb6a'e968, 0xaf2e'ad2c'ab2a'a928},
2829 {0xf776'f574'f372'f170, 0xb736'b534'b332'b130},
2830 {0xff7e'fd7c'fb7a'f978, 0xbf3e'bd3c'bb3a'b938}});
2831 }
2832
TEST_F(Riscv64InterpreterTest,TestVle8_vlmul1)2833 TEST_F(Riscv64InterpreterTest, TestVle8_vlmul1) {
2834 TestVlsegXeXX<UInt8, 1, 1>(0x000008407, // vlse8.v v8, (x1), v0.t
2835 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143}});
2836 }
2837
TEST_F(Riscv64InterpreterTest,TestVle8_vlmul2)2838 TEST_F(Riscv64InterpreterTest, TestVle8_vlmul2) {
2839 TestVlsegXeXX<UInt8, 1, 2>(
2840 0x000008407, // vlse8.v v8, (x1), v0.t
2841 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
2842 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159}});
2843 }
2844
TEST_F(Riscv64InterpreterTest,TestVle8_vlmul4)2845 TEST_F(Riscv64InterpreterTest, TestVle8_vlmul4) {
2846 TestVlsegXeXX<UInt8, 1, 4>(
2847 0x000008407, // vlse8.v v8, (x1), v0.t
2848 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
2849 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159},
2850 {32, 161, 34, 163, 36, 165, 38, 167, 40, 169, 42, 171, 44, 173, 46, 175},
2851 {48, 177, 50, 179, 52, 181, 54, 183, 56, 185, 58, 187, 60, 189, 62, 191}});
2852 }
2853
TEST_F(Riscv64InterpreterTest,TestVle8_vlmul8)2854 TEST_F(Riscv64InterpreterTest, TestVle8_vlmul8) {
2855 TestVlsegXeXX<UInt8, 1, 8>(
2856 0x000008407, // vlse8.v v8, (x1), v0.t
2857 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
2858 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159},
2859 {32, 161, 34, 163, 36, 165, 38, 167, 40, 169, 42, 171, 44, 173, 46, 175},
2860 {48, 177, 50, 179, 52, 181, 54, 183, 56, 185, 58, 187, 60, 189, 62, 191},
2861 {64, 193, 66, 195, 68, 197, 70, 199, 72, 201, 74, 203, 76, 205, 78, 207},
2862 {80, 209, 82, 211, 84, 213, 86, 215, 88, 217, 90, 219, 92, 221, 94, 223},
2863 {96, 225, 98, 227, 100, 229, 102, 231, 104, 233, 106, 235, 108, 237, 110, 239},
2864 {112, 241, 114, 243, 116, 245, 118, 247, 120, 249, 122, 251, 124, 253, 126, 255}});
2865 }
2866
TEST_F(Riscv64InterpreterTest,TestVlseg2e8_vlmul1)2867 TEST_F(Riscv64InterpreterTest, TestVlseg2e8_vlmul1) {
2868 TestVlsegXeXX<UInt8, 2, 1>(
2869 0x20008407, // vlseg2e8.v v8, (x1), v0.t
2870 {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
2871 {129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159}});
2872 }
2873
TEST_F(Riscv64InterpreterTest,TestVlseg2e8_vlmul2)2874 TEST_F(Riscv64InterpreterTest, TestVlseg2e8_vlmul2) {
2875 TestVlsegXeXX<UInt8, 2, 2>(
2876 0x20008407, // vlseg2e8.v v8, (x1), v0.t
2877 {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
2878 {32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62},
2879 {129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159},
2880 {161, 163, 165, 167, 169, 171, 173, 175, 177, 179, 181, 183, 185, 187, 189, 191}});
2881 }
2882
TEST_F(Riscv64InterpreterTest,TestVlseg2e8_vlmul4)2883 TEST_F(Riscv64InterpreterTest, TestVlseg2e8_vlmul4) {
2884 TestVlsegXeXX<UInt8, 2, 4>(
2885 0x20008407, // vlseg2e8.v v8, (x1), v0.t
2886 {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
2887 {32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62},
2888 {64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94},
2889 {96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126},
2890 {129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159},
2891 {161, 163, 165, 167, 169, 171, 173, 175, 177, 179, 181, 183, 185, 187, 189, 191},
2892 {193, 195, 197, 199, 201, 203, 205, 207, 209, 211, 213, 215, 217, 219, 221, 223},
2893 {225, 227, 229, 231, 233, 235, 237, 239, 241, 243, 245, 247, 249, 251, 253, 255}});
2894 }
2895
TEST_F(Riscv64InterpreterTest,TestVlseg3e8_vlmul1)2896 TEST_F(Riscv64InterpreterTest, TestVlseg3e8_vlmul1) {
2897 TestVlsegXeXX<UInt8, 3, 1>(
2898 0x40008407, // vlseg3e8.v v8, (x1), v0.t
2899 {{0, 131, 6, 137, 12, 143, 18, 149, 24, 155, 30, 161, 36, 167, 42, 173},
2900 {129, 4, 135, 10, 141, 16, 147, 22, 153, 28, 159, 34, 165, 40, 171, 46},
2901 {2, 133, 8, 139, 14, 145, 20, 151, 26, 157, 32, 163, 38, 169, 44, 175}});
2902 }
2903
TEST_F(Riscv64InterpreterTest,TestVlseg3e8_vlmul2)2904 TEST_F(Riscv64InterpreterTest, TestVlseg3e8_vlmul2) {
2905 TestVlsegXeXX<UInt8, 3, 2>(
2906 0x40008407, // vlseg3e8.v v8, (x1), v0.t
2907 {{0, 131, 6, 137, 12, 143, 18, 149, 24, 155, 30, 161, 36, 167, 42, 173},
2908 {48, 179, 54, 185, 60, 191, 66, 197, 72, 203, 78, 209, 84, 215, 90, 221},
2909 {129, 4, 135, 10, 141, 16, 147, 22, 153, 28, 159, 34, 165, 40, 171, 46},
2910 {177, 52, 183, 58, 189, 64, 195, 70, 201, 76, 207, 82, 213, 88, 219, 94},
2911 {2, 133, 8, 139, 14, 145, 20, 151, 26, 157, 32, 163, 38, 169, 44, 175},
2912 {50, 181, 56, 187, 62, 193, 68, 199, 74, 205, 80, 211, 86, 217, 92, 223}});
2913 }
2914
TEST_F(Riscv64InterpreterTest,TestVlseg4e8_vlmul1)2915 TEST_F(Riscv64InterpreterTest, TestVlseg4e8_vlmul1) {
2916 TestVlsegXeXX<UInt8, 4, 1>(
2917 0x60008407, // vlseg4e8.v v8, (x1), v0.t
2918 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
2919 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
2920 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
2921 {131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191}});
2922 }
2923
TEST_F(Riscv64InterpreterTest,TestVlseg4e8_vlmul2)2924 TEST_F(Riscv64InterpreterTest, TestVlseg4e8_vlmul2) {
2925 TestVlsegXeXX<UInt8, 4, 2>(
2926 0x60008407, // vlseg4e8.v v8, (x1), v0.t
2927 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
2928 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
2929 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
2930 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253},
2931 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
2932 {66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126},
2933 {131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191},
2934 {195, 199, 203, 207, 211, 215, 219, 223, 227, 231, 235, 239, 243, 247, 251, 255}});
2935 }
2936
TEST_F(Riscv64InterpreterTest,TestVlseg5e8)2937 TEST_F(Riscv64InterpreterTest, TestVlseg5e8) {
2938 TestVlsegXeXX<UInt8, 5, 1>(
2939 0x80008407, // vlseg5e8.v v8, (x1), v0.t
2940 {{0, 133, 10, 143, 20, 153, 30, 163, 40, 173, 50, 183, 60, 193, 70, 203},
2941 {129, 6, 139, 16, 149, 26, 159, 36, 169, 46, 179, 56, 189, 66, 199, 76},
2942 {2, 135, 12, 145, 22, 155, 32, 165, 42, 175, 52, 185, 62, 195, 72, 205},
2943 {131, 8, 141, 18, 151, 28, 161, 38, 171, 48, 181, 58, 191, 68, 201, 78},
2944 {4, 137, 14, 147, 24, 157, 34, 167, 44, 177, 54, 187, 64, 197, 74, 207}});
2945 }
2946
TEST_F(Riscv64InterpreterTest,TestVlseg6e8)2947 TEST_F(Riscv64InterpreterTest, TestVlseg6e8) {
2948 TestVlsegXeXX<UInt8, 6, 1>(
2949 0xa0008407, // vlseg6e8.v v8, (x1), v0.t
2950 {{0, 6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90},
2951 {129, 135, 141, 147, 153, 159, 165, 171, 177, 183, 189, 195, 201, 207, 213, 219},
2952 {2, 8, 14, 20, 26, 32, 38, 44, 50, 56, 62, 68, 74, 80, 86, 92},
2953 {131, 137, 143, 149, 155, 161, 167, 173, 179, 185, 191, 197, 203, 209, 215, 221},
2954 {4, 10, 16, 22, 28, 34, 40, 46, 52, 58, 64, 70, 76, 82, 88, 94},
2955 {133, 139, 145, 151, 157, 163, 169, 175, 181, 187, 193, 199, 205, 211, 217, 223}});
2956 }
2957
TEST_F(Riscv64InterpreterTest,TestVlseg7e8)2958 TEST_F(Riscv64InterpreterTest, TestVlseg7e8) {
2959 TestVlsegXeXX<UInt8, 7, 1>(
2960 0xc0008407, // vlseg7e8.v v8, (x1), v0.t
2961 {{0, 135, 14, 149, 28, 163, 42, 177, 56, 191, 70, 205, 84, 219, 98, 233},
2962 {129, 8, 143, 22, 157, 36, 171, 50, 185, 64, 199, 78, 213, 92, 227, 106},
2963 {2, 137, 16, 151, 30, 165, 44, 179, 58, 193, 72, 207, 86, 221, 100, 235},
2964 {131, 10, 145, 24, 159, 38, 173, 52, 187, 66, 201, 80, 215, 94, 229, 108},
2965 {4, 139, 18, 153, 32, 167, 46, 181, 60, 195, 74, 209, 88, 223, 102, 237},
2966 {133, 12, 147, 26, 161, 40, 175, 54, 189, 68, 203, 82, 217, 96, 231, 110},
2967 {6, 141, 20, 155, 34, 169, 48, 183, 62, 197, 76, 211, 90, 225, 104, 239}});
2968 }
2969
TEST_F(Riscv64InterpreterTest,TestVlseg8e8)2970 TEST_F(Riscv64InterpreterTest, TestVlseg8e8) {
2971 TestVlsegXeXX<UInt8, 8, 1>(
2972 0xe0008407, // vlseg8e8.v v8, (x1), v0.t
2973 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
2974 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
2975 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
2976 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
2977 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124},
2978 {133, 141, 149, 157, 165, 173, 181, 189, 197, 205, 213, 221, 229, 237, 245, 253},
2979 {6, 14, 22, 30, 38, 46, 54, 62, 70, 78, 86, 94, 102, 110, 118, 126},
2980 {135, 143, 151, 159, 167, 175, 183, 191, 199, 207, 215, 223, 231, 239, 247, 255}});
2981 }
2982
TEST_F(Riscv64InterpreterTest,TestVle16_vlmul1)2983 TEST_F(Riscv64InterpreterTest, TestVle16_vlmul1) {
2984 TestVlsegXeXX<UInt16, 1, 1>(0x000d407, // vle16.v v8, (x1), v0.t
2985 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e}});
2986 }
2987
TEST_F(Riscv64InterpreterTest,TestVle16_vlmul2)2988 TEST_F(Riscv64InterpreterTest, TestVle16_vlmul2) {
2989 TestVlsegXeXX<UInt16, 1, 2>(0x000d407, // vle16.v v8, (x1), v0.t
2990 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
2991 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e}});
2992 }
2993
TEST_F(Riscv64InterpreterTest,TestVle16_vlmul4)2994 TEST_F(Riscv64InterpreterTest, TestVle16_vlmul4) {
2995 TestVlsegXeXX<UInt16, 1, 4>(0x000d407, // vle16.v v8, (x1), v0.t
2996 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
2997 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e},
2998 {0xa120, 0xa322, 0xa524, 0xa726, 0xa928, 0xab2a, 0xad2c, 0xaf2e},
2999 {0xb130, 0xb332, 0xb534, 0xb736, 0xb938, 0xbb3a, 0xbd3c, 0xbf3e}});
3000 }
3001
TEST_F(Riscv64InterpreterTest,TestVle16_vlmul8)3002 TEST_F(Riscv64InterpreterTest, TestVle16_vlmul8) {
3003 TestVlsegXeXX<UInt16, 1, 8>(0x000d407, // vle16.v v8, (x1), v0.t
3004 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
3005 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e},
3006 {0xa120, 0xa322, 0xa524, 0xa726, 0xa928, 0xab2a, 0xad2c, 0xaf2e},
3007 {0xb130, 0xb332, 0xb534, 0xb736, 0xb938, 0xbb3a, 0xbd3c, 0xbf3e},
3008 {0xc140, 0xc342, 0xc544, 0xc746, 0xc948, 0xcb4a, 0xcd4c, 0xcf4e},
3009 {0xd150, 0xd352, 0xd554, 0xd756, 0xd958, 0xdb5a, 0xdd5c, 0xdf5e},
3010 {0xe160, 0xe362, 0xe564, 0xe766, 0xe968, 0xeb6a, 0xed6c, 0xef6e},
3011 {0xf170, 0xf372, 0xf574, 0xf776, 0xf978, 0xfb7a, 0xfd7c, 0xff7e}});
3012 }
3013
TEST_F(Riscv64InterpreterTest,TestVlseg2e16_vlmul1)3014 TEST_F(Riscv64InterpreterTest, TestVlseg2e16_vlmul1) {
3015 TestVlsegXeXX<UInt16, 2, 1>(0x2000d407, // vlseg2e16.v v8, (x1), v0.t
3016 {{0x8100, 0x8504, 0x8908, 0x8d0c, 0x9110, 0x9514, 0x9918, 0x9d1c},
3017 {0x8302, 0x8706, 0x8b0a, 0x8f0e, 0x9312, 0x9716, 0x9b1a, 0x9f1e}});
3018 }
3019
TEST_F(Riscv64InterpreterTest,TestVlseg2e16_vlmul2)3020 TEST_F(Riscv64InterpreterTest, TestVlseg2e16_vlmul2) {
3021 TestVlsegXeXX<UInt16, 2, 2>(0x2000d407, // vlseg2e16.v v8, (x1), v0.t
3022 {{0x8100, 0x8504, 0x8908, 0x8d0c, 0x9110, 0x9514, 0x9918, 0x9d1c},
3023 {0xa120, 0xa524, 0xa928, 0xad2c, 0xb130, 0xb534, 0xb938, 0xbd3c},
3024 {0x8302, 0x8706, 0x8b0a, 0x8f0e, 0x9312, 0x9716, 0x9b1a, 0x9f1e},
3025 {0xa322, 0xa726, 0xab2a, 0xaf2e, 0xb332, 0xb736, 0xbb3a, 0xbf3e}});
3026 }
3027
TEST_F(Riscv64InterpreterTest,TestVlseg2e16_vlmul4)3028 TEST_F(Riscv64InterpreterTest, TestVlseg2e16_vlmul4) {
3029 TestVlsegXeXX<UInt16, 2, 4>(0x2000d407, // vlseg2e16.v v8, (x1), v0.t
3030 {{0x8100, 0x8504, 0x8908, 0x8d0c, 0x9110, 0x9514, 0x9918, 0x9d1c},
3031 {0xa120, 0xa524, 0xa928, 0xad2c, 0xb130, 0xb534, 0xb938, 0xbd3c},
3032 {0xc140, 0xc544, 0xc948, 0xcd4c, 0xd150, 0xd554, 0xd958, 0xdd5c},
3033 {0xe160, 0xe564, 0xe968, 0xed6c, 0xf170, 0xf574, 0xf978, 0xfd7c},
3034 {0x8302, 0x8706, 0x8b0a, 0x8f0e, 0x9312, 0x9716, 0x9b1a, 0x9f1e},
3035 {0xa322, 0xa726, 0xab2a, 0xaf2e, 0xb332, 0xb736, 0xbb3a, 0xbf3e},
3036 {0xc342, 0xc746, 0xcb4a, 0xcf4e, 0xd352, 0xd756, 0xdb5a, 0xdf5e},
3037 {0xe362, 0xe766, 0xeb6a, 0xef6e, 0xf372, 0xf776, 0xfb7a, 0xff7e}});
3038 }
3039
TEST_F(Riscv64InterpreterTest,TestVlseg3e16_vlmul1)3040 TEST_F(Riscv64InterpreterTest, TestVlseg3e16_vlmul1) {
3041 TestVlsegXeXX<UInt16, 3, 1>(0x4000d407, // vlseg3e16.v v8, (x1), v0.t
3042 {{0x8100, 0x8706, 0x8d0c, 0x9312, 0x9918, 0x9f1e, 0xa524, 0xab2a},
3043 {0x8302, 0x8908, 0x8f0e, 0x9514, 0x9b1a, 0xa120, 0xa726, 0xad2c},
3044 {0x8504, 0x8b0a, 0x9110, 0x9716, 0x9d1c, 0xa322, 0xa928, 0xaf2e}});
3045 }
3046
TEST_F(Riscv64InterpreterTest,TestVlseg3e16_vlmul2)3047 TEST_F(Riscv64InterpreterTest, TestVlseg3e16_vlmul2) {
3048 TestVlsegXeXX<UInt16, 3, 2>(0x4000d407, // vlseg3e16.v v8, (x1), v0.t
3049 {{0x8100, 0x8706, 0x8d0c, 0x9312, 0x9918, 0x9f1e, 0xa524, 0xab2a},
3050 {0xb130, 0xb736, 0xbd3c, 0xc342, 0xc948, 0xcf4e, 0xd554, 0xdb5a},
3051 {0x8302, 0x8908, 0x8f0e, 0x9514, 0x9b1a, 0xa120, 0xa726, 0xad2c},
3052 {0xb332, 0xb938, 0xbf3e, 0xc544, 0xcb4a, 0xd150, 0xd756, 0xdd5c},
3053 {0x8504, 0x8b0a, 0x9110, 0x9716, 0x9d1c, 0xa322, 0xa928, 0xaf2e},
3054 {0xb534, 0xbb3a, 0xc140, 0xc746, 0xcd4c, 0xd352, 0xd958, 0xdf5e}});
3055 }
3056
TEST_F(Riscv64InterpreterTest,TestVlseg4e16_vlmul1)3057 TEST_F(Riscv64InterpreterTest, TestVlseg4e16_vlmul1) {
3058 TestVlsegXeXX<UInt16, 4, 1>(0x6000d407, // vlseg4e16.v v8, (x1), v0.t
3059 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3060 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3061 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3062 {0x8706, 0x8f0e, 0x9716, 0x9f1e, 0xa726, 0xaf2e, 0xb736, 0xbf3e}});
3063 }
3064
TEST_F(Riscv64InterpreterTest,TestVlseg4e16_vlmul2)3065 TEST_F(Riscv64InterpreterTest, TestVlseg4e16_vlmul2) {
3066 TestVlsegXeXX<UInt16, 4, 2>(0x6000d407, // vlseg4e16.v v8, (x1), v0.t
3067 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3068 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3069 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3070 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a},
3071 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3072 {0xc544, 0xcd4c, 0xd554, 0xdd5c, 0xe564, 0xed6c, 0xf574, 0xfd7c},
3073 {0x8706, 0x8f0e, 0x9716, 0x9f1e, 0xa726, 0xaf2e, 0xb736, 0xbf3e},
3074 {0xc746, 0xcf4e, 0xd756, 0xdf5e, 0xe766, 0xef6e, 0xf776, 0xff7e}});
3075 }
3076
TEST_F(Riscv64InterpreterTest,TestVlseg5e16)3077 TEST_F(Riscv64InterpreterTest, TestVlseg5e16) {
3078 TestVlsegXeXX<UInt16, 5, 1>(0x8000d407, // vlseg5e16.v v8, (x1), v0.t
3079 {{0x8100, 0x8b0a, 0x9514, 0x9f1e, 0xa928, 0xb332, 0xbd3c, 0xc746},
3080 {0x8302, 0x8d0c, 0x9716, 0xa120, 0xab2a, 0xb534, 0xbf3e, 0xc948},
3081 {0x8504, 0x8f0e, 0x9918, 0xa322, 0xad2c, 0xb736, 0xc140, 0xcb4a},
3082 {0x8706, 0x9110, 0x9b1a, 0xa524, 0xaf2e, 0xb938, 0xc342, 0xcd4c},
3083 {0x8908, 0x9312, 0x9d1c, 0xa726, 0xb130, 0xbb3a, 0xc544, 0xcf4e}});
3084 }
3085
TEST_F(Riscv64InterpreterTest,TestVlseg6e16)3086 TEST_F(Riscv64InterpreterTest, TestVlseg6e16) {
3087 TestVlsegXeXX<UInt16, 6, 1>(0xa000d407, // vlseg6e16.v v8, (x1), v0.t
3088 {{0x8100, 0x8d0c, 0x9918, 0xa524, 0xb130, 0xbd3c, 0xc948, 0xd554},
3089 {0x8302, 0x8f0e, 0x9b1a, 0xa726, 0xb332, 0xbf3e, 0xcb4a, 0xd756},
3090 {0x8504, 0x9110, 0x9d1c, 0xa928, 0xb534, 0xc140, 0xcd4c, 0xd958},
3091 {0x8706, 0x9312, 0x9f1e, 0xab2a, 0xb736, 0xc342, 0xcf4e, 0xdb5a},
3092 {0x8908, 0x9514, 0xa120, 0xad2c, 0xb938, 0xc544, 0xd150, 0xdd5c},
3093 {0x8b0a, 0x9716, 0xa322, 0xaf2e, 0xbb3a, 0xc746, 0xd352, 0xdf5e}});
3094 }
3095
TEST_F(Riscv64InterpreterTest,TestVlseg7e16)3096 TEST_F(Riscv64InterpreterTest, TestVlseg7e16) {
3097 TestVlsegXeXX<UInt16, 7, 1>(0xc000d407, // vlseg7e16.v v8, (x1), v0.t
3098 {{0x8100, 0x8f0e, 0x9d1c, 0xab2a, 0xb938, 0xc746, 0xd554, 0xe362},
3099 {0x8302, 0x9110, 0x9f1e, 0xad2c, 0xbb3a, 0xc948, 0xd756, 0xe564},
3100 {0x8504, 0x9312, 0xa120, 0xaf2e, 0xbd3c, 0xcb4a, 0xd958, 0xe766},
3101 {0x8706, 0x9514, 0xa322, 0xb130, 0xbf3e, 0xcd4c, 0xdb5a, 0xe968},
3102 {0x8908, 0x9716, 0xa524, 0xb332, 0xc140, 0xcf4e, 0xdd5c, 0xeb6a},
3103 {0x8b0a, 0x9918, 0xa726, 0xb534, 0xc342, 0xd150, 0xdf5e, 0xed6c},
3104 {0x8d0c, 0x9b1a, 0xa928, 0xb736, 0xc544, 0xd352, 0xe160, 0xef6e}});
3105 }
3106
TEST_F(Riscv64InterpreterTest,TestVlseg8e16)3107 TEST_F(Riscv64InterpreterTest, TestVlseg8e16) {
3108 TestVlsegXeXX<UInt16, 8, 1>(0xe000d407, // vlseg8e16.v v8, (x1), v0.t
3109 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3110 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3111 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3112 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3113 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978},
3114 {0x8b0a, 0x9b1a, 0xab2a, 0xbb3a, 0xcb4a, 0xdb5a, 0xeb6a, 0xfb7a},
3115 {0x8d0c, 0x9d1c, 0xad2c, 0xbd3c, 0xcd4c, 0xdd5c, 0xed6c, 0xfd7c},
3116 {0x8f0e, 0x9f1e, 0xaf2e, 0xbf3e, 0xcf4e, 0xdf5e, 0xef6e, 0xff7e}});
3117 }
3118
TEST_F(Riscv64InterpreterTest,TestVle32_vlmul1)3119 TEST_F(Riscv64InterpreterTest, TestVle32_vlmul1) {
3120 TestVlsegXeXX<UInt32, 1, 1>(0x000e407, // vle32.v v8, (x1), v0.t
3121 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c}});
3122 }
3123
TEST_F(Riscv64InterpreterTest,TestVle32_vlmul2)3124 TEST_F(Riscv64InterpreterTest, TestVle32_vlmul2) {
3125 TestVlsegXeXX<UInt32, 1, 2>(0x000e407, // vle32.v v8, (x1), v0.t
3126 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
3127 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c}});
3128 }
3129
TEST_F(Riscv64InterpreterTest,TestVle32_vlmul4)3130 TEST_F(Riscv64InterpreterTest, TestVle32_vlmul4) {
3131 TestVlsegXeXX<UInt32, 1, 4>(0x000e407, // vle32.v v8, (x1), v0.t
3132 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
3133 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
3134 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
3135 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c}});
3136 }
3137
TEST_F(Riscv64InterpreterTest,TestVle32_vlmul8)3138 TEST_F(Riscv64InterpreterTest, TestVle32_vlmul8) {
3139 TestVlsegXeXX<UInt32, 1, 8>(0x000e407, // vle32.v v8, (x1), v0.t
3140 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
3141 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
3142 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
3143 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
3144 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
3145 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
3146 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
3147 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}});
3148 }
3149
TEST_F(Riscv64InterpreterTest,TestVlseg2e32_vlmul1)3150 TEST_F(Riscv64InterpreterTest, TestVlseg2e32_vlmul1) {
3151 TestVlsegXeXX<UInt32, 2, 1>(0x2000e407, // vlseg2e32.v v8, (x1), v0.t
3152 {{0x8302'8100, 0x8b0a'8908, 0x9312'9110, 0x9b1a'9918},
3153 {0x8706'8504, 0x8f0e'8d0c, 0x9716'9514, 0x9f1e'9d1c}});
3154 }
3155
TEST_F(Riscv64InterpreterTest,TestVlseg2e32_vlmul2)3156 TEST_F(Riscv64InterpreterTest, TestVlseg2e32_vlmul2) {
3157 TestVlsegXeXX<UInt32, 2, 2>(0x2000e407, // vlseg2e32.v v8, (x1), v0.t
3158 {{0x8302'8100, 0x8b0a'8908, 0x9312'9110, 0x9b1a'9918},
3159 {0xa322'a120, 0xab2a'a928, 0xb332'b130, 0xbb3a'b938},
3160 {0x8706'8504, 0x8f0e'8d0c, 0x9716'9514, 0x9f1e'9d1c},
3161 {0xa726'a524, 0xaf2e'ad2c, 0xb736'b534, 0xbf3e'bd3c}});
3162 }
3163
TEST_F(Riscv64InterpreterTest,TestVlseg2e32_vlmul4)3164 TEST_F(Riscv64InterpreterTest, TestVlseg2e32_vlmul4) {
3165 TestVlsegXeXX<UInt32, 2, 4>(0x2000e407, // vlseg2e32.v v8, (x1), v0.t
3166 {{0x8302'8100, 0x8b0a'8908, 0x9312'9110, 0x9b1a'9918},
3167 {0xa322'a120, 0xab2a'a928, 0xb332'b130, 0xbb3a'b938},
3168 {0xc342'c140, 0xcb4a'c948, 0xd352'd150, 0xdb5a'd958},
3169 {0xe362'e160, 0xeb6a'e968, 0xf372'f170, 0xfb7a'f978},
3170 {0x8706'8504, 0x8f0e'8d0c, 0x9716'9514, 0x9f1e'9d1c},
3171 {0xa726'a524, 0xaf2e'ad2c, 0xb736'b534, 0xbf3e'bd3c},
3172 {0xc746'c544, 0xcf4e'cd4c, 0xd756'd554, 0xdf5e'dd5c},
3173 {0xe766'e564, 0xef6e'ed6c, 0xf776'f574, 0xff7e'fd7c}});
3174 }
3175
TEST_F(Riscv64InterpreterTest,TestVlseg3e32_vlmul1)3176 TEST_F(Riscv64InterpreterTest, TestVlseg3e32_vlmul1) {
3177 TestVlsegXeXX<UInt32, 3, 1>(0x4000e407, // vlseg3e32.v v8, (x1), v0.t
3178 {{0x8302'8100, 0x8f0e'8d0c, 0x9b1a'9918, 0xa726'a524},
3179 {0x8706'8504, 0x9312'9110, 0x9f1e'9d1c, 0xab2a'a928},
3180 {0x8b0a'8908, 0x9716'9514, 0xa322'a120, 0xaf2e'ad2c}});
3181 }
3182
TEST_F(Riscv64InterpreterTest,TestVlseg3e32_vlmul2)3183 TEST_F(Riscv64InterpreterTest, TestVlseg3e32_vlmul2) {
3184 TestVlsegXeXX<UInt32, 3, 2>(0x4000e407, // vlseg3e32.v v8, (x1), v0.t
3185 {{0x8302'8100, 0x8f0e'8d0c, 0x9b1a'9918, 0xa726'a524},
3186 {0xb332'b130, 0xbf3e'bd3c, 0xcb4a'c948, 0xd756'd554},
3187 {0x8706'8504, 0x9312'9110, 0x9f1e'9d1c, 0xab2a'a928},
3188 {0xb736'b534, 0xc342'c140, 0xcf4e'cd4c, 0xdb5a'd958},
3189 {0x8b0a'8908, 0x9716'9514, 0xa322'a120, 0xaf2e'ad2c},
3190 {0xbb3a'b938, 0xc746'c544, 0xd352'd150, 0xdf5e'dd5c}});
3191 }
3192
TEST_F(Riscv64InterpreterTest,TestVlseg4e32_vlmul1)3193 TEST_F(Riscv64InterpreterTest, TestVlseg4e32_vlmul1) {
3194 TestVlsegXeXX<UInt32, 4, 1>(0x6000e407, // vlseg4e32.v v8, (x1), v0.t
3195 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3196 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3197 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3198 {0x8f0e'8d0c, 0x9f1e'9d1c, 0xaf2e'ad2c, 0xbf3e'bd3c}});
3199 }
3200
TEST_F(Riscv64InterpreterTest,TestVlseg4e32_vlmul2)3201 TEST_F(Riscv64InterpreterTest, TestVlseg4e32_vlmul2) {
3202 TestVlsegXeXX<UInt32, 4, 2>(0x6000e407, // vlseg4e32.v v8, (x1), v0.t
3203 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3204 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3205 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3206 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574},
3207 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3208 {0xcb4a'c948, 0xdb5a'd958, 0xeb6a'e968, 0xfb7a'f978},
3209 {0x8f0e'8d0c, 0x9f1e'9d1c, 0xaf2e'ad2c, 0xbf3e'bd3c},
3210 {0xcf4e'cd4c, 0xdf5e'dd5c, 0xef6e'ed6c, 0xff7e'fd7c}});
3211 }
3212
TEST_F(Riscv64InterpreterTest,TestVlseg5e32)3213 TEST_F(Riscv64InterpreterTest, TestVlseg5e32) {
3214 TestVlsegXeXX<UInt32, 5, 1>(0x8000e407, // vlseg5e32.v v8, (x1), v0.t
3215 {{0x8302'8100, 0x9716'9514, 0xab2a'a928, 0xbf3e'bd3c},
3216 {0x8706'8504, 0x9b1a'9918, 0xaf2e'ad2c, 0xc342'c140},
3217 {0x8b0a'8908, 0x9f1e'9d1c, 0xb332'b130, 0xc746'c544},
3218 {0x8f0e'8d0c, 0xa322'a120, 0xb736'b534, 0xcb4a'c948},
3219 {0x9312'9110, 0xa726'a524, 0xbb3a'b938, 0xcf4e'cd4c}});
3220 }
3221
TEST_F(Riscv64InterpreterTest,TestVlseg6e32)3222 TEST_F(Riscv64InterpreterTest, TestVlseg6e32) {
3223 TestVlsegXeXX<UInt32, 6, 1>(0xa000e407, // vlseg6e32.v v8, (x1), v0.t
3224 {{0x8302'8100, 0x9b1a'9918, 0xb332'b130, 0xcb4a'c948},
3225 {0x8706'8504, 0x9f1e'9d1c, 0xb736'b534, 0xcf4e'cd4c},
3226 {0x8b0a'8908, 0xa322'a120, 0xbb3a'b938, 0xd352'd150},
3227 {0x8f0e'8d0c, 0xa726'a524, 0xbf3e'bd3c, 0xd756'd554},
3228 {0x9312'9110, 0xab2a'a928, 0xc342'c140, 0xdb5a'd958},
3229 {0x9716'9514, 0xaf2e'ad2c, 0xc746'c544, 0xdf5e'dd5c}});
3230 }
3231
TEST_F(Riscv64InterpreterTest,TestVlseg7e32)3232 TEST_F(Riscv64InterpreterTest, TestVlseg7e32) {
3233 TestVlsegXeXX<UInt32, 7, 1>(0xc000e407, // vlseg7e32.v v8, (x1), v0.t
3234 {{0x8302'8100, 0x9f1e'9d1c, 0xbb3a'b938, 0xd756'd554},
3235 {0x8706'8504, 0xa322'a120, 0xbf3e'bd3c, 0xdb5a'd958},
3236 {0x8b0a'8908, 0xa726'a524, 0xc342'c140, 0xdf5e'dd5c},
3237 {0x8f0e'8d0c, 0xab2a'a928, 0xc746'c544, 0xe362'e160},
3238 {0x9312'9110, 0xaf2e'ad2c, 0xcb4a'c948, 0xe766'e564},
3239 {0x9716'9514, 0xb332'b130, 0xcf4e'cd4c, 0xeb6a'e968},
3240 {0x9b1a'9918, 0xb736'b534, 0xd352'd150, 0xef6e'ed6c}});
3241 }
3242
TEST_F(Riscv64InterpreterTest,TestVlseg8e32)3243 TEST_F(Riscv64InterpreterTest, TestVlseg8e32) {
3244 TestVlsegXeXX<UInt32, 8, 1>(0xe000e407, // vlseg8e32.v v8, (x1), v0.t
3245 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3246 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3247 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3248 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3249 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170},
3250 {0x9716'9514, 0xb736'b534, 0xd756'd554, 0xf776'f574},
3251 {0x9b1a'9918, 0xbb3a'b938, 0xdb5a'd958, 0xfb7a'f978},
3252 {0x9f1e'9d1c, 0xbf3e'bd3c, 0xdf5e'dd5c, 0xff7e'fd7c}});
3253 }
3254
TEST_F(Riscv64InterpreterTest,TestVle64_vlmul1)3255 TEST_F(Riscv64InterpreterTest, TestVle64_vlmul1) {
3256 TestVlsegXeXX<UInt64, 1, 1>(0x000f407, // vle64.v v8, (x1), v0.t
3257 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908}});
3258 }
3259
TEST_F(Riscv64InterpreterTest,TestVle64_vlmul2)3260 TEST_F(Riscv64InterpreterTest, TestVle64_vlmul2) {
3261 TestVlsegXeXX<UInt64, 1, 2>(0x000f407, // vle64.v v8, (x1), v0.t
3262 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
3263 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918}});
3264 }
3265
TEST_F(Riscv64InterpreterTest,TestVle64_vlmul4)3266 TEST_F(Riscv64InterpreterTest, TestVle64_vlmul4) {
3267 TestVlsegXeXX<UInt64, 1, 4>(0x000f407, // vle64.v v8, (x1), v0.t
3268 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
3269 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
3270 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
3271 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938}});
3272 }
3273
TEST_F(Riscv64InterpreterTest,TestVle64_vlmul8)3274 TEST_F(Riscv64InterpreterTest, TestVle64_vlmul8) {
3275 TestVlsegXeXX<UInt64, 1, 8>(0x000f407, // vle64.v v8, (x1), v0.t
3276 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
3277 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
3278 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
3279 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
3280 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
3281 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
3282 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
3283 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}});
3284 }
3285
TEST_F(Riscv64InterpreterTest,TestVlseg2e64_vlmul1)3286 TEST_F(Riscv64InterpreterTest, TestVlseg2e64_vlmul1) {
3287 TestVlsegXeXX<UInt64, 2, 1>(0x2000f407, // vlseg2e64.v v8, (x1), v0.t
3288 {{0x8706'8504'8302'8100, 0x9716'9514'9312'9110},
3289 {0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918}});
3290 }
3291
TEST_F(Riscv64InterpreterTest,TestVlseg2e64_vlmul2)3292 TEST_F(Riscv64InterpreterTest, TestVlseg2e64_vlmul2) {
3293 TestVlsegXeXX<UInt64, 2, 2>(0x2000f407, // vlseg2e64.v v8, (x1), v0.t
3294 {{0x8706'8504'8302'8100, 0x9716'9514'9312'9110},
3295 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130},
3296 {0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918},
3297 {0xaf2e'ad2c'ab2a'a928, 0xbf3e'bd3c'bb3a'b938}});
3298 }
3299
TEST_F(Riscv64InterpreterTest,TestVlseg2e64_vlmul4)3300 TEST_F(Riscv64InterpreterTest, TestVlseg2e64_vlmul4) {
3301 TestVlsegXeXX<UInt64, 2, 4>(0x2000f407, // vlseg2e64.v v8, (x1), v0.t
3302 {{0x8706'8504'8302'8100, 0x9716'9514'9312'9110},
3303 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130},
3304 {0xc746'c544'c342'c140, 0xd756'd554'd352'd150},
3305 {0xe766'e564'e362'e160, 0xf776'f574'f372'f170},
3306 {0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918},
3307 {0xaf2e'ad2c'ab2a'a928, 0xbf3e'bd3c'bb3a'b938},
3308 {0xcf4e'cd4c'cb4a'c948, 0xdf5e'dd5c'db5a'd958},
3309 {0xef6e'ed6c'eb6a'e968, 0xff7e'fd7c'fb7a'f978}});
3310 }
3311
TEST_F(Riscv64InterpreterTest,TestVlseg3e64_vlmul1)3312 TEST_F(Riscv64InterpreterTest, TestVlseg3e64_vlmul1) {
3313 TestVlsegXeXX<UInt64, 3, 1>(0x4000f407, // vlseg3e64.v v8, (x1), v0.t
3314 {{0x8706'8504'8302'8100, 0x9f1e'9d1c'9b1a'9918},
3315 {0x8f0e'8d0c'8b0a'8908, 0xa726'a524'a322'a120},
3316 {0x9716'9514'9312'9110, 0xaf2e'ad2c'ab2a'a928}});
3317 }
3318
TEST_F(Riscv64InterpreterTest,TestVlseg3e64_vlmul2)3319 TEST_F(Riscv64InterpreterTest, TestVlseg3e64_vlmul2) {
3320 TestVlsegXeXX<UInt64, 3, 2>(0x4000f407, // vlseg3e64.v v8, (x1), v0.t
3321 {{0x8706'8504'8302'8100, 0x9f1e'9d1c'9b1a'9918},
3322 {0xb736'b534'b332'b130, 0xcf4e'cd4c'cb4a'c948},
3323 {0x8f0e'8d0c'8b0a'8908, 0xa726'a524'a322'a120},
3324 {0xbf3e'bd3c'bb3a'b938, 0xd756'd554'd352'd150},
3325 {0x9716'9514'9312'9110, 0xaf2e'ad2c'ab2a'a928},
3326 {0xc746'c544'c342'c140, 0xdf5e'dd5c'db5a'd958}});
3327 }
3328
TEST_F(Riscv64InterpreterTest,TestVlseg4e64_vlmul1)3329 TEST_F(Riscv64InterpreterTest, TestVlseg4e64_vlmul1) {
3330 TestVlsegXeXX<UInt64, 4, 1>(0x6000f407, // vlseg4e64.v v8, (x1), v0.t
3331 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3332 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3333 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3334 {0x9f1e'9d1c'9b1a'9918, 0xbf3e'bd3c'bb3a'b938}});
3335 }
3336
TEST_F(Riscv64InterpreterTest,TestVlseg4e64_vlmul2)3337 TEST_F(Riscv64InterpreterTest, TestVlseg4e64_vlmul2) {
3338 TestVlsegXeXX<UInt64, 4, 2>(0x6000f407, // vlseg4e64.v v8, (x1), v0.t
3339 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3340 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3341 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3342 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968},
3343 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3344 {0xd756'd554'd352'd150, 0xf776'f574'f372'f170},
3345 {0x9f1e'9d1c'9b1a'9918, 0xbf3e'bd3c'bb3a'b938},
3346 {0xdf5e'dd5c'db5a'd958, 0xff7e'fd7c'fb7a'f978}});
3347 }
3348
TEST_F(Riscv64InterpreterTest,TestVlseg5e64)3349 TEST_F(Riscv64InterpreterTest, TestVlseg5e64) {
3350 TestVlsegXeXX<UInt64, 5, 1>(0x8000f407, // vlseg5e64.v v8, (x1), v0.t
3351 {{0x8706'8504'8302'8100, 0xaf2e'ad2c'ab2a'a928},
3352 {0x8f0e'8d0c'8b0a'8908, 0xb736'b534'b332'b130},
3353 {0x9716'9514'9312'9110, 0xbf3e'bd3c'bb3a'b938},
3354 {0x9f1e'9d1c'9b1a'9918, 0xc746'c544'c342'c140},
3355 {0xa726'a524'a322'a120, 0xcf4e'cd4c'cb4a'c948}});
3356 }
3357
TEST_F(Riscv64InterpreterTest,TestVlseg6e64)3358 TEST_F(Riscv64InterpreterTest, TestVlseg6e64) {
3359 TestVlsegXeXX<UInt64, 6, 1>(0xa000f407, // vlseg6e64.v v8, (x1), v0.t
3360 {{0x8706'8504'8302'8100, 0xb736'b534'b332'b130},
3361 {0x8f0e'8d0c'8b0a'8908, 0xbf3e'bd3c'bb3a'b938},
3362 {0x9716'9514'9312'9110, 0xc746'c544'c342'c140},
3363 {0x9f1e'9d1c'9b1a'9918, 0xcf4e'cd4c'cb4a'c948},
3364 {0xa726'a524'a322'a120, 0xd756'd554'd352'd150},
3365 {0xaf2e'ad2c'ab2a'a928, 0xdf5e'dd5c'db5a'd958}});
3366 }
3367
TEST_F(Riscv64InterpreterTest,TestVlseg7e64)3368 TEST_F(Riscv64InterpreterTest, TestVlseg7e64) {
3369 TestVlsegXeXX<UInt64, 7, 1>(0xc000f407, // vlseg7e64.v v8, (x1), v0.t
3370 {{0x8706'8504'8302'8100, 0xbf3e'bd3c'bb3a'b938},
3371 {0x8f0e'8d0c'8b0a'8908, 0xc746'c544'c342'c140},
3372 {0x9716'9514'9312'9110, 0xcf4e'cd4c'cb4a'c948},
3373 {0x9f1e'9d1c'9b1a'9918, 0xd756'd554'd352'd150},
3374 {0xa726'a524'a322'a120, 0xdf5e'dd5c'db5a'd958},
3375 {0xaf2e'ad2c'ab2a'a928, 0xe766'e564'e362'e160},
3376 {0xb736'b534'b332'b130, 0xef6e'ed6c'eb6a'e968}});
3377 }
3378
TEST_F(Riscv64InterpreterTest,TestVlseg8e64)3379 TEST_F(Riscv64InterpreterTest, TestVlseg8e64) {
3380 TestVlsegXeXX<UInt64, 8, 1>(0xe000f407, // vlseg8e64.v v8, (x1), v0.t
3381 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3382 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3383 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3384 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3385 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160},
3386 {0xaf2e'ad2c'ab2a'a928, 0xef6e'ed6c'eb6a'e968},
3387 {0xb736'b534'b332'b130, 0xf776'f574'f372'f170},
3388 {0xbf3e'bd3c'bb3a'b938, 0xff7e'fd7c'fb7a'f978}});
3389 }
3390
TEST_F(Riscv64InterpreterTest,TestVlse8_vlmul1)3391 TEST_F(Riscv64InterpreterTest, TestVlse8_vlmul1) {
3392 TestVlssegXeXX<UInt8, 1, 1>(0x08208407, // vlse8.v v8, (x1), x2, v0.t
3393 4,
3394 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60}});
3395 }
3396
TEST_F(Riscv64InterpreterTest,TestVlse8_vlmul2)3397 TEST_F(Riscv64InterpreterTest, TestVlse8_vlmul2) {
3398 TestVlssegXeXX<UInt8, 1, 2>(
3399 0x08208407, // vlse8.v v8, (x1), x2, v0.t
3400 4,
3401 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3402 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124}});
3403 }
3404
TEST_F(Riscv64InterpreterTest,TestVlse8_vlmul4)3405 TEST_F(Riscv64InterpreterTest, TestVlse8_vlmul4) {
3406 TestVlssegXeXX<UInt8, 1, 4>(
3407 0x08208407, // vlse8.v v8, (x1), x2, v0.t
3408 4,
3409 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3410 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3411 {0, 9, 17, 24, 32, 41, 49, 56, 64, 73, 81, 88, 96, 105, 113, 120},
3412 {128, 137, 145, 152, 160, 169, 177, 184, 192, 201, 209, 216, 224, 233, 241, 248}});
3413 }
3414
TEST_F(Riscv64InterpreterTest,TestVlse8_vlmul8)3415 TEST_F(Riscv64InterpreterTest, TestVlse8_vlmul8) {
3416 TestVlssegXeXX<UInt8, 1, 8>(
3417 0x08208407, // vlse8.v v8, (x1), x2, v0.t
3418 2,
3419 {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
3420 {32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62},
3421 {64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94},
3422 {96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126},
3423 {0, 4, 9, 12, 17, 20, 24, 28, 32, 36, 41, 44, 49, 52, 56, 60},
3424 {64, 68, 73, 76, 81, 84, 88, 92, 96, 100, 105, 108, 113, 116, 120, 124},
3425 {128, 132, 137, 140, 145, 148, 152, 156, 160, 164, 169, 172, 177, 180, 184, 188},
3426 {192, 196, 201, 204, 209, 212, 216, 220, 224, 228, 233, 236, 241, 244, 248, 252}});
3427 }
3428
TEST_F(Riscv64InterpreterTest,TestVlsseg2e8_vlmul1)3429 TEST_F(Riscv64InterpreterTest, TestVlsseg2e8_vlmul1) {
3430 TestVlssegXeXX<UInt8, 2, 1>(
3431 0x28208407, // vlsseg2e8.v v8, (x1), x2, v0.t
3432 4,
3433 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3434 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189}});
3435 }
3436
TEST_F(Riscv64InterpreterTest,TestVlsseg2e8_vlmul2)3437 TEST_F(Riscv64InterpreterTest, TestVlsseg2e8_vlmul2) {
3438 TestVlssegXeXX<UInt8, 2, 2>(
3439 0x28208407, // vlsseg2e8.v v8, (x1), x2, v0.t
3440 4,
3441 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3442 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3443 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3444 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253}});
3445 }
3446
TEST_F(Riscv64InterpreterTest,TestVlsseg2e8_vlmul4)3447 TEST_F(Riscv64InterpreterTest, TestVlsseg2e8_vlmul4) {
3448 TestVlssegXeXX<UInt8, 2, 4>(
3449 0x28208407, // vlsseg2e8.v v8, (x1), x2, v0.t
3450 4,
3451 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3452 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3453 {0, 9, 17, 24, 32, 41, 49, 56, 64, 73, 81, 88, 96, 105, 113, 120},
3454 {128, 137, 145, 152, 160, 169, 177, 184, 192, 201, 209, 216, 224, 233, 241, 248},
3455 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3456 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253},
3457 {146, 154, 130, 138, 178, 186, 162, 170, 210, 218, 194, 202, 242, 250, 226, 234},
3458 {18, 26, 2, 10, 50, 58, 34, 42, 82, 90, 66, 74, 114, 122, 98, 106}});
3459 }
3460
TEST_F(Riscv64InterpreterTest,TestVlsseg3e8_vlmul1)3461 TEST_F(Riscv64InterpreterTest, TestVlsseg3e8_vlmul1) {
3462 TestVlssegXeXX<UInt8, 3, 1>(
3463 0x48208407, // vlsseg3e8.v v8, (x1), x2, v0.t
3464 4,
3465 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3466 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3467 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62}});
3468 }
3469
TEST_F(Riscv64InterpreterTest,TestVlsseg3e8_vlmul2)3470 TEST_F(Riscv64InterpreterTest, TestVlsseg3e8_vlmul2) {
3471 TestVlssegXeXX<UInt8, 3, 2>(
3472 0x48208407, // vlsseg3e8.v v8, (x1), x2, v0.t
3473 4,
3474 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3475 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3476 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3477 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253},
3478 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
3479 {66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126}});
3480 }
3481
TEST_F(Riscv64InterpreterTest,TestVlsseg4e8_vlmul1)3482 TEST_F(Riscv64InterpreterTest, TestVlsseg4e8_vlmul1) {
3483 TestVlssegXeXX<UInt8, 4, 1>(
3484 0x68208407, // vlsseg4e8.v v8, (x1), x2, v0.t
3485 4,
3486 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3487 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3488 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
3489 {131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191}});
3490 }
3491
TEST_F(Riscv64InterpreterTest,TestVlsseg4e8_vlmul2)3492 TEST_F(Riscv64InterpreterTest, TestVlsseg4e8_vlmul2) {
3493 TestVlssegXeXX<UInt8, 4, 2>(
3494 0x68208407, // vlsseg4e8.v v8, (x1), x2, v0.t
3495 4,
3496 {{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60},
3497 {64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124},
3498 {129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 189},
3499 {193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237, 241, 245, 249, 253},
3500 {2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62},
3501 {66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126},
3502 {131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191},
3503 {195, 199, 203, 207, 211, 215, 219, 223, 227, 231, 235, 239, 243, 247, 251, 255}});
3504 }
3505
TEST_F(Riscv64InterpreterTest,TestVlsseg5e8)3506 TEST_F(Riscv64InterpreterTest, TestVlsseg5e8) {
3507 TestVlssegXeXX<UInt8, 5, 1>(
3508 0x88208407, // vlsseg5e8.v v8, (x1), x2, v0.t
3509 8,
3510 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
3511 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
3512 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
3513 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
3514 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124}});
3515 }
3516
TEST_F(Riscv64InterpreterTest,TestVlsseg6e8)3517 TEST_F(Riscv64InterpreterTest, TestVlsseg6e8) {
3518 TestVlssegXeXX<UInt8, 6, 1>(
3519 0xa8208407, // vlsseg6e8.v v8, (x1), x2, v0.t
3520 8,
3521 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
3522 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
3523 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
3524 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
3525 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124},
3526 {133, 141, 149, 157, 165, 173, 181, 189, 197, 205, 213, 221, 229, 237, 245, 253}});
3527 }
3528
TEST_F(Riscv64InterpreterTest,TestVlsseg7e8)3529 TEST_F(Riscv64InterpreterTest, TestVlsseg7e8) {
3530 TestVlssegXeXX<UInt8, 7, 1>(
3531 0xc8208407, // vlsseg7e8.v v8, (x1), x2, v0.t
3532 8,
3533 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
3534 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
3535 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
3536 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
3537 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124},
3538 {133, 141, 149, 157, 165, 173, 181, 189, 197, 205, 213, 221, 229, 237, 245, 253},
3539 {6, 14, 22, 30, 38, 46, 54, 62, 70, 78, 86, 94, 102, 110, 118, 126}});
3540 }
3541
TEST_F(Riscv64InterpreterTest,TestVlsseg8e8)3542 TEST_F(Riscv64InterpreterTest, TestVlsseg8e8) {
3543 TestVlssegXeXX<UInt8, 8, 1>(
3544 0xe8208407, // vlsseg8e8.v v8, (x1), x2, v0.t
3545 8,
3546 {{0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120},
3547 {129, 137, 145, 153, 161, 169, 177, 185, 193, 201, 209, 217, 225, 233, 241, 249},
3548 {2, 10, 18, 26, 34, 42, 50, 58, 66, 74, 82, 90, 98, 106, 114, 122},
3549 {131, 139, 147, 155, 163, 171, 179, 187, 195, 203, 211, 219, 227, 235, 243, 251},
3550 {4, 12, 20, 28, 36, 44, 52, 60, 68, 76, 84, 92, 100, 108, 116, 124},
3551 {133, 141, 149, 157, 165, 173, 181, 189, 197, 205, 213, 221, 229, 237, 245, 253},
3552 {6, 14, 22, 30, 38, 46, 54, 62, 70, 78, 86, 94, 102, 110, 118, 126},
3553 {135, 143, 151, 159, 167, 175, 183, 191, 199, 207, 215, 223, 231, 239, 247, 255}});
3554 }
3555
TEST_F(Riscv64InterpreterTest,TestVlse16_vlmul1)3556 TEST_F(Riscv64InterpreterTest, TestVlse16_vlmul1) {
3557 TestVlssegXeXX<UInt16, 1, 1>(0x820d407, // vlse16.v v8, (x1), x2, v0.t
3558 8,
3559 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938}});
3560 }
3561
TEST_F(Riscv64InterpreterTest,TestVlse16_vlmul2)3562 TEST_F(Riscv64InterpreterTest, TestVlse16_vlmul2) {
3563 TestVlssegXeXX<UInt16, 1, 2>(0x820d407, // vlse16.v v8, (x1), x2, v0.t
3564 8,
3565 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3566 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978}});
3567 }
3568
TEST_F(Riscv64InterpreterTest,TestVlse16_vlmul4)3569 TEST_F(Riscv64InterpreterTest, TestVlse16_vlmul4) {
3570 TestVlssegXeXX<UInt16, 1, 4>(0x820d407, // vlse16.v v8, (x1), x2, v0.t
3571 8,
3572 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3573 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3574 {0x9200, 0x8211, 0xb220, 0xa231, 0xd240, 0xc251, 0xf260, 0xe271},
3575 {0x1280, 0x0291, 0x32a0, 0x22b1, 0x52c0, 0x42d1, 0x72e0, 0x62f1}});
3576 }
3577
TEST_F(Riscv64InterpreterTest,TestVlse16_vlmul8)3578 TEST_F(Riscv64InterpreterTest, TestVlse16_vlmul8) {
3579 TestVlssegXeXX<UInt16, 1, 8>(0x820d407, // vlse16.v v8, (x1), x2, v0.t
3580 4,
3581 {{0x8100, 0x8504, 0x8908, 0x8d0c, 0x9110, 0x9514, 0x9918, 0x9d1c},
3582 {0xa120, 0xa524, 0xa928, 0xad2c, 0xb130, 0xb534, 0xb938, 0xbd3c},
3583 {0xc140, 0xc544, 0xc948, 0xcd4c, 0xd150, 0xd554, 0xd958, 0xdd5c},
3584 {0xe160, 0xe564, 0xe968, 0xed6c, 0xf170, 0xf574, 0xf978, 0xfd7c},
3585 {0x9200, 0x9a09, 0x8211, 0x8a18, 0xb220, 0xba29, 0xa231, 0xaa38},
3586 {0xd240, 0xda49, 0xc251, 0xca58, 0xf260, 0xfa69, 0xe271, 0xea78},
3587 {0x1280, 0x1a89, 0x0291, 0x0a98, 0x32a0, 0x3aa9, 0x22b1, 0x2ab8},
3588 {0x52c0, 0x5ac9, 0x42d1, 0x4ad8, 0x72e0, 0x7ae9, 0x62f1, 0x6af8}});
3589 }
3590
TEST_F(Riscv64InterpreterTest,TestVlsseg2e16_vlmul1)3591 TEST_F(Riscv64InterpreterTest, TestVlsseg2e16_vlmul1) {
3592 TestVlssegXeXX<UInt16, 2, 1>(0x2820d407, // vlsseg2e16.v v8, (x1), x2, v0.t
3593 8,
3594 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3595 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a}});
3596 }
3597
TEST_F(Riscv64InterpreterTest,TestVlsseg2e16_vlmul2)3598 TEST_F(Riscv64InterpreterTest, TestVlsseg2e16_vlmul2) {
3599 TestVlssegXeXX<UInt16, 2, 2>(0x2820d407, // vlsseg2e16.v v8, (x1), x2, v0.t
3600 8,
3601 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3602 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3603 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3604 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a}});
3605 }
3606
TEST_F(Riscv64InterpreterTest,TestVlsseg2e16_vlmul4)3607 TEST_F(Riscv64InterpreterTest, TestVlsseg2e16_vlmul4) {
3608 TestVlssegXeXX<UInt16, 2, 4>(0x2820d407, // vlsseg2e16.v v8, (x1), x2, v0.t
3609 8,
3610 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3611 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3612 {0x9200, 0x8211, 0xb220, 0xa231, 0xd240, 0xc251, 0xf260, 0xe271},
3613 {0x1280, 0x0291, 0x32a0, 0x22b1, 0x52c0, 0x42d1, 0x72e0, 0x62f1},
3614 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3615 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a},
3616 {0x9604, 0x8614, 0xb624, 0xa634, 0xd644, 0xc654, 0xf664, 0xe674},
3617 {0x1684, 0x0694, 0x36a4, 0x26b4, 0x56c4, 0x46d4, 0x76e4, 0x66f4}});
3618 }
3619
TEST_F(Riscv64InterpreterTest,TestVlsseg3e16_vlmul1)3620 TEST_F(Riscv64InterpreterTest, TestVlsseg3e16_vlmul1) {
3621 TestVlssegXeXX<UInt16, 3, 1>(0x4820d407, // vlsseg3e16.v v8, (x1), x2, v0.t
3622 8,
3623 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3624 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3625 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c}});
3626 }
3627
TEST_F(Riscv64InterpreterTest,TestVlsseg3e16_vlmul2)3628 TEST_F(Riscv64InterpreterTest, TestVlsseg3e16_vlmul2) {
3629 TestVlssegXeXX<UInt16, 3, 2>(0x4820d407, // vlsseg3e16.v v8, (x1), x2, v0.t
3630 8,
3631 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3632 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3633 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3634 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a},
3635 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3636 {0xc544, 0xcd4c, 0xd554, 0xdd5c, 0xe564, 0xed6c, 0xf574, 0xfd7c}});
3637 }
3638
TEST_F(Riscv64InterpreterTest,TestVlsseg4e16_vlmul1)3639 TEST_F(Riscv64InterpreterTest, TestVlsseg4e16_vlmul1) {
3640 TestVlssegXeXX<UInt16, 4, 1>(0x6820d407, // vlsseg4e16.v v8, (x1), x2, v0.t
3641 8,
3642 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3643 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3644 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3645 {0x8706, 0x8f0e, 0x9716, 0x9f1e, 0xa726, 0xaf2e, 0xb736, 0xbf3e}});
3646 }
3647
TEST_F(Riscv64InterpreterTest,TestVlsseg4e16_vlmul2)3648 TEST_F(Riscv64InterpreterTest, TestVlsseg4e16_vlmul2) {
3649 TestVlssegXeXX<UInt16, 4, 2>(0x6820d407, // vlsseg4e16.v v8, (x1), x2, v0.t
3650 8,
3651 {{0x8100, 0x8908, 0x9110, 0x9918, 0xa120, 0xa928, 0xb130, 0xb938},
3652 {0xc140, 0xc948, 0xd150, 0xd958, 0xe160, 0xe968, 0xf170, 0xf978},
3653 {0x8302, 0x8b0a, 0x9312, 0x9b1a, 0xa322, 0xab2a, 0xb332, 0xbb3a},
3654 {0xc342, 0xcb4a, 0xd352, 0xdb5a, 0xe362, 0xeb6a, 0xf372, 0xfb7a},
3655 {0x8504, 0x8d0c, 0x9514, 0x9d1c, 0xa524, 0xad2c, 0xb534, 0xbd3c},
3656 {0xc544, 0xcd4c, 0xd554, 0xdd5c, 0xe564, 0xed6c, 0xf574, 0xfd7c},
3657 {0x8706, 0x8f0e, 0x9716, 0x9f1e, 0xa726, 0xaf2e, 0xb736, 0xbf3e},
3658 {0xc746, 0xcf4e, 0xd756, 0xdf5e, 0xe766, 0xef6e, 0xf776, 0xff7e}});
3659 }
3660
TEST_F(Riscv64InterpreterTest,TestVlsseg5e16)3661 TEST_F(Riscv64InterpreterTest, TestVlsseg5e16) {
3662 TestVlssegXeXX<UInt16, 5, 1>(0x8820d407, // vlsseg5e16.v v8, (x1), x2, v0.t
3663 16,
3664 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3665 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3666 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3667 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3668 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978}});
3669 }
3670
TEST_F(Riscv64InterpreterTest,TestVlsseg6e16)3671 TEST_F(Riscv64InterpreterTest, TestVlsseg6e16) {
3672 TestVlssegXeXX<UInt16, 6, 1>(0xa820d407, // vlsseg6e16.v v8, (x1), x2, v0.t
3673 16,
3674 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3675 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3676 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3677 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3678 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978},
3679 {0x8b0a, 0x9b1a, 0xab2a, 0xbb3a, 0xcb4a, 0xdb5a, 0xeb6a, 0xfb7a}});
3680 }
3681
TEST_F(Riscv64InterpreterTest,TestVlsseg7e16)3682 TEST_F(Riscv64InterpreterTest, TestVlsseg7e16) {
3683 TestVlssegXeXX<UInt16, 7, 1>(0xc820d407, // vlsseg7e16.v v8, (x1), x2, v0.t
3684 16,
3685 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3686 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3687 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3688 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3689 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978},
3690 {0x8b0a, 0x9b1a, 0xab2a, 0xbb3a, 0xcb4a, 0xdb5a, 0xeb6a, 0xfb7a},
3691 {0x8d0c, 0x9d1c, 0xad2c, 0xbd3c, 0xcd4c, 0xdd5c, 0xed6c, 0xfd7c}});
3692 }
3693
TEST_F(Riscv64InterpreterTest,TestVlsseg8e16)3694 TEST_F(Riscv64InterpreterTest, TestVlsseg8e16) {
3695 TestVlssegXeXX<UInt16, 8, 1>(0xe820d407, // vlsseg8e16.v v8, (x1), x2, v0.t
3696 16,
3697 {{0x8100, 0x9110, 0xa120, 0xb130, 0xc140, 0xd150, 0xe160, 0xf170},
3698 {0x8302, 0x9312, 0xa322, 0xb332, 0xc342, 0xd352, 0xe362, 0xf372},
3699 {0x8504, 0x9514, 0xa524, 0xb534, 0xc544, 0xd554, 0xe564, 0xf574},
3700 {0x8706, 0x9716, 0xa726, 0xb736, 0xc746, 0xd756, 0xe766, 0xf776},
3701 {0x8908, 0x9918, 0xa928, 0xb938, 0xc948, 0xd958, 0xe968, 0xf978},
3702 {0x8b0a, 0x9b1a, 0xab2a, 0xbb3a, 0xcb4a, 0xdb5a, 0xeb6a, 0xfb7a},
3703 {0x8d0c, 0x9d1c, 0xad2c, 0xbd3c, 0xcd4c, 0xdd5c, 0xed6c, 0xfd7c},
3704 {0x8f0e, 0x9f1e, 0xaf2e, 0xbf3e, 0xcf4e, 0xdf5e, 0xef6e, 0xff7e}});
3705 }
3706
TEST_F(Riscv64InterpreterTest,TestVlse32_vlmul1)3707 TEST_F(Riscv64InterpreterTest, TestVlse32_vlmul1) {
3708 TestVlssegXeXX<UInt32, 1, 1>(0x820e407, // vlse32.v v8, (x1), x2, v0.t
3709 16,
3710 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130}});
3711 }
3712
TEST_F(Riscv64InterpreterTest,TestVlse32_vlmul2)3713 TEST_F(Riscv64InterpreterTest, TestVlse32_vlmul2) {
3714 TestVlssegXeXX<UInt32, 1, 2>(0x820e407, // vlse32.v v8, (x1), x2, v0.t
3715 16,
3716 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3717 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170}});
3718 }
3719
TEST_F(Riscv64InterpreterTest,TestVlse32_vlmul4)3720 TEST_F(Riscv64InterpreterTest, TestVlse32_vlmul4) {
3721 TestVlssegXeXX<UInt32, 1, 4>(0x820e407, // vlse32.v v8, (x1), x2, v0.t
3722 16,
3723 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3724 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3725 {0x9604'9200, 0xb624'b220, 0xd644'd240, 0xf664'f260},
3726 {0x1684'1280, 0x36a4'32a0, 0x56c4'52c0, 0x76e4'72e0}});
3727 }
3728
TEST_F(Riscv64InterpreterTest,TestVlse32_vlmul8)3729 TEST_F(Riscv64InterpreterTest, TestVlse32_vlmul8) {
3730 TestVlssegXeXX<UInt32, 1, 8>(0x820e407, // vlse32.v v8, (x1), x2, v0.t
3731 8,
3732 {{0x8302'8100, 0x8b0a'8908, 0x9312'9110, 0x9b1a'9918},
3733 {0xa322'a120, 0xab2a'a928, 0xb332'b130, 0xbb3a'b938},
3734 {0xc342'c140, 0xcb4a'c948, 0xd352'd150, 0xdb5a'd958},
3735 {0xe362'e160, 0xeb6a'e968, 0xf372'f170, 0xfb7a'f978},
3736 {0x9604'9200, 0x8614'8211, 0xb624'b220, 0xa634'a231},
3737 {0xd644'd240, 0xc654'c251, 0xf664'f260, 0xe674'e271},
3738 {0x1684'1280, 0x0694'0291, 0x36a4'32a0, 0x26b4'22b1},
3739 {0x56c4'52c0, 0x46d4'42d1, 0x76e4'72e0, 0x66f4'62f1}});
3740 }
3741
TEST_F(Riscv64InterpreterTest,TestVlsseg2e32_vlmul1)3742 TEST_F(Riscv64InterpreterTest, TestVlsseg2e32_vlmul1) {
3743 TestVlssegXeXX<UInt32, 2, 1>(0x2820e407, // vlsseg2e32.v v8, (x1), x2, v0.t
3744 16,
3745 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3746 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534}});
3747 }
3748
TEST_F(Riscv64InterpreterTest,TestVlsseg2e32_vlmul2)3749 TEST_F(Riscv64InterpreterTest, TestVlsseg2e32_vlmul2) {
3750 TestVlssegXeXX<UInt32, 2, 2>(0x2820e407, // vlsseg2e32.v v8, (x1), x2, v0.t
3751 16,
3752 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3753 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3754 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3755 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574}});
3756 }
3757
TEST_F(Riscv64InterpreterTest,TestVlsseg2e32_vlmul4)3758 TEST_F(Riscv64InterpreterTest, TestVlsseg2e32_vlmul4) {
3759 TestVlssegXeXX<UInt32, 2, 4>(0x2820e407, // vlsseg2e32.v v8, (x1), x2, v0.t
3760 16,
3761 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3762 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3763 {0x9604'9200, 0xb624'b220, 0xd644'd240, 0xf664'f260},
3764 {0x1684'1280, 0x36a4'32a0, 0x56c4'52c0, 0x76e4'72e0},
3765 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3766 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574},
3767 {0x9e0c'9a09, 0xbe2c'ba29, 0xde4c'da49, 0xfe6c'fa69},
3768 {0x1e8c'1a89, 0x3eac'3aa9, 0x5ecc'5ac9, 0x7eec'7ae9}});
3769 }
3770
TEST_F(Riscv64InterpreterTest,TestVlsseg3e32_vlmul1)3771 TEST_F(Riscv64InterpreterTest, TestVlsseg3e32_vlmul1) {
3772 TestVlssegXeXX<UInt32, 3, 1>(0x4820e407, // vlsseg3e32.v v8, (x1), x2, v0.t
3773 16,
3774 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3775 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3776 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938}});
3777 }
3778
TEST_F(Riscv64InterpreterTest,TestVlsseg3e32_vlmul2)3779 TEST_F(Riscv64InterpreterTest, TestVlsseg3e32_vlmul2) {
3780 TestVlssegXeXX<UInt32, 3, 2>(0x4820e407, // vlsseg3e32.v v8, (x1), x2, v0.t
3781 16,
3782 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3783 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3784 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3785 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574},
3786 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3787 {0xcb4a'c948, 0xdb5a'd958, 0xeb6a'e968, 0xfb7a'f978}});
3788 }
3789
TEST_F(Riscv64InterpreterTest,TestVlsseg4e32_vlmul1)3790 TEST_F(Riscv64InterpreterTest, TestVlsseg4e32_vlmul1) {
3791 TestVlssegXeXX<UInt32, 4, 1>(0x6820e407, // vlsseg4e32.v v8, (x1), x2, v0.t
3792 16,
3793 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3794 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3795 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3796 {0x8f0e'8d0c, 0x9f1e'9d1c, 0xaf2e'ad2c, 0xbf3e'bd3c}});
3797 }
3798
TEST_F(Riscv64InterpreterTest,TestVlsseg4e32_vlmul2)3799 TEST_F(Riscv64InterpreterTest, TestVlsseg4e32_vlmul2) {
3800 TestVlssegXeXX<UInt32, 4, 2>(0x6820e407, // vlsseg4e32.v v8, (x1), x2, v0.t
3801 16,
3802 {{0x8302'8100, 0x9312'9110, 0xa322'a120, 0xb332'b130},
3803 {0xc342'c140, 0xd352'd150, 0xe362'e160, 0xf372'f170},
3804 {0x8706'8504, 0x9716'9514, 0xa726'a524, 0xb736'b534},
3805 {0xc746'c544, 0xd756'd554, 0xe766'e564, 0xf776'f574},
3806 {0x8b0a'8908, 0x9b1a'9918, 0xab2a'a928, 0xbb3a'b938},
3807 {0xcb4a'c948, 0xdb5a'd958, 0xeb6a'e968, 0xfb7a'f978},
3808 {0x8f0e'8d0c, 0x9f1e'9d1c, 0xaf2e'ad2c, 0xbf3e'bd3c},
3809 {0xcf4e'cd4c, 0xdf5e'dd5c, 0xef6e'ed6c, 0xff7e'fd7c}});
3810 }
3811
TEST_F(Riscv64InterpreterTest,TestVlsseg5e32)3812 TEST_F(Riscv64InterpreterTest, TestVlsseg5e32) {
3813 TestVlssegXeXX<UInt32, 5, 1>(0x8820e407, // vlsseg5e32.v v8, (x1), x2, v0.t
3814 32,
3815 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3816 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3817 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3818 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3819 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170}});
3820 }
3821
TEST_F(Riscv64InterpreterTest,TestVlsseg6e32)3822 TEST_F(Riscv64InterpreterTest, TestVlsseg6e32) {
3823 TestVlssegXeXX<UInt32, 6, 1>(0xa820e407, // vlsseg6e32.v v8, (x1), x2, v0.t
3824 32,
3825 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3826 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3827 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3828 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3829 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170},
3830 {0x9716'9514, 0xb736'b534, 0xd756'd554, 0xf776'f574}});
3831 }
3832
TEST_F(Riscv64InterpreterTest,TestVlsseg7e32)3833 TEST_F(Riscv64InterpreterTest, TestVlsseg7e32) {
3834 TestVlssegXeXX<UInt32, 7, 1>(0xc820e407, // vlsseg7e32.v v8, (x1), x2, v0.t
3835 32,
3836 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3837 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3838 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3839 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3840 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170},
3841 {0x9716'9514, 0xb736'b534, 0xd756'd554, 0xf776'f574},
3842 {0x9b1a'9918, 0xbb3a'b938, 0xdb5a'd958, 0xfb7a'f978}});
3843 }
3844
TEST_F(Riscv64InterpreterTest,TestVlsseg8e32)3845 TEST_F(Riscv64InterpreterTest, TestVlsseg8e32) {
3846 TestVlssegXeXX<UInt32, 8, 1>(0xe820e407, // vlsseg8e32.v v8, (x1), x2, v0.t
3847 32,
3848 {{0x8302'8100, 0xa322'a120, 0xc342'c140, 0xe362'e160},
3849 {0x8706'8504, 0xa726'a524, 0xc746'c544, 0xe766'e564},
3850 {0x8b0a'8908, 0xab2a'a928, 0xcb4a'c948, 0xeb6a'e968},
3851 {0x8f0e'8d0c, 0xaf2e'ad2c, 0xcf4e'cd4c, 0xef6e'ed6c},
3852 {0x9312'9110, 0xb332'b130, 0xd352'd150, 0xf372'f170},
3853 {0x9716'9514, 0xb736'b534, 0xd756'd554, 0xf776'f574},
3854 {0x9b1a'9918, 0xbb3a'b938, 0xdb5a'd958, 0xfb7a'f978},
3855 {0x9f1e'9d1c, 0xbf3e'bd3c, 0xdf5e'dd5c, 0xff7e'fd7c}});
3856 }
3857
TEST_F(Riscv64InterpreterTest,TestVlse64_vlmul1)3858 TEST_F(Riscv64InterpreterTest, TestVlse64_vlmul1) {
3859 TestVlssegXeXX<UInt64, 1, 1>(0x820f407, // vlse64.v v8, (x1), x2, v0.t
3860 32,
3861 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120}});
3862 }
3863
TEST_F(Riscv64InterpreterTest,TestVlse64_vlmul2)3864 TEST_F(Riscv64InterpreterTest, TestVlse64_vlmul2) {
3865 TestVlssegXeXX<UInt64, 1, 2>(0x820f407, // vlse64.v v8, (x1), x2, v0.t
3866 32,
3867 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3868 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160}});
3869 }
3870
TEST_F(Riscv64InterpreterTest,TestVlse64_vlmul4)3871 TEST_F(Riscv64InterpreterTest, TestVlse64_vlmul4) {
3872 TestVlssegXeXX<UInt64, 1, 4>(0x820f407, // vlse64.v v8, (x1), x2, v0.t
3873 32,
3874 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3875 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3876 {0x9e0c'9a09'9604'9200, 0xde4c'da49'd644'd240},
3877 {0x1e8c'1a89'1684'1280, 0x5ecc'5ac9'56c4'52c0}});
3878 }
3879
TEST_F(Riscv64InterpreterTest,TestVlse64_vlmul8)3880 TEST_F(Riscv64InterpreterTest, TestVlse64_vlmul8) {
3881 TestVlssegXeXX<UInt64, 1, 8>(0x820f407, // vlse64.v v8, (x1), x2, v0.t
3882 16,
3883 {{0x8706'8504'8302'8100, 0x9716'9514'9312'9110},
3884 {0xa726'a524'a322'a120, 0xb736'b534'b332'b130},
3885 {0xc746'c544'c342'c140, 0xd756'd554'd352'd150},
3886 {0xe766'e564'e362'e160, 0xf776'f574'f372'f170},
3887 {0x9e0c'9a09'9604'9200, 0xbe2c'ba29'b624'b220},
3888 {0xde4c'da49'd644'd240, 0xfe6c'fa69'f664'f260},
3889 {0x1e8c'1a89'1684'1280, 0x3eac'3aa9'36a4'32a0},
3890 {0x5ecc'5ac9'56c4'52c0, 0x7eec'7ae9'76e4'72e0}});
3891 }
3892
TEST_F(Riscv64InterpreterTest,TestVlsseg2e64_vlmul1)3893 TEST_F(Riscv64InterpreterTest, TestVlsseg2e64_vlmul1) {
3894 TestVlssegXeXX<UInt64, 2, 1>(0x2820f407, // vlsseg2e64.v v8, (x1), x2, v0.t
3895 32,
3896 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3897 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928}});
3898 }
3899
TEST_F(Riscv64InterpreterTest,TestVlsseg2e64_vlmul2)3900 TEST_F(Riscv64InterpreterTest, TestVlsseg2e64_vlmul2) {
3901 TestVlssegXeXX<UInt64, 2, 2>(0x2820f407, // vlsseg2e64.v v8, (x1), x2, v0.t
3902 32,
3903 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3904 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3905 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3906 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968}});
3907 }
3908
TEST_F(Riscv64InterpreterTest,TestVlsseg2e64_vlmul4)3909 TEST_F(Riscv64InterpreterTest, TestVlsseg2e64_vlmul4) {
3910 TestVlssegXeXX<UInt64, 2, 4>(0x2820f407, // vlsseg2e64.v v8, (x1), x2, v0.t
3911 32,
3912 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3913 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3914 {0x9e0c'9a09'9604'9200, 0xde4c'da49'd644'd240},
3915 {0x1e8c'1a89'1684'1280, 0x5ecc'5ac9'56c4'52c0},
3916 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3917 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968},
3918 {0x8e1c'8a18'8614'8211, 0xce5c'ca58'c654'c251},
3919 {0x0e9c'0a98'0694'0291, 0x4edc'4ad8'46d4'42d1}});
3920 }
3921
TEST_F(Riscv64InterpreterTest,TestVlsseg3e64_vlmul1)3922 TEST_F(Riscv64InterpreterTest, TestVlsseg3e64_vlmul1) {
3923 TestVlssegXeXX<UInt64, 3, 1>(0x4820f407, // vlsseg3e64.v v8, (x1), x2, v0.t
3924 32,
3925 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3926 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3927 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130}});
3928 }
3929
TEST_F(Riscv64InterpreterTest,TestVlsseg3e64_vlmul2)3930 TEST_F(Riscv64InterpreterTest, TestVlsseg3e64_vlmul2) {
3931 TestVlssegXeXX<UInt64, 3, 2>(0x4820f407, // vlsseg3e64.v v8, (x1), x2, v0.t
3932 32,
3933 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3934 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3935 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3936 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968},
3937 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3938 {0xd756'd554'd352'd150, 0xf776'f574'f372'f170}});
3939 }
3940
TEST_F(Riscv64InterpreterTest,TestVlsseg4e64_vlmul1)3941 TEST_F(Riscv64InterpreterTest, TestVlsseg4e64_vlmul1) {
3942 TestVlssegXeXX<UInt64, 4, 1>(0x6820f407, // vlsseg4e64.v v8, (x1), x2, v0.t
3943 32,
3944 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3945 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3946 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3947 {0x9f1e'9d1c'9b1a'9918, 0xbf3e'bd3c'bb3a'b938}});
3948 }
3949
TEST_F(Riscv64InterpreterTest,TestVlsseg4e64_vlmul2)3950 TEST_F(Riscv64InterpreterTest, TestVlsseg4e64_vlmul2) {
3951 TestVlssegXeXX<UInt64, 4, 2>(0x6820f407, // vlsseg4e64.v v8, (x1), x2, v0.t
3952 32,
3953 {{0x8706'8504'8302'8100, 0xa726'a524'a322'a120},
3954 {0xc746'c544'c342'c140, 0xe766'e564'e362'e160},
3955 {0x8f0e'8d0c'8b0a'8908, 0xaf2e'ad2c'ab2a'a928},
3956 {0xcf4e'cd4c'cb4a'c948, 0xef6e'ed6c'eb6a'e968},
3957 {0x9716'9514'9312'9110, 0xb736'b534'b332'b130},
3958 {0xd756'd554'd352'd150, 0xf776'f574'f372'f170},
3959 {0x9f1e'9d1c'9b1a'9918, 0xbf3e'bd3c'bb3a'b938},
3960 {0xdf5e'dd5c'db5a'd958, 0xff7e'fd7c'fb7a'f978}});
3961 }
3962
TEST_F(Riscv64InterpreterTest,TestVlsseg5e64)3963 TEST_F(Riscv64InterpreterTest, TestVlsseg5e64) {
3964 TestVlssegXeXX<UInt64, 5, 1>(0x8820f407, // vlsseg5e64.v v8, (x1), x2, v0.t
3965 64,
3966 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3967 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3968 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3969 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3970 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160}});
3971 }
3972
TEST_F(Riscv64InterpreterTest,TestVlsseg6e64)3973 TEST_F(Riscv64InterpreterTest, TestVlsseg6e64) {
3974 TestVlssegXeXX<UInt64, 6, 1>(0xa820f407, // vlsseg6e64.v v8, (x1), x2, v0.t
3975 64,
3976 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3977 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3978 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3979 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3980 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160},
3981 {0xaf2e'ad2c'ab2a'a928, 0xef6e'ed6c'eb6a'e968}});
3982 }
3983
TEST_F(Riscv64InterpreterTest,TestVlsseg7e64)3984 TEST_F(Riscv64InterpreterTest, TestVlsseg7e64) {
3985 TestVlssegXeXX<UInt64, 7, 1>(0xc820f407, // vlsseg7e64.v v8, (x1), x2, v0.t
3986 64,
3987 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
3988 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
3989 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
3990 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
3991 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160},
3992 {0xaf2e'ad2c'ab2a'a928, 0xef6e'ed6c'eb6a'e968},
3993 {0xb736'b534'b332'b130, 0xf776'f574'f372'f170}});
3994 }
3995
TEST_F(Riscv64InterpreterTest,TestVlsseg8e64)3996 TEST_F(Riscv64InterpreterTest, TestVlsseg8e64) {
3997 TestVlssegXeXX<UInt64, 8, 1>(0xe820f407, // vlsseg8e64.v v8, (x1), x2, v0.t
3998 64,
3999 {{0x8706'8504'8302'8100, 0xc746'c544'c342'c140},
4000 {0x8f0e'8d0c'8b0a'8908, 0xcf4e'cd4c'cb4a'c948},
4001 {0x9716'9514'9312'9110, 0xd756'd554'd352'd150},
4002 {0x9f1e'9d1c'9b1a'9918, 0xdf5e'dd5c'db5a'd958},
4003 {0xa726'a524'a322'a120, 0xe766'e564'e362'e160},
4004 {0xaf2e'ad2c'ab2a'a928, 0xef6e'ed6c'eb6a'e968},
4005 {0xb736'b534'b332'b130, 0xf776'f574'f372'f170},
4006 {0xbf3e'bd3c'bb3a'b938, 0xff7e'fd7c'fb7a'f978}});
4007 }
4008
TEST_F(Riscv64InterpreterTest,TestVlm)4009 TEST_F(Riscv64InterpreterTest, TestVlm) {
4010 TestVlm(0x2b08407, // vlm.v v8, (x1)
4011 {0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143});
4012 }
4013
TEST_F(Riscv64InterpreterTest,Vsxei8_sew8_vlmul1)4014 TEST_F(Riscv64InterpreterTest, Vsxei8_sew8_vlmul1) {
4015 VsxsegXeiXX<UInt8, 1, 1>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4016 {0x0487'8506'0283'0081, 0x0a89'0c8d'8b8f'080e});
4017 }
4018
TEST_F(Riscv64InterpreterTest,Vsxei8_sew8_vlmul2)4019 TEST_F(Riscv64InterpreterTest, Vsxei8_sew8_vlmul2) {
4020 VsxsegXeiXX<UInt8, 1, 2>(
4021 0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4022 {0x0487'8506'0283'0081, 0x0a89'0c8d'8b8f'080e, 0x9f93'9b1e'9714'121a, 0x9110'1899'1c95'169d});
4023 }
4024
TEST_F(Riscv64InterpreterTest,Vsxei8_sew8_vlmul4)4025 TEST_F(Riscv64InterpreterTest, Vsxei8_sew8_vlmul4) {
4026 VsxsegXeiXX<UInt8, 1, 4>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4027 {0x0487'8506'0283'0081,
4028 0x0a89'0c8d'8b8f'080e,
4029 0x9f93'9b1e'9714'121a,
4030 0x9110'1899'1c95'169d,
4031 0x2ea5'bd2c'30a3'38b9,
4032 0xafad'3e20'a728'b1ab,
4033 0x3626'b722'b5a1'bbbf,
4034 0xa932'2434'b33a'2a3c});
4035 }
4036
TEST_F(Riscv64InterpreterTest,Vsxei8_sew8_vlmul8)4037 TEST_F(Riscv64InterpreterTest, Vsxei8_sew8_vlmul8) {
4038 VsxsegXeiXX<UInt8, 1, 8>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4039 {0x0487'8506'0283'0081,
4040 0x0a89'0c8d'8b8f'080e,
4041 0x9f93'9b1e'9714'121a,
4042 0x9110'1899'1c95'169d,
4043 0x2ea5'bd2c'30a3'38b9,
4044 0xafad'3e20'a728'b1ab,
4045 0x3626'b722'b5a1'bbbf,
4046 0xa932'2434'b33a'2a3c,
4047 0x6aed'ddd1'e35c'66c7,
4048 0xd542'72e1'4674'4ed3,
4049 0x78ef'd9e7'7a7e'eb76,
4050 0xfbf9'f5c1'6e5a'c5ff,
4051 0x52cd'c362'6c48'dfd7,
4052 0x4a54'50fd'f3f7'cf68,
4053 0x56cb'e57c'7044'60c9,
4054 0xf1db'6440'58e9'4c5e});
4055 }
4056
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew8_vlmul1)4057 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew8_vlmul1) {
4058 VsxsegXeiXX<UInt8, 2, 1>(
4059 0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4060 {0x1202'9383'1000'9181, 0x1404'9787'9585'1606, 0x9b8b'9f8f'1808'1e0e, 0x1a0a'9989'1c0c'9d8d});
4061 }
4062
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew8_vlmul2)4063 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew8_vlmul2) {
4064 VsxsegXeiXX<UInt8, 2, 2>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4065 {0x2202'a383'2000'a181,
4066 0x2404'a787'a585'2606,
4067 0xab8b'af8f'2808'2e0e,
4068 0x2a0a'a989'2c0c'ad8d,
4069 0xb797'3414'3212'3a1a,
4070 0xbf9f'b393'bb9b'3e1e,
4071 0x3c1c'b595'3616'bd9d,
4072 0xb191'3010'3818'b999});
4073 }
4074
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew8_vlmul4)4075 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew8_vlmul4) {
4076 VsxsegXeiXX<UInt8, 2, 4>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4077 {0x4202'c383'4000'c181,
4078 0x4404'c787'c585'4606,
4079 0xcb8b'cf8f'4808'4e0e,
4080 0x4a0a'c989'4c0c'cd8d,
4081 0xd797'5414'5212'5a1a,
4082 0xdf9f'd393'db9b'5e1e,
4083 0x5c1c'd595'5616'dd9d,
4084 0xd191'5010'5818'd999,
4085 0x7030'e3a3'7838'f9b9,
4086 0x6e2e'e5a5'fdbd'6c2c,
4087 0xe7a7'6828'f1b1'ebab,
4088 0xefaf'edad'7e3e'6020,
4089 0xf5b5'e1a1'fbbb'ffbf,
4090 0x7636'6626'f7b7'6222,
4091 0xf3b3'7a3a'6a2a'7c3c,
4092 0xe9a9'7232'6424'7434});
4093 }
4094
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew8_vlmul1)4095 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew8_vlmul1) {
4096 VsxsegXeiXX<UInt8, 3, 1>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4097 {0x9383'2010'00a1'9181,
4098 0x8526'1606'2212'02a3,
4099 0x2414'04a7'9787'a595,
4100 0x9f8f'2818'082e'1e0e,
4101 0x0cad'9d8d'ab9b'8baf,
4102 0x2a1a'0aa9'9989'2c1c});
4103 }
4104
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew8_vlmul2)4105 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew8_vlmul2) {
4106 VsxsegXeiXX<UInt8, 3, 2>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4107 {0xa383'4020'00c1'a181,
4108 0x8546'2606'4222'02c3,
4109 0x4424'04c7'a787'c5a5,
4110 0xaf8f'4828'084e'2e0e,
4111 0x0ccd'ad8d'cbab'8bcf,
4112 0x4a2a'0ac9'a989'4c2c,
4113 0x3414'5232'125a'3a1a,
4114 0x9b5e'3e1e'd7b7'9754,
4115 0xdfbf'9fd3'b393'dbbb,
4116 0xb595'5636'16dd'bd9d,
4117 0x18d9'b999'5c3c'1cd5,
4118 0xd1b1'9150'3010'5838});
4119 }
4120
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew8_vlmul1)4121 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew8_vlmul1) {
4122 VsxsegXeiXX<UInt8, 4, 1>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4123 {0x3020'1000'b1a1'9181,
4124 0x3222'1202'b3a3'9383,
4125 0xb5a5'9585'3626'1606,
4126 0x3424'1404'b7a7'9787,
4127 0x3828'1808'3e2e'1e0e,
4128 0xbbab'9b8b'bfaf'9f8f,
4129 0x3c2c'1c0c'bdad'9d8d,
4130 0x3a2a'1a0a'b9a9'9989});
4131 }
4132
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew8_vlmul2)4133 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew8_vlmul2) {
4134 VsxsegXeiXX<UInt8, 4, 2>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4135 {0x6040'2000'e1c1'a181,
4136 0x6242'2202'e3c3'a383,
4137 0xe5c5'a585'6646'2606,
4138 0x6444'2404'e7c7'a787,
4139 0x6848'2808'6e4e'2e0e,
4140 0xebcb'ab8b'efcf'af8f,
4141 0x6c4c'2c0c'edcd'ad8d,
4142 0x6a4a'2a0a'e9c9'a989,
4143 0x7252'3212'7a5a'3a1a,
4144 0xf7d7'b797'7454'3414,
4145 0xfbdb'bb9b'7e5e'3e1e,
4146 0xffdf'bf9f'f3d3'b393,
4147 0x7656'3616'fddd'bd9d,
4148 0x7c5c'3c1c'f5d5'b595,
4149 0x7858'3818'f9d9'b999,
4150 0xf1d1'b191'7050'3010});
4151 }
4152
TEST_F(Riscv64InterpreterTest,Vsxseg5eiXX_sew8)4153 TEST_F(Riscv64InterpreterTest, Vsxseg5eiXX_sew8) {
4154 VsxsegXeiXX<UInt8, 5, 1>(0x85008427, // Vsuxseg5ei8.v v8, (x1), v16, v0.t
4155 {0x2010'00c1'b1a1'9181,
4156 0x02c3'b3a3'9383'4030,
4157 0x3626'1606'4232'2212,
4158 0x9787'c5b5'a595'8546,
4159 0x4434'2414'04c7'b7a7,
4160 0x2818'084e'3e2e'1e0e,
4161 0x8bcf'bfaf'9f8f'4838,
4162 0xbdad'9d8d'cbbb'ab9b,
4163 0x9989'4c3c'2c1c'0ccd,
4164 0x4a3a'2a1a'0ac9'b9a9});
4165 }
4166
TEST_F(Riscv64InterpreterTest,Vsxseg6eiXX_sew8)4167 TEST_F(Riscv64InterpreterTest, Vsxseg6eiXX_sew8) {
4168 VsxsegXeiXX<UInt8, 6, 1>(0xa5008427, // Vsuxseg6ei8.v v8, (x1), v16, v0.t
4169 {0x1000'd1c1'b1a1'9181,
4170 0xb3a3'9383'5040'3020,
4171 0x5242'3222'1202'd3c3,
4172 0x9585'5646'3626'1606,
4173 0xb7a7'9787'd5c5'b5a5,
4174 0x5444'3424'1404'd7c7,
4175 0x1808'5e4e'3e2e'1e0e,
4176 0xbfaf'9f8f'5848'3828,
4177 0xdbcb'bbab'9b8b'dfcf,
4178 0x1c0c'ddcd'bdad'9d8d,
4179 0xb9a9'9989'5c4c'3c2c,
4180 0x5a4a'3a2a'1a0a'd9c9});
4181 }
4182
TEST_F(Riscv64InterpreterTest,Vsxseg7eiXX_sew8)4183 TEST_F(Riscv64InterpreterTest, Vsxseg7eiXX_sew8) {
4184 VsxsegXeiXX<UInt8, 7, 1>(0xc5008427, // Vsuxseg7ei8.v v8, (x1), v16, v0.t
4185 {0x00e1'd1c1'b1a1'9181,
4186 0x9383'6050'4030'2010,
4187 0x2212'02e3'd3c3'b3a3,
4188 0x3626'1606'6252'4232,
4189 0xc5b5'a595'8566'5646,
4190 0xd7c7'b7a7'9787'e5d5,
4191 0x6454'4434'2414'04e7,
4192 0x086e'5e4e'3e2e'1e0e,
4193 0x9f8f'6858'4838'2818,
4194 0xab9b'8bef'dfcf'bfaf,
4195 0xbdad'9d8d'ebdb'cbbb,
4196 0x4c3c'2c1c'0ced'ddcd,
4197 0xd9c9'b9a9'9989'6c5c,
4198 0x6a5a'4a3a'2a1a'0ae9});
4199 }
4200
TEST_F(Riscv64InterpreterTest,Vsxseg8eiXX_sew8)4201 TEST_F(Riscv64InterpreterTest, Vsxseg8eiXX_sew8) {
4202 VsxsegXeiXX<UInt8, 8, 1>(0xe5008427, // Vsuxseg8ei8.v v8, (x1), v16, v0.t
4203 {0xf1e1'd1c1'b1a1'9181,
4204 0x7060'5040'3020'1000,
4205 0xf3e3'd3c3'b3a3'9383,
4206 0x7262'5242'3222'1202,
4207 0x7666'5646'3626'1606,
4208 0xf5e5'd5c5'b5a5'9585,
4209 0xf7e7'd7c7'b7a7'9787,
4210 0x7464'5444'3424'1404,
4211 0x7e6e'5e4e'3e2e'1e0e,
4212 0x7868'5848'3828'1808,
4213 0xffef'dfcf'bfaf'9f8f,
4214 0xfbeb'dbcb'bbab'9b8b,
4215 0xfded'ddcd'bdad'9d8d,
4216 0x7c6c'5c4c'3c2c'1c0c,
4217 0xf9e9'd9c9'b9a9'9989,
4218 0x7a6a'5a4a'3a2a'1a0a});
4219 }
4220
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew16_vlmul1)4221 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew16_vlmul1) {
4222 VsxsegXeiXX<UInt16, 1, 1>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4223 {0x8504'8706'8100'8302, 0x8908'8f0e'8b0a'8d0c});
4224 }
4225
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew16_vlmul2)4226 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew16_vlmul2) {
4227 VsxsegXeiXX<UInt16, 1, 2>(
4228 0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4229 {0x8504'8706'8100'8302, 0x8908'8f0e'8b0a'8d0c, 0x9716'9f1e'9110'9d1c, 0x9514'9312'9918'9b1a});
4230 }
4231
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew16_vlmul4)4232 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew16_vlmul4) {
4233 VsxsegXeiXX<UInt16, 1, 4>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4234 {0x8504'8706'8100'8302,
4235 0x8908'8f0e'8b0a'8d0c,
4236 0x9716'9f1e'9110'9d1c,
4237 0x9514'9312'9918'9b1a,
4238 0xaf2e'a928'a524'b534,
4239 0xbf3e'a726'b736'bd3c,
4240 0xb938'ab2a'ad2c'bb3a,
4241 0xa322'a120'b130'b332});
4242 }
4243
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew16_vlmul8)4244 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew16_vlmul8) {
4245 VsxsegXeiXX<UInt16, 1, 8>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4246 {0x8504'8706'8100'8302,
4247 0x8908'8f0e'8b0a'8d0c,
4248 0x9716'9f1e'9110'9d1c,
4249 0x9514'9312'9918'9b1a,
4250 0xaf2e'a928'a524'b534,
4251 0xbf3e'a726'b736'bd3c,
4252 0xb938'ab2a'ad2c'bb3a,
4253 0xa322'a120'b130'b332,
4254 0xe160'c746'f170'f372,
4255 0xdd5c'cb4a'fb7a'd958,
4256 0xcf4e'd150'e362'd756,
4257 0xdf5e'db5a'fd7c'c140,
4258 0xeb6a'c342'f776'ff7e,
4259 0xed6c'cd4c'ef6e'c544,
4260 0xe766'f574'd554'f978,
4261 0xd352'e564'c948'e968});
4262 }
4263
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew16_vlmul1)4264 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew16_vlmul1) {
4265 VsxsegXeiXX<UInt16, 2, 1>(
4266 0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4267 {0x9110'8100'9312'8302, 0x9514'8504'9716'8706, 0x9b1a'8b0a'9d1c'8d0c, 0x9918'8908'9f1e'8f0e});
4268 }
4269
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew16_vlmul2)4270 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew16_vlmul2) {
4271 VsxsegXeiXX<UInt16, 2, 2>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4272 {0xa120'8100'a322'8302,
4273 0xa524'8504'a726'8706,
4274 0xab2a'8b0a'ad2c'8d0c,
4275 0xa928'8908'af2e'8f0e,
4276 0xb130'9110'bd3c'9d1c,
4277 0xb736'9716'bf3e'9f1e,
4278 0xb938'9918'bb3a'9b1a,
4279 0xb534'9514'b332'9312});
4280 }
4281
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew16_vlmul4)4282 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew16_vlmul4) {
4283 VsxsegXeiXX<UInt16, 2, 4>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4284 {0xc140'8100'c342'8302,
4285 0xc544'8504'c746'8706,
4286 0xcb4a'8b0a'cd4c'8d0c,
4287 0xc948'8908'cf4e'8f0e,
4288 0xd150'9110'dd5c'9d1c,
4289 0xd756'9716'df5e'9f1e,
4290 0xd958'9918'db5a'9b1a,
4291 0xd554'9514'd352'9312,
4292 0xe564'a524'f574'b534,
4293 0xef6e'af2e'e968'a928,
4294 0xf776'b736'fd7c'bd3c,
4295 0xff7e'bf3e'e766'a726,
4296 0xed6c'ad2c'fb7a'bb3a,
4297 0xf978'b938'eb6a'ab2a,
4298 0xf170'b130'f372'b332,
4299 0xe362'a322'e160'a120});
4300 }
4301
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew16_vlmul1)4302 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew16_vlmul1) {
4303 VsxsegXeiXX<UInt16, 3, 1>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4304 {0x8100'a322'9312'8302,
4305 0x9716'8706'a120'9110,
4306 0xa524'9514'8504'a726,
4307 0x8b0a'ad2c'9d1c'8d0c,
4308 0x9f1e'8f0e'ab2a'9b1a,
4309 0xa928'9918'8908'af2e});
4310 }
4311
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew16_vlmul2)4312 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew16_vlmul2) {
4313 VsxsegXeiXX<UInt16, 3, 2>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4314 {0x8100'c342'a322'8302,
4315 0xa726'8706'c140'a120,
4316 0xc544'a524'8504'c746,
4317 0x8b0a'cd4c'ad2c'8d0c,
4318 0xaf2e'8f0e'cb4a'ab2a,
4319 0xc948'a928'8908'cf4e,
4320 0x9110'dd5c'bd3c'9d1c,
4321 0xbf3e'9f1e'd150'b130,
4322 0xd756'b736'9716'df5e,
4323 0x9918'db5a'bb3a'9b1a,
4324 0xb332'9312'd958'b938,
4325 0xd554'b534'9514'd352});
4326 }
4327
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew16_vlmul1)4328 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew16_vlmul1) {
4329 VsxsegXeiXX<UInt16, 4, 1>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4330 {0xb332'a322'9312'8302,
4331 0xb130'a120'9110'8100,
4332 0xb736'a726'9716'8706,
4333 0xb534'a524'9514'8504,
4334 0xbd3c'ad2c'9d1c'8d0c,
4335 0xbb3a'ab2a'9b1a'8b0a,
4336 0xbf3e'af2e'9f1e'8f0e,
4337 0xb938'a928'9918'8908});
4338 }
4339
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew16_vlmul2)4340 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew16_vlmul2) {
4341 VsxsegXeiXX<UInt16, 4, 2>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4342 {0xe362'c342'a322'8302,
4343 0xe160'c140'a120'8100,
4344 0xe766'c746'a726'8706,
4345 0xe564'c544'a524'8504,
4346 0xed6c'cd4c'ad2c'8d0c,
4347 0xeb6a'cb4a'ab2a'8b0a,
4348 0xef6e'cf4e'af2e'8f0e,
4349 0xe968'c948'a928'8908,
4350 0xfd7c'dd5c'bd3c'9d1c,
4351 0xf170'd150'b130'9110,
4352 0xff7e'df5e'bf3e'9f1e,
4353 0xf776'd756'b736'9716,
4354 0xfb7a'db5a'bb3a'9b1a,
4355 0xf978'd958'b938'9918,
4356 0xf372'd352'b332'9312,
4357 0xf574'd554'b534'9514});
4358 }
4359
TEST_F(Riscv64InterpreterTest,Vsxseg5eiXX_sew16)4360 TEST_F(Riscv64InterpreterTest, Vsxseg5eiXX_sew16) {
4361 VsxsegXeiXX<UInt16, 5, 1>(0x85008427, // Vsuxseg5ei8.v v8, (x1), v16, v0.t
4362 {0xb332'a322'9312'8302,
4363 0xa120'9110'8100'c342,
4364 0x9716'8706'c140'b130,
4365 0x8504'c746'b736'a726,
4366 0xc544'b534'a524'9514,
4367 0xbd3c'ad2c'9d1c'8d0c,
4368 0xab2a'9b1a'8b0a'cd4c,
4369 0x9f1e'8f0e'cb4a'bb3a,
4370 0x8908'cf4e'bf3e'af2e,
4371 0xc948'b938'a928'9918});
4372 }
4373
TEST_F(Riscv64InterpreterTest,Vsxseg6eiXX_sew16)4374 TEST_F(Riscv64InterpreterTest, Vsxseg6eiXX_sew16) {
4375 VsxsegXeiXX<UInt16, 6, 1>(0xa5008427, // Vsuxseg6ei8.v v8, (x1), v16, v0.t
4376 {0xb332'a322'9312'8302,
4377 0x9110'8100'd352'c342,
4378 0xd150'c140'b130'a120,
4379 0xb736'a726'9716'8706,
4380 0x9514'8504'd756'c746,
4381 0xd554'c544'b534'a524,
4382 0xbd3c'ad2c'9d1c'8d0c,
4383 0x9b1a'8b0a'dd5c'cd4c,
4384 0xdb5a'cb4a'bb3a'ab2a,
4385 0xbf3e'af2e'9f1e'8f0e,
4386 0x9918'8908'df5e'cf4e,
4387 0xd958'c948'b938'a928});
4388 }
4389
TEST_F(Riscv64InterpreterTest,Vsxseg7eiXX_sew16)4390 TEST_F(Riscv64InterpreterTest, Vsxseg7eiXX_sew16) {
4391 VsxsegXeiXX<UInt16, 7, 1>(0xc5008427, // Vsuxseg7ei8.v v8, (x1), v16, v0.t
4392 {0xb332'a322'9312'8302,
4393 0x8100'e362'd352'c342,
4394 0xc140'b130'a120'9110,
4395 0x9716'8706'e160'd150,
4396 0xd756'c746'b736'a726,
4397 0xa524'9514'8504'e766,
4398 0xe564'd554'c544'b534,
4399 0xbd3c'ad2c'9d1c'8d0c,
4400 0x8b0a'ed6c'dd5c'cd4c,
4401 0xcb4a'bb3a'ab2a'9b1a,
4402 0x9f1e'8f0e'eb6a'db5a,
4403 0xdf5e'cf4e'bf3e'af2e,
4404 0xa928'9918'8908'ef6e,
4405 0xe968'd958'c948'b938});
4406 }
4407
TEST_F(Riscv64InterpreterTest,Vsxseg8eiXX_sew16)4408 TEST_F(Riscv64InterpreterTest, Vsxseg8eiXX_sew16) {
4409 VsxsegXeiXX<UInt16, 8, 1>(0xe5008427, // Vsuxseg8ei8.v v8, (x1), v16, v0.t
4410 {0xb332'a322'9312'8302,
4411 0xf372'e362'd352'c342,
4412 0xb130'a120'9110'8100,
4413 0xf170'e160'd150'c140,
4414 0xb736'a726'9716'8706,
4415 0xf776'e766'd756'c746,
4416 0xb534'a524'9514'8504,
4417 0xf574'e564'd554'c544,
4418 0xbd3c'ad2c'9d1c'8d0c,
4419 0xfd7c'ed6c'dd5c'cd4c,
4420 0xbb3a'ab2a'9b1a'8b0a,
4421 0xfb7a'eb6a'db5a'cb4a,
4422 0xbf3e'af2e'9f1e'8f0e,
4423 0xff7e'ef6e'df5e'cf4e,
4424 0xb938'a928'9918'8908,
4425 0xf978'e968'd958'c948});
4426 }
4427
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew32_vlmul1)4428 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew32_vlmul1) {
4429 VsxsegXeiXX<UInt32, 1, 1>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4430 {0x8302'8100'8706'8504, 0x8b0a'8908'8f0e'8d0c});
4431 }
4432
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew32_vlmul2)4433 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew32_vlmul2) {
4434 VsxsegXeiXX<UInt32, 1, 2>(
4435 0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4436 {0x8302'8100'8706'8504, 0x8b0a'8908'8f0e'8d0c, 0x9716'9514'9b1a'9918, 0x9312'9110'9f1e'9d1c});
4437 }
4438
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew32_vlmul4)4439 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew32_vlmul4) {
4440 VsxsegXeiXX<UInt32, 1, 4>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4441 {0x8302'8100'8706'8504,
4442 0x8b0a'8908'8f0e'8d0c,
4443 0x9716'9514'9b1a'9918,
4444 0x9312'9110'9f1e'9d1c,
4445 0xa322'a120'bb3a'b938,
4446 0xaf2e'ad2c'bf3e'bd3c,
4447 0xb332'b130'b736'b534,
4448 0xab2a'a928'a726'a524});
4449 }
4450
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew32_vlmul8)4451 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew32_vlmul8) {
4452 VsxsegXeiXX<UInt32, 1, 8>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4453 {0x8302'8100'8706'8504,
4454 0x8b0a'8908'8f0e'8d0c,
4455 0x9716'9514'9b1a'9918,
4456 0x9312'9110'9f1e'9d1c,
4457 0xa322'a120'bb3a'b938,
4458 0xaf2e'ad2c'bf3e'bd3c,
4459 0xb332'b130'b736'b534,
4460 0xab2a'a928'a726'a524,
4461 0xcb4a'c948'eb6a'e968,
4462 0xdf5e'dd5c'd352'd150,
4463 0xef6e'ed6c'fb7a'f978,
4464 0xff7e'fd7c'cf4e'cd4c,
4465 0xdb5a'd958'f776'f574,
4466 0xf372'f170'd756'd554,
4467 0xe362'e160'e766'e564,
4468 0xc746'c544'c342'c140});
4469 }
4470
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew32_vlmul1)4471 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew32_vlmul1) {
4472 VsxsegXeiXX<UInt32, 2, 1>(
4473 0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4474 {0x9716'9514'8706'8504, 0x9312'9110'8302'8100, 0x9f1e'9d1c'8f0e'8d0c, 0x9b1a'9918'8b0a'8908});
4475 }
4476
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew32_vlmul2)4477 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew32_vlmul2) {
4478 VsxsegXeiXX<UInt32, 2, 2>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4479 {0xa726'a524'8706'8504,
4480 0xa322'a120'8302'8100,
4481 0xaf2e'ad2c'8f0e'8d0c,
4482 0xab2a'a928'8b0a'8908,
4483 0xbb3a'b938'9b1a'9918,
4484 0xb736'b534'9716'9514,
4485 0xbf3e'bd3c'9f1e'9d1c,
4486 0xb332'b130'9312'9110});
4487 }
4488
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew32_vlmul4)4489 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew32_vlmul4) {
4490 VsxsegXeiXX<UInt32, 2, 4>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4491 {0xc746'c544'8706'8504,
4492 0xc342'c140'8302'8100,
4493 0xcf4e'cd4c'8f0e'8d0c,
4494 0xcb4a'c948'8b0a'8908,
4495 0xdb5a'd958'9b1a'9918,
4496 0xd756'd554'9716'9514,
4497 0xdf5e'dd5c'9f1e'9d1c,
4498 0xd352'd150'9312'9110,
4499 0xfb7a'f978'bb3a'b938,
4500 0xe362'e160'a322'a120,
4501 0xff7e'fd7c'bf3e'bd3c,
4502 0xef6e'ed6c'af2e'ad2c,
4503 0xf776'f574'b736'b534,
4504 0xf372'f170'b332'b130,
4505 0xe766'e564'a726'a524,
4506 0xeb6a'e968'ab2a'a928});
4507 }
4508
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew32_vlmul1)4509 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew32_vlmul1) {
4510 VsxsegXeiXX<UInt32, 3, 1>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4511 {0x9716'9514'8706'8504,
4512 0x8302'8100'a726'a524,
4513 0xa322'a120'9312'9110,
4514 0x9f1e'9d1c'8f0e'8d0c,
4515 0x8b0a'8908'af2e'ad2c,
4516 0xab2a'a928'9b1a'9918});
4517 }
4518
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew32_vlmul2)4519 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew32_vlmul2) {
4520 VsxsegXeiXX<UInt32, 3, 2>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4521 {0xa726'a524'8706'8504,
4522 0x8302'8100'c746'c544,
4523 0xc342'c140'a322'a120,
4524 0xaf2e'ad2c'8f0e'8d0c,
4525 0x8b0a'8908'cf4e'cd4c,
4526 0xcb4a'c948'ab2a'a928,
4527 0xbb3a'b938'9b1a'9918,
4528 0x9716'9514'db5a'd958,
4529 0xd756'd554'b736'b534,
4530 0xbf3e'bd3c'9f1e'9d1c,
4531 0x9312'9110'df5e'dd5c,
4532 0xd352'd150'b332'b130});
4533 }
4534
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew32_vlmul1)4535 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew32_vlmul1) {
4536 VsxsegXeiXX<UInt32, 4, 1>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4537 {0x9716'9514'8706'8504,
4538 0xb736'b534'a726'a524,
4539 0x9312'9110'8302'8100,
4540 0xb332'b130'a322'a120,
4541 0x9f1e'9d1c'8f0e'8d0c,
4542 0xbf3e'bd3c'af2e'ad2c,
4543 0x9b1a'9918'8b0a'8908,
4544 0xbb3a'b938'ab2a'a928});
4545 }
4546
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew32_vlmul2)4547 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew32_vlmul2) {
4548 VsxsegXeiXX<UInt32, 4, 2>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4549 {0xa726'a524'8706'8504,
4550 0xe766'e564'c746'c544,
4551 0xa322'a120'8302'8100,
4552 0xe362'e160'c342'c140,
4553 0xaf2e'ad2c'8f0e'8d0c,
4554 0xef6e'ed6c'cf4e'cd4c,
4555 0xab2a'a928'8b0a'8908,
4556 0xeb6a'e968'cb4a'c948,
4557 0xbb3a'b938'9b1a'9918,
4558 0xfb7a'f978'db5a'd958,
4559 0xb736'b534'9716'9514,
4560 0xf776'f574'd756'd554,
4561 0xbf3e'bd3c'9f1e'9d1c,
4562 0xff7e'fd7c'df5e'dd5c,
4563 0xb332'b130'9312'9110,
4564 0xf372'f170'd352'd150});
4565 }
4566
TEST_F(Riscv64InterpreterTest,Vsxseg5eiXX_sew32)4567 TEST_F(Riscv64InterpreterTest, Vsxseg5eiXX_sew32) {
4568 VsxsegXeiXX<UInt32, 5, 1>(0x85008427, // Vsuxseg5ei8.v v8, (x1), v16, v0.t
4569 {0x9716'9514'8706'8504,
4570 0xb736'b534'a726'a524,
4571 0x8302'8100'c746'c544,
4572 0xa322'a120'9312'9110,
4573 0xc342'c140'b332'b130,
4574 0x9f1e'9d1c'8f0e'8d0c,
4575 0xbf3e'bd3c'af2e'ad2c,
4576 0x8b0a'8908'cf4e'cd4c,
4577 0xab2a'a928'9b1a'9918,
4578 0xcb4a'c948'bb3a'b938});
4579 }
4580
TEST_F(Riscv64InterpreterTest,Vsxseg6eiXX_sew32)4581 TEST_F(Riscv64InterpreterTest, Vsxseg6eiXX_sew32) {
4582 VsxsegXeiXX<UInt32, 6, 1>(0xa5008427, // Vsuxseg6ei8.v v8, (x1), v16, v0.t
4583 {0x9716'9514'8706'8504,
4584 0xb736'b534'a726'a524,
4585 0xd756'd554'c746'c544,
4586 0x9312'9110'8302'8100,
4587 0xb332'b130'a322'a120,
4588 0xd352'd150'c342'c140,
4589 0x9f1e'9d1c'8f0e'8d0c,
4590 0xbf3e'bd3c'af2e'ad2c,
4591 0xdf5e'dd5c'cf4e'cd4c,
4592 0x9b1a'9918'8b0a'8908,
4593 0xbb3a'b938'ab2a'a928,
4594 0xdb5a'd958'cb4a'c948});
4595 }
4596
TEST_F(Riscv64InterpreterTest,Vsxseg7eiXX_sew32)4597 TEST_F(Riscv64InterpreterTest, Vsxseg7eiXX_sew32) {
4598 VsxsegXeiXX<UInt32, 7, 1>(0xc5008427, // Vsuxseg7ei8.v v8, (x1), v16, v0.t
4599 {0x9716'9514'8706'8504,
4600 0xb736'b534'a726'a524,
4601 0xd756'd554'c746'c544,
4602 0x8302'8100'e766'e564,
4603 0xa322'a120'9312'9110,
4604 0xc342'c140'b332'b130,
4605 0xe362'e160'd352'd150,
4606 0x9f1e'9d1c'8f0e'8d0c,
4607 0xbf3e'bd3c'af2e'ad2c,
4608 0xdf5e'dd5c'cf4e'cd4c,
4609 0x8b0a'8908'ef6e'ed6c,
4610 0xab2a'a928'9b1a'9918,
4611 0xcb4a'c948'bb3a'b938,
4612 0xeb6a'e968'db5a'd958});
4613 }
4614
TEST_F(Riscv64InterpreterTest,Vsxseg8eiXX_sew32)4615 TEST_F(Riscv64InterpreterTest, Vsxseg8eiXX_sew32) {
4616 VsxsegXeiXX<UInt32, 8, 1>(0xe5008427, // Vsuxseg8ei8.v v8, (x1), v16, v0.t
4617 {0x9716'9514'8706'8504,
4618 0xb736'b534'a726'a524,
4619 0xd756'd554'c746'c544,
4620 0xf776'f574'e766'e564,
4621 0x9312'9110'8302'8100,
4622 0xb332'b130'a322'a120,
4623 0xd352'd150'c342'c140,
4624 0xf372'f170'e362'e160,
4625 0x9f1e'9d1c'8f0e'8d0c,
4626 0xbf3e'bd3c'af2e'ad2c,
4627 0xdf5e'dd5c'cf4e'cd4c,
4628 0xff7e'fd7c'ef6e'ed6c,
4629 0x9b1a'9918'8b0a'8908,
4630 0xbb3a'b938'ab2a'a928,
4631 0xdb5a'd958'cb4a'c948,
4632 0xfb7a'f978'eb6a'e968});
4633 }
4634
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew64_vlmul1)4635 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew64_vlmul1) {
4636 VsxsegXeiXX<UInt64, 1, 1>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4637 {0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100});
4638 }
4639
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew64_vlmul2)4640 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew64_vlmul2) {
4641 VsxsegXeiXX<UInt64, 1, 2>(
4642 0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4643 {0x8f0e'8d0c'8b0a'8908, 0x8706'8504'8302'8100, 0x9f1e'9d1c'9b1a'9918, 0x9716'9514'9312'9110});
4644 }
4645
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew64_vlmul4)4646 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew64_vlmul4) {
4647 VsxsegXeiXX<UInt64, 1, 4>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4648 {0x8f0e'8d0c'8b0a'8908,
4649 0x8706'8504'8302'8100,
4650 0x9f1e'9d1c'9b1a'9918,
4651 0x9716'9514'9312'9110,
4652 0xb736'b534'b332'b130,
4653 0xaf2e'ad2c'ab2a'a928,
4654 0xbf3e'bd3c'bb3a'b938,
4655 0xa726'a524'a322'a120});
4656 }
4657
TEST_F(Riscv64InterpreterTest,VsxeiXX_sew64_vlmul8)4658 TEST_F(Riscv64InterpreterTest, VsxeiXX_sew64_vlmul8) {
4659 VsxsegXeiXX<UInt64, 1, 8>(0x5008427, // Vsuxei8.v v8, (x1), v16, v0.t
4660 {0x8f0e'8d0c'8b0a'8908,
4661 0x8706'8504'8302'8100,
4662 0x9f1e'9d1c'9b1a'9918,
4663 0x9716'9514'9312'9110,
4664 0xb736'b534'b332'b130,
4665 0xaf2e'ad2c'ab2a'a928,
4666 0xbf3e'bd3c'bb3a'b938,
4667 0xa726'a524'a322'a120,
4668 0xf776'f574'f372'f170,
4669 0xc746'c544'c342'c140,
4670 0xff7e'fd7c'fb7a'f978,
4671 0xdf5e'dd5c'db5a'd958,
4672 0xef6e'ed6c'eb6a'e968,
4673 0xe766'e564'e362'e160,
4674 0xcf4e'cd4c'cb4a'c948,
4675 0xd756'd554'd352'd150});
4676 }
4677
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew64_vlmul1)4678 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew64_vlmul1) {
4679 VsxsegXeiXX<UInt64, 2, 1>(
4680 0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4681 {0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918, 0x8706'8504'8302'8100, 0x9716'9514'9312'9110});
4682 }
4683
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew64_vlmul2)4684 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew64_vlmul2) {
4685 VsxsegXeiXX<UInt64, 2, 2>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4686 {0x8f0e'8d0c'8b0a'8908,
4687 0xaf2e'ad2c'ab2a'a928,
4688 0x8706'8504'8302'8100,
4689 0xa726'a524'a322'a120,
4690 0x9f1e'9d1c'9b1a'9918,
4691 0xbf3e'bd3c'bb3a'b938,
4692 0x9716'9514'9312'9110,
4693 0xb736'b534'b332'b130});
4694 }
4695
TEST_F(Riscv64InterpreterTest,Vsxseg2eiXX_sew64_vlmul4)4696 TEST_F(Riscv64InterpreterTest, Vsxseg2eiXX_sew64_vlmul4) {
4697 VsxsegXeiXX<UInt64, 2, 4>(0x25008427, // Vsuxseg2ei8.v v8, (x1), v16, v0.t
4698 {0x8f0e'8d0c'8b0a'8908,
4699 0xcf4e'cd4c'cb4a'c948,
4700 0x8706'8504'8302'8100,
4701 0xc746'c544'c342'c140,
4702 0x9f1e'9d1c'9b1a'9918,
4703 0xdf5e'dd5c'db5a'd958,
4704 0x9716'9514'9312'9110,
4705 0xd756'd554'd352'd150,
4706 0xb736'b534'b332'b130,
4707 0xf776'f574'f372'f170,
4708 0xaf2e'ad2c'ab2a'a928,
4709 0xef6e'ed6c'eb6a'e968,
4710 0xbf3e'bd3c'bb3a'b938,
4711 0xff7e'fd7c'fb7a'f978,
4712 0xa726'a524'a322'a120,
4713 0xe766'e564'e362'e160});
4714 }
4715
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew64_vlmul1)4716 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew64_vlmul1) {
4717 VsxsegXeiXX<UInt64, 3, 1>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4718 {0x8f0e'8d0c'8b0a'8908,
4719 0x9f1e'9d1c'9b1a'9918,
4720 0xaf2e'ad2c'ab2a'a928,
4721 0x8706'8504'8302'8100,
4722 0x9716'9514'9312'9110,
4723 0xa726'a524'a322'a120});
4724 }
4725
TEST_F(Riscv64InterpreterTest,Vsxseg3eiXX_sew64_vlmul2)4726 TEST_F(Riscv64InterpreterTest, Vsxseg3eiXX_sew64_vlmul2) {
4727 VsxsegXeiXX<UInt64, 3, 2>(0x45008427, // Vsuxseg3ei8.v v8, (x1), v16, v0.t
4728 {0x8f0e'8d0c'8b0a'8908,
4729 0xaf2e'ad2c'ab2a'a928,
4730 0xcf4e'cd4c'cb4a'c948,
4731 0x8706'8504'8302'8100,
4732 0xa726'a524'a322'a120,
4733 0xc746'c544'c342'c140,
4734 0x9f1e'9d1c'9b1a'9918,
4735 0xbf3e'bd3c'bb3a'b938,
4736 0xdf5e'dd5c'db5a'd958,
4737 0x9716'9514'9312'9110,
4738 0xb736'b534'b332'b130,
4739 0xd756'd554'd352'd150});
4740 }
4741
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew64_vlmul1)4742 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew64_vlmul1) {
4743 VsxsegXeiXX<UInt64, 4, 1>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4744 {0x8f0e'8d0c'8b0a'8908,
4745 0x9f1e'9d1c'9b1a'9918,
4746 0xaf2e'ad2c'ab2a'a928,
4747 0xbf3e'bd3c'bb3a'b938,
4748 0x8706'8504'8302'8100,
4749 0x9716'9514'9312'9110,
4750 0xa726'a524'a322'a120,
4751 0xb736'b534'b332'b130});
4752 }
4753
TEST_F(Riscv64InterpreterTest,Vsxseg4eiXX_sew64_vlmul2)4754 TEST_F(Riscv64InterpreterTest, Vsxseg4eiXX_sew64_vlmul2) {
4755 VsxsegXeiXX<UInt64, 4, 2>(0x65008427, // Vsuxseg4ei8.v v8, (x1), v16, v0.t
4756 {0x8f0e'8d0c'8b0a'8908,
4757 0xaf2e'ad2c'ab2a'a928,
4758 0xcf4e'cd4c'cb4a'c948,
4759 0xef6e'ed6c'eb6a'e968,
4760 0x8706'8504'8302'8100,
4761 0xa726'a524'a322'a120,
4762 0xc746'c544'c342'c140,
4763 0xe766'e564'e362'e160,
4764 0x9f1e'9d1c'9b1a'9918,
4765 0xbf3e'bd3c'bb3a'b938,
4766 0xdf5e'dd5c'db5a'd958,
4767 0xff7e'fd7c'fb7a'f978,
4768 0x9716'9514'9312'9110,
4769 0xb736'b534'b332'b130,
4770 0xd756'd554'd352'd150,
4771 0xf776'f574'f372'f170});
4772 }
4773
TEST_F(Riscv64InterpreterTest,Vsxseg5eiXX_sew64)4774 TEST_F(Riscv64InterpreterTest, Vsxseg5eiXX_sew64) {
4775 VsxsegXeiXX<UInt64, 5, 1>(0x85008427, // Vsuxseg5ei8.v v8, (x1), v16, v0.t
4776 {0x8f0e'8d0c'8b0a'8908,
4777 0x9f1e'9d1c'9b1a'9918,
4778 0xaf2e'ad2c'ab2a'a928,
4779 0xbf3e'bd3c'bb3a'b938,
4780 0xcf4e'cd4c'cb4a'c948,
4781 0x8706'8504'8302'8100,
4782 0x9716'9514'9312'9110,
4783 0xa726'a524'a322'a120,
4784 0xb736'b534'b332'b130,
4785 0xc746'c544'c342'c140});
4786 }
4787
TEST_F(Riscv64InterpreterTest,Vsxseg6eiXX_sew64)4788 TEST_F(Riscv64InterpreterTest, Vsxseg6eiXX_sew64) {
4789 VsxsegXeiXX<UInt64, 6, 1>(0xa5008427, // Vsuxseg6ei8.v v8, (x1), v16, v0.t
4790 {0x8f0e'8d0c'8b0a'8908,
4791 0x9f1e'9d1c'9b1a'9918,
4792 0xaf2e'ad2c'ab2a'a928,
4793 0xbf3e'bd3c'bb3a'b938,
4794 0xcf4e'cd4c'cb4a'c948,
4795 0xdf5e'dd5c'db5a'd958,
4796 0x8706'8504'8302'8100,
4797 0x9716'9514'9312'9110,
4798 0xa726'a524'a322'a120,
4799 0xb736'b534'b332'b130,
4800 0xc746'c544'c342'c140,
4801 0xd756'd554'd352'd150});
4802 }
4803
TEST_F(Riscv64InterpreterTest,Vsxseg7eiXX_sew64)4804 TEST_F(Riscv64InterpreterTest, Vsxseg7eiXX_sew64) {
4805 VsxsegXeiXX<UInt64, 7, 1>(0xc5008427, // Vsuxseg7ei8.v v8, (x1), v16, v0.t
4806 {0x8f0e'8d0c'8b0a'8908,
4807 0x9f1e'9d1c'9b1a'9918,
4808 0xaf2e'ad2c'ab2a'a928,
4809 0xbf3e'bd3c'bb3a'b938,
4810 0xcf4e'cd4c'cb4a'c948,
4811 0xdf5e'dd5c'db5a'd958,
4812 0xef6e'ed6c'eb6a'e968,
4813 0x8706'8504'8302'8100,
4814 0x9716'9514'9312'9110,
4815 0xa726'a524'a322'a120,
4816 0xb736'b534'b332'b130,
4817 0xc746'c544'c342'c140,
4818 0xd756'd554'd352'd150,
4819 0xe766'e564'e362'e160});
4820 }
4821
TEST_F(Riscv64InterpreterTest,Vsxseg8eiXX_sew64)4822 TEST_F(Riscv64InterpreterTest, Vsxseg8eiXX_sew64) {
4823 VsxsegXeiXX<UInt64, 8, 1>(0xe5008427, // Vsuxseg8ei8.v v8, (x1), v16, v0.t
4824 {0x8f0e'8d0c'8b0a'8908,
4825 0x9f1e'9d1c'9b1a'9918,
4826 0xaf2e'ad2c'ab2a'a928,
4827 0xbf3e'bd3c'bb3a'b938,
4828 0xcf4e'cd4c'cb4a'c948,
4829 0xdf5e'dd5c'db5a'd958,
4830 0xef6e'ed6c'eb6a'e968,
4831 0xff7e'fd7c'fb7a'f978,
4832 0x8706'8504'8302'8100,
4833 0x9716'9514'9312'9110,
4834 0xa726'a524'a322'a120,
4835 0xb736'b534'b332'b130,
4836 0xc746'c544'c342'c140,
4837 0xd756'd554'd352'd150,
4838 0xe766'e564'e362'e160,
4839 0xf776'f574'f372'f170});
4840 }
4841
TEST_F(Riscv64InterpreterTest,TestVse8_vlmul1)4842 TEST_F(Riscv64InterpreterTest, TestVse8_vlmul1) {
4843 TestVssegXeXX<UInt8, 1, 1>(0x000008427, // vsse8.v v8, (x1), v0.t
4844 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908});
4845 }
4846
TEST_F(Riscv64InterpreterTest,TestVse8_vlmul2)4847 TEST_F(Riscv64InterpreterTest, TestVse8_vlmul2) {
4848 TestVssegXeXX<UInt8, 1, 2>(
4849 0x000008427, // vsse8.v v8, (x1), v0.t
4850 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908, 0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918});
4851 }
4852
TEST_F(Riscv64InterpreterTest,TestVse8_vlmul4)4853 TEST_F(Riscv64InterpreterTest, TestVse8_vlmul4) {
4854 TestVssegXeXX<UInt8, 1, 4>(0x000008427, // vsse8.v v8, (x1), v0.t
4855 {0x8706'8504'8302'8100,
4856 0x8f0e'8d0c'8b0a'8908,
4857 0x9716'9514'9312'9110,
4858 0x9f1e'9d1c'9b1a'9918,
4859 0xa726'a524'a322'a120,
4860 0xaf2e'ad2c'ab2a'a928,
4861 0xb736'b534'b332'b130,
4862 0xbf3e'bd3c'bb3a'b938});
4863 }
4864
TEST_F(Riscv64InterpreterTest,TestVse8_vlmul8)4865 TEST_F(Riscv64InterpreterTest, TestVse8_vlmul8) {
4866 TestVssegXeXX<UInt8, 1, 8>(0x000008427, // vsse8.v v8, (x1), v0.t
4867 {0x8706'8504'8302'8100,
4868 0x8f0e'8d0c'8b0a'8908,
4869 0x9716'9514'9312'9110,
4870 0x9f1e'9d1c'9b1a'9918,
4871 0xa726'a524'a322'a120,
4872 0xaf2e'ad2c'ab2a'a928,
4873 0xb736'b534'b332'b130,
4874 0xbf3e'bd3c'bb3a'b938,
4875 0xc746'c544'c342'c140,
4876 0xcf4e'cd4c'cb4a'c948,
4877 0xd756'd554'd352'd150,
4878 0xdf5e'dd5c'db5a'd958,
4879 0xe766'e564'e362'e160,
4880 0xef6e'ed6c'eb6a'e968,
4881 0xf776'f574'f372'f170,
4882 0xff7e'fd7c'fb7a'f978});
4883 }
4884
TEST_F(Riscv64InterpreterTest,TestVsseg2e8_vlmul1)4885 TEST_F(Riscv64InterpreterTest, TestVsseg2e8_vlmul1) {
4886 TestVssegXeXX<UInt8, 2, 1>(
4887 0x20008427, // vsseg2e8.v v8, (x1), v0.t
4888 {0x9383'1202'9181'1000, 0x9787'1606'9585'1404, 0x9b8b'1a0a'9989'1808, 0x9f8f'1e0e'9d8d'1c0c});
4889 }
4890
TEST_F(Riscv64InterpreterTest,TestVsseg2e8_vlmul2)4891 TEST_F(Riscv64InterpreterTest, TestVsseg2e8_vlmul2) {
4892 TestVssegXeXX<UInt8, 2, 2>(0x20008427, // vsseg2e8.v v8, (x1), v0.t
4893 {0xa383'2202'a181'2000,
4894 0xa787'2606'a585'2404,
4895 0xab8b'2a0a'a989'2808,
4896 0xaf8f'2e0e'ad8d'2c0c,
4897 0xb393'3212'b191'3010,
4898 0xb797'3616'b595'3414,
4899 0xbb9b'3a1a'b999'3818,
4900 0xbf9f'3e1e'bd9d'3c1c});
4901 }
4902
TEST_F(Riscv64InterpreterTest,TestVsseg2e8_vlmul4)4903 TEST_F(Riscv64InterpreterTest, TestVsseg2e8_vlmul4) {
4904 TestVssegXeXX<UInt8, 2, 4>(0x20008427, // vsseg2e8.v v8, (x1), v0.t
4905 {0xc383'4202'c181'4000,
4906 0xc787'4606'c585'4404,
4907 0xcb8b'4a0a'c989'4808,
4908 0xcf8f'4e0e'cd8d'4c0c,
4909 0xd393'5212'd191'5010,
4910 0xd797'5616'd595'5414,
4911 0xdb9b'5a1a'd999'5818,
4912 0xdf9f'5e1e'dd9d'5c1c,
4913 0xe3a3'6222'e1a1'6020,
4914 0xe7a7'6626'e5a5'6424,
4915 0xebab'6a2a'e9a9'6828,
4916 0xefaf'6e2e'edad'6c2c,
4917 0xf3b3'7232'f1b1'7030,
4918 0xf7b7'7636'f5b5'7434,
4919 0xfbbb'7a3a'f9b9'7838,
4920 0xffbf'7e3e'fdbd'7c3c});
4921 }
4922
TEST_F(Riscv64InterpreterTest,TestVsseg3e8_vlmul1)4923 TEST_F(Riscv64InterpreterTest, TestVsseg3e8_vlmul1) {
4924 TestVssegXeXX<UInt8, 3, 1>(0x40008427, // vsseg3e8.v v8, (x1), v0.t
4925 {0x1202'a191'8120'1000,
4926 0x8524'1404'a393'8322,
4927 0xa797'8726'1606'a595,
4928 0x1a0a'a999'8928'1808,
4929 0x8d2c'1c0c'ab9b'8b2a,
4930 0xaf9f'8f2e'1e0e'ad9d});
4931 }
4932
TEST_F(Riscv64InterpreterTest,TestVsseg3e8_vlmul2)4933 TEST_F(Riscv64InterpreterTest, TestVsseg3e8_vlmul2) {
4934 TestVssegXeXX<UInt8, 3, 2>(0x40008427, // vsseg3e8.v v8, (x1), v0.t
4935 {0x2202'c1a1'8140'2000,
4936 0x8544'2404'c3a3'8342,
4937 0xc7a7'8746'2606'c5a5,
4938 0x2a0a'c9a9'8948'2808,
4939 0x8d4c'2c0c'cbab'8b4a,
4940 0xcfaf'8f4e'2e0e'cdad,
4941 0x3212'd1b1'9150'3010,
4942 0x9554'3414'd3b3'9352,
4943 0xd7b7'9756'3616'd5b5,
4944 0x3a1a'd9b9'9958'3818,
4945 0x9d5c'3c1c'dbbb'9b5a,
4946 0xdfbf'9f5e'3e1e'ddbd});
4947 }
4948
TEST_F(Riscv64InterpreterTest,TestVsseg4e8_vlmul1)4949 TEST_F(Riscv64InterpreterTest, TestVsseg4e8_vlmul1) {
4950 TestVssegXeXX<UInt8, 4, 1>(0x60008427, // vsseg4e8.v v8, (x1), v0.t
4951 {0xb1a1'9181'3020'1000,
4952 0xb3a3'9383'3222'1202,
4953 0xb5a5'9585'3424'1404,
4954 0xb7a7'9787'3626'1606,
4955 0xb9a9'9989'3828'1808,
4956 0xbbab'9b8b'3a2a'1a0a,
4957 0xbdad'9d8d'3c2c'1c0c,
4958 0xbfaf'9f8f'3e2e'1e0e});
4959 }
4960
TEST_F(Riscv64InterpreterTest,TestVsseg4e8_vlmul2)4961 TEST_F(Riscv64InterpreterTest, TestVsseg4e8_vlmul2) {
4962 TestVssegXeXX<UInt8, 4, 2>(0x60008427, // vsseg4e8.v v8, (x1), v0.t
4963 {0xe1c1'a181'6040'2000,
4964 0xe3c3'a383'6242'2202,
4965 0xe5c5'a585'6444'2404,
4966 0xe7c7'a787'6646'2606,
4967 0xe9c9'a989'6848'2808,
4968 0xebcb'ab8b'6a4a'2a0a,
4969 0xedcd'ad8d'6c4c'2c0c,
4970 0xefcf'af8f'6e4e'2e0e,
4971 0xf1d1'b191'7050'3010,
4972 0xf3d3'b393'7252'3212,
4973 0xf5d5'b595'7454'3414,
4974 0xf7d7'b797'7656'3616,
4975 0xf9d9'b999'7858'3818,
4976 0xfbdb'bb9b'7a5a'3a1a,
4977 0xfddd'bd9d'7c5c'3c1c,
4978 0xffdf'bf9f'7e5e'3e1e});
4979 }
4980
TEST_F(Riscv64InterpreterTest,TestVsseg5e8)4981 TEST_F(Riscv64InterpreterTest, TestVsseg5e8) {
4982 TestVssegXeXX<UInt8, 5, 1>(0x80008427, // vsseg5e8.v v8, (x1), v0.t
4983 {0xa191'8140'3020'1000,
4984 0x8342'3222'1202'c1b1,
4985 0x3424'1404'c3b3'a393,
4986 0x1606'c5b5'a595'8544,
4987 0xc7b7'a797'8746'3626,
4988 0xa999'8948'3828'1808,
4989 0x8b4a'3a2a'1a0a'c9b9,
4990 0x3c2c'1c0c'cbbb'ab9b,
4991 0x1e0e'cdbd'ad9d'8d4c,
4992 0xcfbf'af9f'8f4e'3e2e});
4993 }
4994
TEST_F(Riscv64InterpreterTest,TestVsseg6e8)4995 TEST_F(Riscv64InterpreterTest, TestVsseg6e8) {
4996 TestVssegXeXX<UInt8, 6, 1>(0xa0008427, // vsseg6e8.v v8, (x1), v0.t
4997 {0x9181'5040'3020'1000,
4998 0x3222'1202'd1c1'b1a1,
4999 0xd3c3'b3a3'9383'5242,
5000 0x9585'5444'3424'1404,
5001 0x3626'1606'd5c5'b5a5,
5002 0xd7c7'b7a7'9787'5646,
5003 0x9989'5848'3828'1808,
5004 0x3a2a'1a0a'd9c9'b9a9,
5005 0xdbcb'bbab'9b8b'5a4a,
5006 0x9d8d'5c4c'3c2c'1c0c,
5007 0x3e2e'1e0e'ddcd'bdad,
5008 0xdfcf'bfaf'9f8f'5e4e});
5009 }
5010
TEST_F(Riscv64InterpreterTest,TestVsseg7e8)5011 TEST_F(Riscv64InterpreterTest, TestVsseg7e8) {
5012 TestVssegXeXX<UInt8, 7, 1>(0xc0008427, // vsseg7e8.v v8, (x1), v0.t
5013 {0x8160'5040'3020'1000,
5014 0x1202'e1d1'c1b1'a191,
5015 0xa393'8362'5242'3222,
5016 0x3424'1404'e3d3'c3b3,
5017 0xc5b5'a595'8564'5444,
5018 0x5646'3626'1606'e5d5,
5019 0xe7d7'c7b7'a797'8766,
5020 0x8968'5848'3828'1808,
5021 0x1a0a'e9d9'c9b9'a999,
5022 0xab9b'8b6a'5a4a'3a2a,
5023 0x3c2c'1c0c'ebdb'cbbb,
5024 0xcdbd'ad9d'8d6c'5c4c,
5025 0x5e4e'3e2e'1e0e'eddd,
5026 0xefdf'cfbf'af9f'8f6e});
5027 }
5028
TEST_F(Riscv64InterpreterTest,TestVsseg8e8)5029 TEST_F(Riscv64InterpreterTest, TestVsseg8e8) {
5030 TestVssegXeXX<UInt8, 8, 1>(0xe0008427, // vsseg8e8.v v8, (x1), v0.t
5031 {0x7060'5040'3020'1000,
5032 0xf1e1'd1c1'b1a1'9181,
5033 0x7262'5242'3222'1202,
5034 0xf3e3'd3c3'b3a3'9383,
5035 0x7464'5444'3424'1404,
5036 0xf5e5'd5c5'b5a5'9585,
5037 0x7666'5646'3626'1606,
5038 0xf7e7'd7c7'b7a7'9787,
5039 0x7868'5848'3828'1808,
5040 0xf9e9'd9c9'b9a9'9989,
5041 0x7a6a'5a4a'3a2a'1a0a,
5042 0xfbeb'dbcb'bbab'9b8b,
5043 0x7c6c'5c4c'3c2c'1c0c,
5044 0xfded'ddcd'bdad'9d8d,
5045 0x7e6e'5e4e'3e2e'1e0e,
5046 0xffef'dfcf'bfaf'9f8f});
5047 }
5048
TEST_F(Riscv64InterpreterTest,TestVse16_vlmul1)5049 TEST_F(Riscv64InterpreterTest, TestVse16_vlmul1) {
5050 TestVssegXeXX<UInt16, 1, 1>(0x000d427, // vse16.v v8, (x1), v0.t
5051 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908});
5052 }
5053
TEST_F(Riscv64InterpreterTest,TestVse16_vlmul2)5054 TEST_F(Riscv64InterpreterTest, TestVse16_vlmul2) {
5055 TestVssegXeXX<UInt16, 1, 2>(
5056 0x000d427, // vse16.v v8, (x1), v0.t
5057 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908, 0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918});
5058 }
5059
TEST_F(Riscv64InterpreterTest,TestVse16_vlmul4)5060 TEST_F(Riscv64InterpreterTest, TestVse16_vlmul4) {
5061 TestVssegXeXX<UInt16, 1, 4>(0x000d427, // vse16.v v8, (x1), v0.t
5062 {0x8706'8504'8302'8100,
5063 0x8f0e'8d0c'8b0a'8908,
5064 0x9716'9514'9312'9110,
5065 0x9f1e'9d1c'9b1a'9918,
5066 0xa726'a524'a322'a120,
5067 0xaf2e'ad2c'ab2a'a928,
5068 0xb736'b534'b332'b130,
5069 0xbf3e'bd3c'bb3a'b938});
5070 }
5071
TEST_F(Riscv64InterpreterTest,TestVse16_vlmul8)5072 TEST_F(Riscv64InterpreterTest, TestVse16_vlmul8) {
5073 TestVssegXeXX<UInt16, 1, 8>(0x000d427, // vse16.v v8, (x1), v0.t
5074 {0x8706'8504'8302'8100,
5075 0x8f0e'8d0c'8b0a'8908,
5076 0x9716'9514'9312'9110,
5077 0x9f1e'9d1c'9b1a'9918,
5078 0xa726'a524'a322'a120,
5079 0xaf2e'ad2c'ab2a'a928,
5080 0xb736'b534'b332'b130,
5081 0xbf3e'bd3c'bb3a'b938,
5082 0xc746'c544'c342'c140,
5083 0xcf4e'cd4c'cb4a'c948,
5084 0xd756'd554'd352'd150,
5085 0xdf5e'dd5c'db5a'd958,
5086 0xe766'e564'e362'e160,
5087 0xef6e'ed6c'eb6a'e968,
5088 0xf776'f574'f372'f170,
5089 0xff7e'fd7c'fb7a'f978});
5090 }
5091
TEST_F(Riscv64InterpreterTest,TestVsseg2e16_vlmul1)5092 TEST_F(Riscv64InterpreterTest, TestVsseg2e16_vlmul1) {
5093 TestVssegXeXX<UInt16, 2, 1>(
5094 0x2000d427, // vsseg2e16.v v8, (x1), v0.t
5095 {0x9312'8302'9110'8100, 0x9716'8706'9514'8504, 0x9b1a'8b0a'9918'8908, 0x9f1e'8f0e'9d1c'8d0c});
5096 }
5097
TEST_F(Riscv64InterpreterTest,TestVsseg2e16_vlmul2)5098 TEST_F(Riscv64InterpreterTest, TestVsseg2e16_vlmul2) {
5099 TestVssegXeXX<UInt16, 2, 2>(0x2000d427, // vsseg2e16.v v8, (x1), v0.t
5100 {0xa322'8302'a120'8100,
5101 0xa726'8706'a524'8504,
5102 0xab2a'8b0a'a928'8908,
5103 0xaf2e'8f0e'ad2c'8d0c,
5104 0xb332'9312'b130'9110,
5105 0xb736'9716'b534'9514,
5106 0xbb3a'9b1a'b938'9918,
5107 0xbf3e'9f1e'bd3c'9d1c});
5108 }
5109
TEST_F(Riscv64InterpreterTest,TestVsseg2e16_vlmul4)5110 TEST_F(Riscv64InterpreterTest, TestVsseg2e16_vlmul4) {
5111 TestVssegXeXX<UInt16, 2, 4>(0x2000d427, // vsseg2e16.v v8, (x1), v0.t
5112 {0xc342'8302'c140'8100,
5113 0xc746'8706'c544'8504,
5114 0xcb4a'8b0a'c948'8908,
5115 0xcf4e'8f0e'cd4c'8d0c,
5116 0xd352'9312'd150'9110,
5117 0xd756'9716'd554'9514,
5118 0xdb5a'9b1a'd958'9918,
5119 0xdf5e'9f1e'dd5c'9d1c,
5120 0xe362'a322'e160'a120,
5121 0xe766'a726'e564'a524,
5122 0xeb6a'ab2a'e968'a928,
5123 0xef6e'af2e'ed6c'ad2c,
5124 0xf372'b332'f170'b130,
5125 0xf776'b736'f574'b534,
5126 0xfb7a'bb3a'f978'b938,
5127 0xff7e'bf3e'fd7c'bd3c});
5128 }
5129
TEST_F(Riscv64InterpreterTest,TestVsseg3e16_vlmul1)5130 TEST_F(Riscv64InterpreterTest, TestVsseg3e16_vlmul1) {
5131 TestVssegXeXX<UInt16, 3, 1>(0x4000d427, // vsseg3e16.v v8, (x1), v0.t
5132 {0x8302'a120'9110'8100,
5133 0x9514'8504'a322'9312,
5134 0xa726'9716'8706'a524,
5135 0x8b0a'a928'9918'8908,
5136 0x9d1c'8d0c'ab2a'9b1a,
5137 0xaf2e'9f1e'8f0e'ad2c});
5138 }
5139
TEST_F(Riscv64InterpreterTest,TestVsseg3e16_vlmul2)5140 TEST_F(Riscv64InterpreterTest, TestVsseg3e16_vlmul2) {
5141 TestVssegXeXX<UInt16, 3, 2>(0x4000d427, // vsseg3e16.v v8, (x1), v0.t
5142 {0x8302'c140'a120'8100,
5143 0xa524'8504'c342'a322,
5144 0xc746'a726'8706'c544,
5145 0x8b0a'c948'a928'8908,
5146 0xad2c'8d0c'cb4a'ab2a,
5147 0xcf4e'af2e'8f0e'cd4c,
5148 0x9312'd150'b130'9110,
5149 0xb534'9514'd352'b332,
5150 0xd756'b736'9716'd554,
5151 0x9b1a'd958'b938'9918,
5152 0xbd3c'9d1c'db5a'bb3a,
5153 0xdf5e'bf3e'9f1e'dd5c});
5154 }
5155
TEST_F(Riscv64InterpreterTest,TestVsseg4e16_vlmul1)5156 TEST_F(Riscv64InterpreterTest, TestVsseg4e16_vlmul1) {
5157 TestVssegXeXX<UInt16, 4, 1>(0x6000d427, // vsseg4e16.v v8, (x1), v0.t
5158 {0xb130'a120'9110'8100,
5159 0xb332'a322'9312'8302,
5160 0xb534'a524'9514'8504,
5161 0xb736'a726'9716'8706,
5162 0xb938'a928'9918'8908,
5163 0xbb3a'ab2a'9b1a'8b0a,
5164 0xbd3c'ad2c'9d1c'8d0c,
5165 0xbf3e'af2e'9f1e'8f0e});
5166 }
5167
TEST_F(Riscv64InterpreterTest,TestVsseg4e16_vlmul2)5168 TEST_F(Riscv64InterpreterTest, TestVsseg4e16_vlmul2) {
5169 TestVssegXeXX<UInt16, 4, 2>(0x6000d427, // vsseg4e16.v v8, (x1), v0.t
5170 {0xe160'c140'a120'8100,
5171 0xe362'c342'a322'8302,
5172 0xe564'c544'a524'8504,
5173 0xe766'c746'a726'8706,
5174 0xe968'c948'a928'8908,
5175 0xeb6a'cb4a'ab2a'8b0a,
5176 0xed6c'cd4c'ad2c'8d0c,
5177 0xef6e'cf4e'af2e'8f0e,
5178 0xf170'd150'b130'9110,
5179 0xf372'd352'b332'9312,
5180 0xf574'd554'b534'9514,
5181 0xf776'd756'b736'9716,
5182 0xf978'd958'b938'9918,
5183 0xfb7a'db5a'bb3a'9b1a,
5184 0xfd7c'dd5c'bd3c'9d1c,
5185 0xff7e'df5e'bf3e'9f1e});
5186 }
5187
TEST_F(Riscv64InterpreterTest,TestVsseg5e16)5188 TEST_F(Riscv64InterpreterTest, TestVsseg5e16) {
5189 TestVssegXeXX<UInt16, 5, 1>(0x8000d427, // vsseg5e16.v v8, (x1), v0.t
5190 {0xb130'a120'9110'8100,
5191 0xa322'9312'8302'c140,
5192 0x9514'8504'c342'b332,
5193 0x8706'c544'b534'a524,
5194 0xc746'b736'a726'9716,
5195 0xb938'a928'9918'8908,
5196 0xab2a'9b1a'8b0a'c948,
5197 0x9d1c'8d0c'cb4a'bb3a,
5198 0x8f0e'cd4c'bd3c'ad2c,
5199 0xcf4e'bf3e'af2e'9f1e});
5200 }
5201
TEST_F(Riscv64InterpreterTest,TestVsseg6e16)5202 TEST_F(Riscv64InterpreterTest, TestVsseg6e16) {
5203 TestVssegXeXX<UInt16, 6, 1>(0xa000d427, // vsseg6e16.v v8, (x1), v0.t
5204 {0xb130'a120'9110'8100,
5205 0x9312'8302'd150'c140,
5206 0xd352'c342'b332'a322,
5207 0xb534'a524'9514'8504,
5208 0x9716'8706'd554'c544,
5209 0xd756'c746'b736'a726,
5210 0xb938'a928'9918'8908,
5211 0x9b1a'8b0a'd958'c948,
5212 0xdb5a'cb4a'bb3a'ab2a,
5213 0xbd3c'ad2c'9d1c'8d0c,
5214 0x9f1e'8f0e'dd5c'cd4c,
5215 0xdf5e'cf4e'bf3e'af2e});
5216 }
5217
TEST_F(Riscv64InterpreterTest,TestVsseg7e16)5218 TEST_F(Riscv64InterpreterTest, TestVsseg7e16) {
5219 TestVssegXeXX<UInt16, 7, 1>(0xc000d427, // vsseg7e16.v v8, (x1), v0.t
5220 {0xb130'a120'9110'8100,
5221 0x8302'e160'd150'c140,
5222 0xc342'b332'a322'9312,
5223 0x9514'8504'e362'd352,
5224 0xd554'c544'b534'a524,
5225 0xa726'9716'8706'e564,
5226 0xe766'd756'c746'b736,
5227 0xb938'a928'9918'8908,
5228 0x8b0a'e968'd958'c948,
5229 0xcb4a'bb3a'ab2a'9b1a,
5230 0x9d1c'8d0c'eb6a'db5a,
5231 0xdd5c'cd4c'bd3c'ad2c,
5232 0xaf2e'9f1e'8f0e'ed6c,
5233 0xef6e'df5e'cf4e'bf3e});
5234 }
5235
TEST_F(Riscv64InterpreterTest,TestVsseg8e16)5236 TEST_F(Riscv64InterpreterTest, TestVsseg8e16) {
5237 TestVssegXeXX<UInt16, 8, 1>(0xe000d427, // vsseg8e16.v v8, (x1), v0.t
5238 {0xb130'a120'9110'8100,
5239 0xf170'e160'd150'c140,
5240 0xb332'a322'9312'8302,
5241 0xf372'e362'd352'c342,
5242 0xb534'a524'9514'8504,
5243 0xf574'e564'd554'c544,
5244 0xb736'a726'9716'8706,
5245 0xf776'e766'd756'c746,
5246 0xb938'a928'9918'8908,
5247 0xf978'e968'd958'c948,
5248 0xbb3a'ab2a'9b1a'8b0a,
5249 0xfb7a'eb6a'db5a'cb4a,
5250 0xbd3c'ad2c'9d1c'8d0c,
5251 0xfd7c'ed6c'dd5c'cd4c,
5252 0xbf3e'af2e'9f1e'8f0e,
5253 0xff7e'ef6e'df5e'cf4e});
5254 }
5255
TEST_F(Riscv64InterpreterTest,TestVse32_vlmul1)5256 TEST_F(Riscv64InterpreterTest, TestVse32_vlmul1) {
5257 TestVssegXeXX<UInt32, 1, 1>(0x000e427, // vse32.v v8, (x1), v0.t
5258 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908});
5259 }
5260
TEST_F(Riscv64InterpreterTest,TestVse32_vlmul2)5261 TEST_F(Riscv64InterpreterTest, TestVse32_vlmul2) {
5262 TestVssegXeXX<UInt32, 1, 2>(
5263 0x000e427, // vse32.v v8, (x1), v0.t
5264 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908, 0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918});
5265 }
5266
TEST_F(Riscv64InterpreterTest,TestVse32_vlmul4)5267 TEST_F(Riscv64InterpreterTest, TestVse32_vlmul4) {
5268 TestVssegXeXX<UInt32, 1, 4>(0x000e427, // vse32.v v8, (x1), v0.t
5269 {0x8706'8504'8302'8100,
5270 0x8f0e'8d0c'8b0a'8908,
5271 0x9716'9514'9312'9110,
5272 0x9f1e'9d1c'9b1a'9918,
5273 0xa726'a524'a322'a120,
5274 0xaf2e'ad2c'ab2a'a928,
5275 0xb736'b534'b332'b130,
5276 0xbf3e'bd3c'bb3a'b938});
5277 }
5278
TEST_F(Riscv64InterpreterTest,TestVse32_vlmul8)5279 TEST_F(Riscv64InterpreterTest, TestVse32_vlmul8) {
5280 TestVssegXeXX<UInt32, 1, 8>(0x000e427, // vse32.v v8, (x1), v0.t
5281 {0x8706'8504'8302'8100,
5282 0x8f0e'8d0c'8b0a'8908,
5283 0x9716'9514'9312'9110,
5284 0x9f1e'9d1c'9b1a'9918,
5285 0xa726'a524'a322'a120,
5286 0xaf2e'ad2c'ab2a'a928,
5287 0xb736'b534'b332'b130,
5288 0xbf3e'bd3c'bb3a'b938,
5289 0xc746'c544'c342'c140,
5290 0xcf4e'cd4c'cb4a'c948,
5291 0xd756'd554'd352'd150,
5292 0xdf5e'dd5c'db5a'd958,
5293 0xe766'e564'e362'e160,
5294 0xef6e'ed6c'eb6a'e968,
5295 0xf776'f574'f372'f170,
5296 0xff7e'fd7c'fb7a'f978});
5297 }
5298
TEST_F(Riscv64InterpreterTest,TestVsseg2e32_vlmul1)5299 TEST_F(Riscv64InterpreterTest, TestVsseg2e32_vlmul1) {
5300 TestVssegXeXX<UInt32, 2, 1>(
5301 0x2000e427, // vsseg2e32.v v8, (x1), v0.t
5302 {0x9312'9110'8302'8100, 0x9716'9514'8706'8504, 0x9b1a'9918'8b0a'8908, 0x9f1e'9d1c'8f0e'8d0c});
5303 }
5304
TEST_F(Riscv64InterpreterTest,TestVsseg2e32_vlmul2)5305 TEST_F(Riscv64InterpreterTest, TestVsseg2e32_vlmul2) {
5306 TestVssegXeXX<UInt32, 2, 2>(0x2000e427, // vsseg2e32.v v8, (x1), v0.t
5307 {0xa322'a120'8302'8100,
5308 0xa726'a524'8706'8504,
5309 0xab2a'a928'8b0a'8908,
5310 0xaf2e'ad2c'8f0e'8d0c,
5311 0xb332'b130'9312'9110,
5312 0xb736'b534'9716'9514,
5313 0xbb3a'b938'9b1a'9918,
5314 0xbf3e'bd3c'9f1e'9d1c});
5315 }
5316
TEST_F(Riscv64InterpreterTest,TestVsseg2e32_vlmul4)5317 TEST_F(Riscv64InterpreterTest, TestVsseg2e32_vlmul4) {
5318 TestVssegXeXX<UInt32, 2, 4>(0x2000e427, // vsseg2e32.v v8, (x1), v0.t
5319 {0xc342'c140'8302'8100,
5320 0xc746'c544'8706'8504,
5321 0xcb4a'c948'8b0a'8908,
5322 0xcf4e'cd4c'8f0e'8d0c,
5323 0xd352'd150'9312'9110,
5324 0xd756'd554'9716'9514,
5325 0xdb5a'd958'9b1a'9918,
5326 0xdf5e'dd5c'9f1e'9d1c,
5327 0xe362'e160'a322'a120,
5328 0xe766'e564'a726'a524,
5329 0xeb6a'e968'ab2a'a928,
5330 0xef6e'ed6c'af2e'ad2c,
5331 0xf372'f170'b332'b130,
5332 0xf776'f574'b736'b534,
5333 0xfb7a'f978'bb3a'b938,
5334 0xff7e'fd7c'bf3e'bd3c});
5335 }
5336
TEST_F(Riscv64InterpreterTest,TestVsseg3e32_vlmul1)5337 TEST_F(Riscv64InterpreterTest, TestVsseg3e32_vlmul1) {
5338 TestVssegXeXX<UInt32, 3, 1>(0x4000e427, // vsseg3e32.v v8, (x1), v0.t
5339 {0x9312'9110'8302'8100,
5340 0x8706'8504'a322'a120,
5341 0xa726'a524'9716'9514,
5342 0x9b1a'9918'8b0a'8908,
5343 0x8f0e'8d0c'ab2a'a928,
5344 0xaf2e'ad2c'9f1e'9d1c});
5345 }
5346
TEST_F(Riscv64InterpreterTest,TestVsseg3e32_vlmul2)5347 TEST_F(Riscv64InterpreterTest, TestVsseg3e32_vlmul2) {
5348 TestVssegXeXX<UInt32, 3, 2>(0x4000e427, // vsseg3e32.v v8, (x1), v0.t
5349 {0xa322'a120'8302'8100,
5350 0x8706'8504'c342'c140,
5351 0xc746'c544'a726'a524,
5352 0xab2a'a928'8b0a'8908,
5353 0x8f0e'8d0c'cb4a'c948,
5354 0xcf4e'cd4c'af2e'ad2c,
5355 0xb332'b130'9312'9110,
5356 0x9716'9514'd352'd150,
5357 0xd756'd554'b736'b534,
5358 0xbb3a'b938'9b1a'9918,
5359 0x9f1e'9d1c'db5a'd958,
5360 0xdf5e'dd5c'bf3e'bd3c});
5361 }
5362
TEST_F(Riscv64InterpreterTest,TestVsseg4e32_vlmul1)5363 TEST_F(Riscv64InterpreterTest, TestVsseg4e32_vlmul1) {
5364 TestVssegXeXX<UInt32, 4, 1>(0x6000e427, // vsseg4e32.v v8, (x1), v0.t
5365 {0x9312'9110'8302'8100,
5366 0xb332'b130'a322'a120,
5367 0x9716'9514'8706'8504,
5368 0xb736'b534'a726'a524,
5369 0x9b1a'9918'8b0a'8908,
5370 0xbb3a'b938'ab2a'a928,
5371 0x9f1e'9d1c'8f0e'8d0c,
5372 0xbf3e'bd3c'af2e'ad2c});
5373 }
5374
TEST_F(Riscv64InterpreterTest,TestVsseg4e32_vlmul2)5375 TEST_F(Riscv64InterpreterTest, TestVsseg4e32_vlmul2) {
5376 TestVssegXeXX<UInt32, 4, 2>(0x6000e427, // vsseg4e32.v v8, (x1), v0.t
5377 {0xa322'a120'8302'8100,
5378 0xe362'e160'c342'c140,
5379 0xa726'a524'8706'8504,
5380 0xe766'e564'c746'c544,
5381 0xab2a'a928'8b0a'8908,
5382 0xeb6a'e968'cb4a'c948,
5383 0xaf2e'ad2c'8f0e'8d0c,
5384 0xef6e'ed6c'cf4e'cd4c,
5385 0xb332'b130'9312'9110,
5386 0xf372'f170'd352'd150,
5387 0xb736'b534'9716'9514,
5388 0xf776'f574'd756'd554,
5389 0xbb3a'b938'9b1a'9918,
5390 0xfb7a'f978'db5a'd958,
5391 0xbf3e'bd3c'9f1e'9d1c,
5392 0xff7e'fd7c'df5e'dd5c});
5393 }
5394
TEST_F(Riscv64InterpreterTest,TestVsseg5e32)5395 TEST_F(Riscv64InterpreterTest, TestVsseg5e32) {
5396 TestVssegXeXX<UInt32, 5, 1>(0x8000e427, // vsseg5e32.v v8, (x1), v0.t
5397 {0x9312'9110'8302'8100,
5398 0xb332'b130'a322'a120,
5399 0x8706'8504'c342'c140,
5400 0xa726'a524'9716'9514,
5401 0xc746'c544'b736'b534,
5402 0x9b1a'9918'8b0a'8908,
5403 0xbb3a'b938'ab2a'a928,
5404 0x8f0e'8d0c'cb4a'c948,
5405 0xaf2e'ad2c'9f1e'9d1c,
5406 0xcf4e'cd4c'bf3e'bd3c});
5407 }
5408
TEST_F(Riscv64InterpreterTest,TestVsseg6e32)5409 TEST_F(Riscv64InterpreterTest, TestVsseg6e32) {
5410 TestVssegXeXX<UInt32, 6, 1>(0xa000e427, // vsseg6e32.v v8, (x1), v0.t
5411 {0x9312'9110'8302'8100,
5412 0xb332'b130'a322'a120,
5413 0xd352'd150'c342'c140,
5414 0x9716'9514'8706'8504,
5415 0xb736'b534'a726'a524,
5416 0xd756'd554'c746'c544,
5417 0x9b1a'9918'8b0a'8908,
5418 0xbb3a'b938'ab2a'a928,
5419 0xdb5a'd958'cb4a'c948,
5420 0x9f1e'9d1c'8f0e'8d0c,
5421 0xbf3e'bd3c'af2e'ad2c,
5422 0xdf5e'dd5c'cf4e'cd4c});
5423 }
5424
TEST_F(Riscv64InterpreterTest,TestVsseg7e32)5425 TEST_F(Riscv64InterpreterTest, TestVsseg7e32) {
5426 TestVssegXeXX<UInt32, 7, 1>(0xc000e427, // vsseg7e32.v v8, (x1), v0.t
5427 {0x9312'9110'8302'8100,
5428 0xb332'b130'a322'a120,
5429 0xd352'd150'c342'c140,
5430 0x8706'8504'e362'e160,
5431 0xa726'a524'9716'9514,
5432 0xc746'c544'b736'b534,
5433 0xe766'e564'd756'd554,
5434 0x9b1a'9918'8b0a'8908,
5435 0xbb3a'b938'ab2a'a928,
5436 0xdb5a'd958'cb4a'c948,
5437 0x8f0e'8d0c'eb6a'e968,
5438 0xaf2e'ad2c'9f1e'9d1c,
5439 0xcf4e'cd4c'bf3e'bd3c,
5440 0xef6e'ed6c'df5e'dd5c});
5441 }
5442
TEST_F(Riscv64InterpreterTest,TestVsseg8e32)5443 TEST_F(Riscv64InterpreterTest, TestVsseg8e32) {
5444 TestVssegXeXX<UInt32, 8, 1>(0xe000e427, // vsseg8e32.v v8, (x1), v0.t
5445 {0x9312'9110'8302'8100,
5446 0xb332'b130'a322'a120,
5447 0xd352'd150'c342'c140,
5448 0xf372'f170'e362'e160,
5449 0x9716'9514'8706'8504,
5450 0xb736'b534'a726'a524,
5451 0xd756'd554'c746'c544,
5452 0xf776'f574'e766'e564,
5453 0x9b1a'9918'8b0a'8908,
5454 0xbb3a'b938'ab2a'a928,
5455 0xdb5a'd958'cb4a'c948,
5456 0xfb7a'f978'eb6a'e968,
5457 0x9f1e'9d1c'8f0e'8d0c,
5458 0xbf3e'bd3c'af2e'ad2c,
5459 0xdf5e'dd5c'cf4e'cd4c,
5460 0xff7e'fd7c'ef6e'ed6c});
5461 }
5462
TEST_F(Riscv64InterpreterTest,TestVse64_vlmul1)5463 TEST_F(Riscv64InterpreterTest, TestVse64_vlmul1) {
5464 TestVssegXeXX<UInt64, 1, 1>(0x000f427, // vse64.v v8, (x1), v0.t
5465 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908});
5466 }
5467
TEST_F(Riscv64InterpreterTest,TestVse64_vlmul2)5468 TEST_F(Riscv64InterpreterTest, TestVse64_vlmul2) {
5469 TestVssegXeXX<UInt64, 1, 2>(
5470 0x000f427, // vse64.v v8, (x1), v0.t
5471 {0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908, 0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918});
5472 }
5473
TEST_F(Riscv64InterpreterTest,TestVse64_vlmul4)5474 TEST_F(Riscv64InterpreterTest, TestVse64_vlmul4) {
5475 TestVssegXeXX<UInt64, 1, 4>(0x000f427, // vse64.v v8, (x1), v0.t
5476 {0x8706'8504'8302'8100,
5477 0x8f0e'8d0c'8b0a'8908,
5478 0x9716'9514'9312'9110,
5479 0x9f1e'9d1c'9b1a'9918,
5480 0xa726'a524'a322'a120,
5481 0xaf2e'ad2c'ab2a'a928,
5482 0xb736'b534'b332'b130,
5483 0xbf3e'bd3c'bb3a'b938});
5484 }
5485
TEST_F(Riscv64InterpreterTest,TestVse64_vlmul8)5486 TEST_F(Riscv64InterpreterTest, TestVse64_vlmul8) {
5487 TestVssegXeXX<UInt64, 1, 8>(0x000f427, // vse64.v v8, (x1), v0.t
5488 {0x8706'8504'8302'8100,
5489 0x8f0e'8d0c'8b0a'8908,
5490 0x9716'9514'9312'9110,
5491 0x9f1e'9d1c'9b1a'9918,
5492 0xa726'a524'a322'a120,
5493 0xaf2e'ad2c'ab2a'a928,
5494 0xb736'b534'b332'b130,
5495 0xbf3e'bd3c'bb3a'b938,
5496 0xc746'c544'c342'c140,
5497 0xcf4e'cd4c'cb4a'c948,
5498 0xd756'd554'd352'd150,
5499 0xdf5e'dd5c'db5a'd958,
5500 0xe766'e564'e362'e160,
5501 0xef6e'ed6c'eb6a'e968,
5502 0xf776'f574'f372'f170,
5503 0xff7e'fd7c'fb7a'f978});
5504 }
5505
TEST_F(Riscv64InterpreterTest,TestVsseg2e64_vlmul1)5506 TEST_F(Riscv64InterpreterTest, TestVsseg2e64_vlmul1) {
5507 TestVssegXeXX<UInt64, 2, 1>(
5508 0x2000f427, // vsseg2e64.v v8, (x1), v0.t
5509 {0x8706'8504'8302'8100, 0x9716'9514'9312'9110, 0x8f0e'8d0c'8b0a'8908, 0x9f1e'9d1c'9b1a'9918});
5510 }
5511
TEST_F(Riscv64InterpreterTest,TestVsseg2e64_vlmul2)5512 TEST_F(Riscv64InterpreterTest, TestVsseg2e64_vlmul2) {
5513 TestVssegXeXX<UInt64, 2, 2>(0x2000f427, // vsseg2e64.v v8, (x1), v0.t
5514 {0x8706'8504'8302'8100,
5515 0xa726'a524'a322'a120,
5516 0x8f0e'8d0c'8b0a'8908,
5517 0xaf2e'ad2c'ab2a'a928,
5518 0x9716'9514'9312'9110,
5519 0xb736'b534'b332'b130,
5520 0x9f1e'9d1c'9b1a'9918,
5521 0xbf3e'bd3c'bb3a'b938});
5522 }
5523
TEST_F(Riscv64InterpreterTest,TestVsseg2e64_vlmul4)5524 TEST_F(Riscv64InterpreterTest, TestVsseg2e64_vlmul4) {
5525 TestVssegXeXX<UInt64, 2, 4>(0x2000f427, // vsseg2e64.v v8, (x1), v0.t
5526 {0x8706'8504'8302'8100,
5527 0xc746'c544'c342'c140,
5528 0x8f0e'8d0c'8b0a'8908,
5529 0xcf4e'cd4c'cb4a'c948,
5530 0x9716'9514'9312'9110,
5531 0xd756'd554'd352'd150,
5532 0x9f1e'9d1c'9b1a'9918,
5533 0xdf5e'dd5c'db5a'd958,
5534 0xa726'a524'a322'a120,
5535 0xe766'e564'e362'e160,
5536 0xaf2e'ad2c'ab2a'a928,
5537 0xef6e'ed6c'eb6a'e968,
5538 0xb736'b534'b332'b130,
5539 0xf776'f574'f372'f170,
5540 0xbf3e'bd3c'bb3a'b938,
5541 0xff7e'fd7c'fb7a'f978});
5542 }
5543
TEST_F(Riscv64InterpreterTest,TestVsseg3e64_vlmul1)5544 TEST_F(Riscv64InterpreterTest, TestVsseg3e64_vlmul1) {
5545 TestVssegXeXX<UInt64, 3, 1>(0x4000f427, // vsseg3e64.v v8, (x1), v0.t
5546 {0x8706'8504'8302'8100,
5547 0x9716'9514'9312'9110,
5548 0xa726'a524'a322'a120,
5549 0x8f0e'8d0c'8b0a'8908,
5550 0x9f1e'9d1c'9b1a'9918,
5551 0xaf2e'ad2c'ab2a'a928});
5552 }
5553
TEST_F(Riscv64InterpreterTest,TestVsseg3e64_vlmul2)5554 TEST_F(Riscv64InterpreterTest, TestVsseg3e64_vlmul2) {
5555 TestVssegXeXX<UInt64, 3, 2>(0x4000f427, // vsseg3e64.v v8, (x1), v0.t
5556 {0x8706'8504'8302'8100,
5557 0xa726'a524'a322'a120,
5558 0xc746'c544'c342'c140,
5559 0x8f0e'8d0c'8b0a'8908,
5560 0xaf2e'ad2c'ab2a'a928,
5561 0xcf4e'cd4c'cb4a'c948,
5562 0x9716'9514'9312'9110,
5563 0xb736'b534'b332'b130,
5564 0xd756'd554'd352'd150,
5565 0x9f1e'9d1c'9b1a'9918,
5566 0xbf3e'bd3c'bb3a'b938,
5567 0xdf5e'dd5c'db5a'd958});
5568 }
5569
TEST_F(Riscv64InterpreterTest,TestVsseg4e64_vlmul1)5570 TEST_F(Riscv64InterpreterTest, TestVsseg4e64_vlmul1) {
5571 TestVssegXeXX<UInt64, 4, 1>(0x6000f427, // vsseg4e64.v v8, (x1), v0.t
5572 {0x8706'8504'8302'8100,
5573 0x9716'9514'9312'9110,
5574 0xa726'a524'a322'a120,
5575 0xb736'b534'b332'b130,
5576 0x8f0e'8d0c'8b0a'8908,
5577 0x9f1e'9d1c'9b1a'9918,
5578 0xaf2e'ad2c'ab2a'a928,
5579 0xbf3e'bd3c'bb3a'b938});
5580 }
5581
TEST_F(Riscv64InterpreterTest,TestVsseg4e64_vlmul2)5582 TEST_F(Riscv64InterpreterTest, TestVsseg4e64_vlmul2) {
5583 TestVssegXeXX<UInt64, 4, 2>(0x6000f427, // vsseg4e64.v v8, (x1), v0.t
5584 {0x8706'8504'8302'8100,
5585 0xa726'a524'a322'a120,
5586 0xc746'c544'c342'c140,
5587 0xe766'e564'e362'e160,
5588 0x8f0e'8d0c'8b0a'8908,
5589 0xaf2e'ad2c'ab2a'a928,
5590 0xcf4e'cd4c'cb4a'c948,
5591 0xef6e'ed6c'eb6a'e968,
5592 0x9716'9514'9312'9110,
5593 0xb736'b534'b332'b130,
5594 0xd756'd554'd352'd150,
5595 0xf776'f574'f372'f170,
5596 0x9f1e'9d1c'9b1a'9918,
5597 0xbf3e'bd3c'bb3a'b938,
5598 0xdf5e'dd5c'db5a'd958,
5599 0xff7e'fd7c'fb7a'f978});
5600 }
5601
TEST_F(Riscv64InterpreterTest,TestVsseg5e64)5602 TEST_F(Riscv64InterpreterTest, TestVsseg5e64) {
5603 TestVssegXeXX<UInt64, 5, 1>(0x8000f427, // vsseg5e64.v v8, (x1), v0.t
5604 {0x8706'8504'8302'8100,
5605 0x9716'9514'9312'9110,
5606 0xa726'a524'a322'a120,
5607 0xb736'b534'b332'b130,
5608 0xc746'c544'c342'c140,
5609 0x8f0e'8d0c'8b0a'8908,
5610 0x9f1e'9d1c'9b1a'9918,
5611 0xaf2e'ad2c'ab2a'a928,
5612 0xbf3e'bd3c'bb3a'b938,
5613 0xcf4e'cd4c'cb4a'c948});
5614 }
5615
TEST_F(Riscv64InterpreterTest,TestVsseg6e64)5616 TEST_F(Riscv64InterpreterTest, TestVsseg6e64) {
5617 TestVssegXeXX<UInt64, 6, 1>(0xa000f427, // vsseg6e64.v v8, (x1), v0.t
5618 {0x8706'8504'8302'8100,
5619 0x9716'9514'9312'9110,
5620 0xa726'a524'a322'a120,
5621 0xb736'b534'b332'b130,
5622 0xc746'c544'c342'c140,
5623 0xd756'd554'd352'd150,
5624 0x8f0e'8d0c'8b0a'8908,
5625 0x9f1e'9d1c'9b1a'9918,
5626 0xaf2e'ad2c'ab2a'a928,
5627 0xbf3e'bd3c'bb3a'b938,
5628 0xcf4e'cd4c'cb4a'c948,
5629 0xdf5e'dd5c'db5a'd958});
5630 }
5631
TEST_F(Riscv64InterpreterTest,TestVsseg7e64)5632 TEST_F(Riscv64InterpreterTest, TestVsseg7e64) {
5633 TestVssegXeXX<UInt64, 7, 1>(0xc000f427, // vsseg7e64.v v8, (x1), v0.t
5634 {0x8706'8504'8302'8100,
5635 0x9716'9514'9312'9110,
5636 0xa726'a524'a322'a120,
5637 0xb736'b534'b332'b130,
5638 0xc746'c544'c342'c140,
5639 0xd756'd554'd352'd150,
5640 0xe766'e564'e362'e160,
5641 0x8f0e'8d0c'8b0a'8908,
5642 0x9f1e'9d1c'9b1a'9918,
5643 0xaf2e'ad2c'ab2a'a928,
5644 0xbf3e'bd3c'bb3a'b938,
5645 0xcf4e'cd4c'cb4a'c948,
5646 0xdf5e'dd5c'db5a'd958,
5647 0xef6e'ed6c'eb6a'e968});
5648 }
5649
TEST_F(Riscv64InterpreterTest,TestVsseg8e64)5650 TEST_F(Riscv64InterpreterTest, TestVsseg8e64) {
5651 TestVssegXeXX<UInt64, 8, 1>(0xe000f427, // vsseg8e64.v v8, (x1), v0.t
5652 {0x8706'8504'8302'8100,
5653 0x9716'9514'9312'9110,
5654 0xa726'a524'a322'a120,
5655 0xb736'b534'b332'b130,
5656 0xc746'c544'c342'c140,
5657 0xd756'd554'd352'd150,
5658 0xe766'e564'e362'e160,
5659 0xf776'f574'f372'f170,
5660 0x8f0e'8d0c'8b0a'8908,
5661 0x9f1e'9d1c'9b1a'9918,
5662 0xaf2e'ad2c'ab2a'a928,
5663 0xbf3e'bd3c'bb3a'b938,
5664 0xcf4e'cd4c'cb4a'c948,
5665 0xdf5e'dd5c'db5a'd958,
5666 0xef6e'ed6c'eb6a'e968,
5667 0xff7e'fd7c'fb7a'f978});
5668 }
5669
TEST_F(Riscv64InterpreterTest,TestVsse8_vlmul1)5670 TEST_F(Riscv64InterpreterTest, TestVsse8_vlmul1) {
5671 TestVsssegXeXX<UInt8, 1, 1>(0x8208427, // vsse8.v v8, (x1), x2, v0.t
5672 4,
5673 {0x5555'5581'5555'5500,
5674 0x5555'5583'5555'5502,
5675 0x5555'5585'5555'5504,
5676 0x5555'5587'5555'5506,
5677 0x5555'5589'5555'5508,
5678 0x5555'558b'5555'550a,
5679 0x5555'558d'5555'550c,
5680 0x5555'558f'5555'550e});
5681 }
5682
TEST_F(Riscv64InterpreterTest,TestVsse8_vlmul2)5683 TEST_F(Riscv64InterpreterTest, TestVsse8_vlmul2) {
5684 TestVsssegXeXX<UInt8, 1, 2>(0x8208427, // vsse8.v v8, (x1), x2, v0.t
5685 4,
5686 {0x5555'5581'5555'5500,
5687 0x5555'5583'5555'5502,
5688 0x5555'5585'5555'5504,
5689 0x5555'5587'5555'5506,
5690 0x5555'5589'5555'5508,
5691 0x5555'558b'5555'550a,
5692 0x5555'558d'5555'550c,
5693 0x5555'558f'5555'550e,
5694 0x5555'5591'5555'5510,
5695 0x5555'5593'5555'5512,
5696 0x5555'5595'5555'5514,
5697 0x5555'5597'5555'5516,
5698 0x5555'5599'5555'5518,
5699 0x5555'559b'5555'551a,
5700 0x5555'559d'5555'551c,
5701 0x5555'559f'5555'551e});
5702 }
5703
TEST_F(Riscv64InterpreterTest,TestVsse8_vlmul4)5704 TEST_F(Riscv64InterpreterTest, TestVsse8_vlmul4) {
5705 TestVsssegXeXX<UInt8, 1, 4>(
5706 0x8208427, // vlse8.v v8, (x1), x2, v0.t
5707 4,
5708 {0x5555'5581'5555'5500, 0x5555'5583'5555'5502, 0x5555'5585'5555'5504, 0x5555'5587'5555'5506,
5709 0x5555'5589'5555'5508, 0x5555'558b'5555'550a, 0x5555'558d'5555'550c, 0x5555'558f'5555'550e,
5710 0x5555'5591'5555'5510, 0x5555'5593'5555'5512, 0x5555'5595'5555'5514, 0x5555'5597'5555'5516,
5711 0x5555'5599'5555'5518, 0x5555'559b'5555'551a, 0x5555'559d'5555'551c, 0x5555'559f'5555'551e,
5712 0x5555'55a1'5555'5520, 0x5555'55a3'5555'5522, 0x5555'55a5'5555'5524, 0x5555'55a7'5555'5526,
5713 0x5555'55a9'5555'5528, 0x5555'55ab'5555'552a, 0x5555'55ad'5555'552c, 0x5555'55af'5555'552e,
5714 0x5555'55b1'5555'5530, 0x5555'55b3'5555'5532, 0x5555'55b5'5555'5534, 0x5555'55b7'5555'5536,
5715 0x5555'55b9'5555'5538, 0x5555'55bb'5555'553a, 0x5555'55bd'5555'553c, 0x5555'55bf'5555'553e});
5716 }
5717
TEST_F(Riscv64InterpreterTest,TestVsse8_vlmul8)5718 TEST_F(Riscv64InterpreterTest, TestVsse8_vlmul8) {
5719 TestVsssegXeXX<UInt8, 1, 8>(
5720 0x8208427, // vsse8.v v8, (x1), x2, v0.t
5721 2,
5722 {0x5583'5502'5581'5500, 0x5587'5506'5585'5504, 0x558b'550a'5589'5508, 0x558f'550e'558d'550c,
5723 0x5593'5512'5591'5510, 0x5597'5516'5595'5514, 0x559b'551a'5599'5518, 0x559f'551e'559d'551c,
5724 0x55a3'5522'55a1'5520, 0x55a7'5526'55a5'5524, 0x55ab'552a'55a9'5528, 0x55af'552e'55ad'552c,
5725 0x55b3'5532'55b1'5530, 0x55b7'5536'55b5'5534, 0x55bb'553a'55b9'5538, 0x55bf'553e'55bd'553c,
5726 0x55c3'5542'55c1'5540, 0x55c7'5546'55c5'5544, 0x55cb'554a'55c9'5548, 0x55cf'554e'55cd'554c,
5727 0x55d3'5552'55d1'5550, 0x55d7'5556'55d5'5554, 0x55db'555a'55d9'5558, 0x55df'555e'55dd'555c,
5728 0x55e3'5562'55e1'5560, 0x55e7'5566'55e5'5564, 0x55eb'556a'55e9'5568, 0x55ef'556e'55ed'556c,
5729 0x55f3'5572'55f1'5570, 0x55f7'5576'55f5'5574, 0x55fb'557a'55f9'5578, 0x55ff'557e'55fd'557c});
5730 }
5731
TEST_F(Riscv64InterpreterTest,TestVssseg2e8_vlmul1)5732 TEST_F(Riscv64InterpreterTest, TestVssseg2e8_vlmul1) {
5733 TestVsssegXeXX<UInt8, 2, 1>(0x28208427, // vssseg2e8.v v8, (x1), x2, v0.t
5734 4,
5735 {0x5555'9181'5555'1000,
5736 0x5555'9383'5555'1202,
5737 0x5555'9585'5555'1404,
5738 0x5555'9787'5555'1606,
5739 0x5555'9989'5555'1808,
5740 0x5555'9b8b'5555'1a0a,
5741 0x5555'9d8d'5555'1c0c,
5742 0x5555'9f8f'5555'1e0e});
5743 }
5744
TEST_F(Riscv64InterpreterTest,TestVssseg2e8_vlmul2)5745 TEST_F(Riscv64InterpreterTest, TestVssseg2e8_vlmul2) {
5746 TestVsssegXeXX<UInt8, 2, 2>(0x28208427, // vssseg2e8.v v8, (x1), x2, v0.t
5747 4,
5748 {0x5555'a181'5555'2000,
5749 0x5555'a383'5555'2202,
5750 0x5555'a585'5555'2404,
5751 0x5555'a787'5555'2606,
5752 0x5555'a989'5555'2808,
5753 0x5555'ab8b'5555'2a0a,
5754 0x5555'ad8d'5555'2c0c,
5755 0x5555'af8f'5555'2e0e,
5756 0x5555'b191'5555'3010,
5757 0x5555'b393'5555'3212,
5758 0x5555'b595'5555'3414,
5759 0x5555'b797'5555'3616,
5760 0x5555'b999'5555'3818,
5761 0x5555'bb9b'5555'3a1a,
5762 0x5555'bd9d'5555'3c1c,
5763 0x5555'bf9f'5555'3e1e});
5764 }
5765
TEST_F(Riscv64InterpreterTest,TestVssseg2e8_vlmul4)5766 TEST_F(Riscv64InterpreterTest, TestVssseg2e8_vlmul4) {
5767 TestVsssegXeXX<UInt8, 2, 4>(
5768 0x28208427, // vssseg4e8.v v8, (x1), x2, v0.t
5769 4,
5770 {0x5555'c181'5555'4000, 0x5555'c383'5555'4202, 0x5555'c585'5555'4404, 0x5555'c787'5555'4606,
5771 0x5555'c989'5555'4808, 0x5555'cb8b'5555'4a0a, 0x5555'cd8d'5555'4c0c, 0x5555'cf8f'5555'4e0e,
5772 0x5555'd191'5555'5010, 0x5555'd393'5555'5212, 0x5555'd595'5555'5414, 0x5555'd797'5555'5616,
5773 0x5555'd999'5555'5818, 0x5555'db9b'5555'5a1a, 0x5555'dd9d'5555'5c1c, 0x5555'df9f'5555'5e1e,
5774 0x5555'e1a1'5555'6020, 0x5555'e3a3'5555'6222, 0x5555'e5a5'5555'6424, 0x5555'e7a7'5555'6626,
5775 0x5555'e9a9'5555'6828, 0x5555'ebab'5555'6a2a, 0x5555'edad'5555'6c2c, 0x5555'efaf'5555'6e2e,
5776 0x5555'f1b1'5555'7030, 0x5555'f3b3'5555'7232, 0x5555'f5b5'5555'7434, 0x5555'f7b7'5555'7636,
5777 0x5555'f9b9'5555'7838, 0x5555'fbbb'5555'7a3a, 0x5555'fdbd'5555'7c3c, 0x5555'ffbf'5555'7e3e});
5778 }
5779
TEST_F(Riscv64InterpreterTest,TestVssseg3e8_vlmul1)5780 TEST_F(Riscv64InterpreterTest, TestVssseg3e8_vlmul1) {
5781 TestVsssegXeXX<UInt8, 3, 1>(0x48208427, // vssseg3e8.v v8, (x1), x2, v0.t
5782 4,
5783 {0x55a1'9181'5520'1000,
5784 0x55a3'9383'5522'1202,
5785 0x55a5'9585'5524'1404,
5786 0x55a7'9787'5526'1606,
5787 0x55a9'9989'5528'1808,
5788 0x55ab'9b8b'552a'1a0a,
5789 0x55ad'9d8d'552c'1c0c,
5790 0x55af'9f8f'552e'1e0e});
5791 }
5792
TEST_F(Riscv64InterpreterTest,TestVssseg3e8_vlmul2)5793 TEST_F(Riscv64InterpreterTest, TestVssseg3e8_vlmul2) {
5794 TestVsssegXeXX<UInt8, 3, 2>(0x48208427, // vssseg3e8.v v8, (x1), x2, v0.t
5795 4,
5796 {0x55c1'a181'5540'2000,
5797 0x55c3'a383'5542'2202,
5798 0x55c5'a585'5544'2404,
5799 0x55c7'a787'5546'2606,
5800 0x55c9'a989'5548'2808,
5801 0x55cb'ab8b'554a'2a0a,
5802 0x55cd'ad8d'554c'2c0c,
5803 0x55cf'af8f'554e'2e0e,
5804 0x55d1'b191'5550'3010,
5805 0x55d3'b393'5552'3212,
5806 0x55d5'b595'5554'3414,
5807 0x55d7'b797'5556'3616,
5808 0x55d9'b999'5558'3818,
5809 0x55db'bb9b'555a'3a1a,
5810 0x55dd'bd9d'555c'3c1c,
5811 0x55df'bf9f'555e'3e1e});
5812 }
5813
TEST_F(Riscv64InterpreterTest,TestVssseg4e8_vlmul1)5814 TEST_F(Riscv64InterpreterTest, TestVssseg4e8_vlmul1) {
5815 TestVsssegXeXX<UInt8, 4, 1>(0x68208427, // vssseg4e8.v v8, (x1), x2, v0.t
5816 4,
5817 {0xb1a1'9181'3020'1000,
5818 0xb3a3'9383'3222'1202,
5819 0xb5a5'9585'3424'1404,
5820 0xb7a7'9787'3626'1606,
5821 0xb9a9'9989'3828'1808,
5822 0xbbab'9b8b'3a2a'1a0a,
5823 0xbdad'9d8d'3c2c'1c0c,
5824 0xbfaf'9f8f'3e2e'1e0e});
5825 }
5826
TEST_F(Riscv64InterpreterTest,TestVssseg4e8_vlmul2)5827 TEST_F(Riscv64InterpreterTest, TestVssseg4e8_vlmul2) {
5828 TestVsssegXeXX<UInt8, 4, 2>(0x68208427, // vssseg4e8.v v8, (x1), x2, v0.t
5829 4,
5830 {0xe1c1'a181'6040'2000,
5831 0xe3c3'a383'6242'2202,
5832 0xe5c5'a585'6444'2404,
5833 0xe7c7'a787'6646'2606,
5834 0xe9c9'a989'6848'2808,
5835 0xebcb'ab8b'6a4a'2a0a,
5836 0xedcd'ad8d'6c4c'2c0c,
5837 0xefcf'af8f'6e4e'2e0e,
5838 0xf1d1'b191'7050'3010,
5839 0xf3d3'b393'7252'3212,
5840 0xf5d5'b595'7454'3414,
5841 0xf7d7'b797'7656'3616,
5842 0xf9d9'b999'7858'3818,
5843 0xfbdb'bb9b'7a5a'3a1a,
5844 0xfddd'bd9d'7c5c'3c1c,
5845 0xffdf'bf9f'7e5e'3e1e});
5846 }
5847
TEST_F(Riscv64InterpreterTest,TestVssseg5e8)5848 TEST_F(Riscv64InterpreterTest, TestVssseg5e8) {
5849 TestVsssegXeXX<UInt8, 5, 1>(0x88208427, // vssseg5e8.v v8, (x1), x2, v0.t
5850 8,
5851 {0x5555'5540'3020'1000,
5852 0x5555'55c1'b1a1'9181,
5853 0x5555'5542'3222'1202,
5854 0x5555'55c3'b3a3'9383,
5855 0x5555'5544'3424'1404,
5856 0x5555'55c5'b5a5'9585,
5857 0x5555'5546'3626'1606,
5858 0x5555'55c7'b7a7'9787,
5859 0x5555'5548'3828'1808,
5860 0x5555'55c9'b9a9'9989,
5861 0x5555'554a'3a2a'1a0a,
5862 0x5555'55cb'bbab'9b8b,
5863 0x5555'554c'3c2c'1c0c,
5864 0x5555'55cd'bdad'9d8d,
5865 0x5555'554e'3e2e'1e0e,
5866 0x5555'55cf'bfaf'9f8f});
5867 }
5868
TEST_F(Riscv64InterpreterTest,TestVssseg6e8)5869 TEST_F(Riscv64InterpreterTest, TestVssseg6e8) {
5870 TestVsssegXeXX<UInt8, 6, 1>(0xa8208427, // vssseg6e8.v v8, (x1), x2, v0.t
5871 8,
5872 {0x5555'5040'3020'1000,
5873 0x5555'd1c1'b1a1'9181,
5874 0x5555'5242'3222'1202,
5875 0x5555'd3c3'b3a3'9383,
5876 0x5555'5444'3424'1404,
5877 0x5555'd5c5'b5a5'9585,
5878 0x5555'5646'3626'1606,
5879 0x5555'd7c7'b7a7'9787,
5880 0x5555'5848'3828'1808,
5881 0x5555'd9c9'b9a9'9989,
5882 0x5555'5a4a'3a2a'1a0a,
5883 0x5555'dbcb'bbab'9b8b,
5884 0x5555'5c4c'3c2c'1c0c,
5885 0x5555'ddcd'bdad'9d8d,
5886 0x5555'5e4e'3e2e'1e0e,
5887 0x5555'dfcf'bfaf'9f8f});
5888 }
5889
TEST_F(Riscv64InterpreterTest,TestVssseg7e8)5890 TEST_F(Riscv64InterpreterTest, TestVssseg7e8) {
5891 TestVsssegXeXX<UInt8, 7, 1>(0xc8208427, // vssseg7e8.v v8, (x1), x2, v0.t
5892 8,
5893 {0x5560'5040'3020'1000,
5894 0x55e1'd1c1'b1a1'9181,
5895 0x5562'5242'3222'1202,
5896 0x55e3'd3c3'b3a3'9383,
5897 0x5564'5444'3424'1404,
5898 0x55e5'd5c5'b5a5'9585,
5899 0x5566'5646'3626'1606,
5900 0x55e7'd7c7'b7a7'9787,
5901 0x5568'5848'3828'1808,
5902 0x55e9'd9c9'b9a9'9989,
5903 0x556a'5a4a'3a2a'1a0a,
5904 0x55eb'dbcb'bbab'9b8b,
5905 0x556c'5c4c'3c2c'1c0c,
5906 0x55ed'ddcd'bdad'9d8d,
5907 0x556e'5e4e'3e2e'1e0e,
5908 0x55ef'dfcf'bfaf'9f8f});
5909 }
5910
TEST_F(Riscv64InterpreterTest,TestVssseg8e8)5911 TEST_F(Riscv64InterpreterTest, TestVssseg8e8) {
5912 TestVsssegXeXX<UInt8, 8, 1>(0xe8208427, // vssseg8e8.v v8, (x1), x2, v0.t
5913 8,
5914 {0x7060'5040'3020'1000,
5915 0xf1e1'd1c1'b1a1'9181,
5916 0x7262'5242'3222'1202,
5917 0xf3e3'd3c3'b3a3'9383,
5918 0x7464'5444'3424'1404,
5919 0xf5e5'd5c5'b5a5'9585,
5920 0x7666'5646'3626'1606,
5921 0xf7e7'd7c7'b7a7'9787,
5922 0x7868'5848'3828'1808,
5923 0xf9e9'd9c9'b9a9'9989,
5924 0x7a6a'5a4a'3a2a'1a0a,
5925 0xfbeb'dbcb'bbab'9b8b,
5926 0x7c6c'5c4c'3c2c'1c0c,
5927 0xfded'ddcd'bdad'9d8d,
5928 0x7e6e'5e4e'3e2e'1e0e,
5929 0xffef'dfcf'bfaf'9f8f});
5930 }
5931
TEST_F(Riscv64InterpreterTest,TestVsse16_vlmul1)5932 TEST_F(Riscv64InterpreterTest, TestVsse16_vlmul1) {
5933 TestVsssegXeXX<UInt16, 1, 1>(0x820d427, // vsse16.v v8, (x1), x2, v0.t
5934 8,
5935 {0x5555'5555'5555'8100,
5936 0x5555'5555'5555'8302,
5937 0x5555'5555'5555'8504,
5938 0x5555'5555'5555'8706,
5939 0x5555'5555'5555'8908,
5940 0x5555'5555'5555'8b0a,
5941 0x5555'5555'5555'8d0c,
5942 0x5555'5555'5555'8f0e});
5943 }
5944
TEST_F(Riscv64InterpreterTest,TestVsse16_vlmul2)5945 TEST_F(Riscv64InterpreterTest, TestVsse16_vlmul2) {
5946 TestVsssegXeXX<UInt16, 1, 2>(0x820d427, // vsse16.v v8, (x1), x2, v0.t
5947 8,
5948 {0x5555'5555'5555'8100,
5949 0x5555'5555'5555'8302,
5950 0x5555'5555'5555'8504,
5951 0x5555'5555'5555'8706,
5952 0x5555'5555'5555'8908,
5953 0x5555'5555'5555'8b0a,
5954 0x5555'5555'5555'8d0c,
5955 0x5555'5555'5555'8f0e,
5956 0x5555'5555'5555'9110,
5957 0x5555'5555'5555'9312,
5958 0x5555'5555'5555'9514,
5959 0x5555'5555'5555'9716,
5960 0x5555'5555'5555'9918,
5961 0x5555'5555'5555'9b1a,
5962 0x5555'5555'5555'9d1c,
5963 0x5555'5555'5555'9f1e});
5964 }
5965
TEST_F(Riscv64InterpreterTest,TestVsse16_vlmul4)5966 TEST_F(Riscv64InterpreterTest, TestVsse16_vlmul4) {
5967 TestVsssegXeXX<UInt16, 1, 4>(
5968 0x820d427, // vsse16.v v8, (x1), x2, v0.t
5969 8,
5970 {0x5555'5555'5555'8100, 0x5555'5555'5555'8302, 0x5555'5555'5555'8504, 0x5555'5555'5555'8706,
5971 0x5555'5555'5555'8908, 0x5555'5555'5555'8b0a, 0x5555'5555'5555'8d0c, 0x5555'5555'5555'8f0e,
5972 0x5555'5555'5555'9110, 0x5555'5555'5555'9312, 0x5555'5555'5555'9514, 0x5555'5555'5555'9716,
5973 0x5555'5555'5555'9918, 0x5555'5555'5555'9b1a, 0x5555'5555'5555'9d1c, 0x5555'5555'5555'9f1e,
5974 0x5555'5555'5555'a120, 0x5555'5555'5555'a322, 0x5555'5555'5555'a524, 0x5555'5555'5555'a726,
5975 0x5555'5555'5555'a928, 0x5555'5555'5555'ab2a, 0x5555'5555'5555'ad2c, 0x5555'5555'5555'af2e,
5976 0x5555'5555'5555'b130, 0x5555'5555'5555'b332, 0x5555'5555'5555'b534, 0x5555'5555'5555'b736,
5977 0x5555'5555'5555'b938, 0x5555'5555'5555'bb3a, 0x5555'5555'5555'bd3c, 0x5555'5555'5555'bf3e});
5978 }
5979
TEST_F(Riscv64InterpreterTest,TestVsse16_vlmul8)5980 TEST_F(Riscv64InterpreterTest, TestVsse16_vlmul8) {
5981 TestVsssegXeXX<UInt16, 1, 8>(
5982 0x820d427, // vsse16.v v8, (x1), x2, v0.t
5983 4,
5984 {0x5555'8302'5555'8100, 0x5555'8706'5555'8504, 0x5555'8b0a'5555'8908, 0x5555'8f0e'5555'8d0c,
5985 0x5555'9312'5555'9110, 0x5555'9716'5555'9514, 0x5555'9b1a'5555'9918, 0x5555'9f1e'5555'9d1c,
5986 0x5555'a322'5555'a120, 0x5555'a726'5555'a524, 0x5555'ab2a'5555'a928, 0x5555'af2e'5555'ad2c,
5987 0x5555'b332'5555'b130, 0x5555'b736'5555'b534, 0x5555'bb3a'5555'b938, 0x5555'bf3e'5555'bd3c,
5988 0x5555'c342'5555'c140, 0x5555'c746'5555'c544, 0x5555'cb4a'5555'c948, 0x5555'cf4e'5555'cd4c,
5989 0x5555'd352'5555'd150, 0x5555'd756'5555'd554, 0x5555'db5a'5555'd958, 0x5555'df5e'5555'dd5c,
5990 0x5555'e362'5555'e160, 0x5555'e766'5555'e564, 0x5555'eb6a'5555'e968, 0x5555'ef6e'5555'ed6c,
5991 0x5555'f372'5555'f170, 0x5555'f776'5555'f574, 0x5555'fb7a'5555'f978, 0x5555'ff7e'5555'fd7c});
5992 }
5993
TEST_F(Riscv64InterpreterTest,TestVssseg2e16_vlmul1)5994 TEST_F(Riscv64InterpreterTest, TestVssseg2e16_vlmul1) {
5995 TestVsssegXeXX<UInt16, 2, 1>(0x2820d427, // vssseg2e16.v v8, (x1), x2, v0.t
5996 8,
5997 {0x5555'5555'9110'8100,
5998 0x5555'5555'9312'8302,
5999 0x5555'5555'9514'8504,
6000 0x5555'5555'9716'8706,
6001 0x5555'5555'9918'8908,
6002 0x5555'5555'9b1a'8b0a,
6003 0x5555'5555'9d1c'8d0c,
6004 0x5555'5555'9f1e'8f0e});
6005 }
6006
TEST_F(Riscv64InterpreterTest,TestVssseg2e16_vlmul2)6007 TEST_F(Riscv64InterpreterTest, TestVssseg2e16_vlmul2) {
6008 TestVsssegXeXX<UInt16, 2, 2>(0x2820d427, // vssseg2e16.v v8, (x1), x2, v0.t
6009 8,
6010 {0x5555'5555'a120'8100,
6011 0x5555'5555'a322'8302,
6012 0x5555'5555'a524'8504,
6013 0x5555'5555'a726'8706,
6014 0x5555'5555'a928'8908,
6015 0x5555'5555'ab2a'8b0a,
6016 0x5555'5555'ad2c'8d0c,
6017 0x5555'5555'af2e'8f0e,
6018 0x5555'5555'b130'9110,
6019 0x5555'5555'b332'9312,
6020 0x5555'5555'b534'9514,
6021 0x5555'5555'b736'9716,
6022 0x5555'5555'b938'9918,
6023 0x5555'5555'bb3a'9b1a,
6024 0x5555'5555'bd3c'9d1c,
6025 0x5555'5555'bf3e'9f1e});
6026 }
6027
TEST_F(Riscv64InterpreterTest,TestVssseg2e16_vlmul4)6028 TEST_F(Riscv64InterpreterTest, TestVssseg2e16_vlmul4) {
6029 TestVsssegXeXX<UInt16, 2, 4>(
6030 0x2820d427, // vssseg2e16.v v8, (x1), x2, v0.t
6031 8,
6032 {0x5555'5555'c140'8100, 0x5555'5555'c342'8302, 0x5555'5555'c544'8504, 0x5555'5555'c746'8706,
6033 0x5555'5555'c948'8908, 0x5555'5555'cb4a'8b0a, 0x5555'5555'cd4c'8d0c, 0x5555'5555'cf4e'8f0e,
6034 0x5555'5555'd150'9110, 0x5555'5555'd352'9312, 0x5555'5555'd554'9514, 0x5555'5555'd756'9716,
6035 0x5555'5555'd958'9918, 0x5555'5555'db5a'9b1a, 0x5555'5555'dd5c'9d1c, 0x5555'5555'df5e'9f1e,
6036 0x5555'5555'e160'a120, 0x5555'5555'e362'a322, 0x5555'5555'e564'a524, 0x5555'5555'e766'a726,
6037 0x5555'5555'e968'a928, 0x5555'5555'eb6a'ab2a, 0x5555'5555'ed6c'ad2c, 0x5555'5555'ef6e'af2e,
6038 0x5555'5555'f170'b130, 0x5555'5555'f372'b332, 0x5555'5555'f574'b534, 0x5555'5555'f776'b736,
6039 0x5555'5555'f978'b938, 0x5555'5555'fb7a'bb3a, 0x5555'5555'fd7c'bd3c, 0x5555'5555'ff7e'bf3e});
6040 }
6041
TEST_F(Riscv64InterpreterTest,TestVssseg3e16_vlmul1)6042 TEST_F(Riscv64InterpreterTest, TestVssseg3e16_vlmul1) {
6043 TestVsssegXeXX<UInt16, 3, 1>(0x4820d427, // vssseg3e16.v v8, (x1), x2, v0.t
6044 8,
6045 {0x5555'a120'9110'8100,
6046 0x5555'a322'9312'8302,
6047 0x5555'a524'9514'8504,
6048 0x5555'a726'9716'8706,
6049 0x5555'a928'9918'8908,
6050 0x5555'ab2a'9b1a'8b0a,
6051 0x5555'ad2c'9d1c'8d0c,
6052 0x5555'af2e'9f1e'8f0e});
6053 }
6054
TEST_F(Riscv64InterpreterTest,TestVssseg3e16_vlmul2)6055 TEST_F(Riscv64InterpreterTest, TestVssseg3e16_vlmul2) {
6056 TestVsssegXeXX<UInt16, 3, 2>(0x4820d427, // vssseg3e16.v v8, (x1), x2, v0.t
6057 8,
6058 {0x5555'c140'a120'8100,
6059 0x5555'c342'a322'8302,
6060 0x5555'c544'a524'8504,
6061 0x5555'c746'a726'8706,
6062 0x5555'c948'a928'8908,
6063 0x5555'cb4a'ab2a'8b0a,
6064 0x5555'cd4c'ad2c'8d0c,
6065 0x5555'cf4e'af2e'8f0e,
6066 0x5555'd150'b130'9110,
6067 0x5555'd352'b332'9312,
6068 0x5555'd554'b534'9514,
6069 0x5555'd756'b736'9716,
6070 0x5555'd958'b938'9918,
6071 0x5555'db5a'bb3a'9b1a,
6072 0x5555'dd5c'bd3c'9d1c,
6073 0x5555'df5e'bf3e'9f1e});
6074 }
6075
TEST_F(Riscv64InterpreterTest,TestVssseg4e16_vlmul1)6076 TEST_F(Riscv64InterpreterTest, TestVssseg4e16_vlmul1) {
6077 TestVsssegXeXX<UInt16, 4, 1>(0x6820d427, // vssseg4e16.v v8, (x1), x2, v0.t
6078 8,
6079 {0xb130'a120'9110'8100,
6080 0xb332'a322'9312'8302,
6081 0xb534'a524'9514'8504,
6082 0xb736'a726'9716'8706,
6083 0xb938'a928'9918'8908,
6084 0xbb3a'ab2a'9b1a'8b0a,
6085 0xbd3c'ad2c'9d1c'8d0c,
6086 0xbf3e'af2e'9f1e'8f0e});
6087 }
6088
TEST_F(Riscv64InterpreterTest,TestVssseg4e16_vlmul2)6089 TEST_F(Riscv64InterpreterTest, TestVssseg4e16_vlmul2) {
6090 TestVsssegXeXX<UInt16, 4, 2>(0x6820d427, // vssseg4e16.v v8, (x1), x2, v0.t
6091 8,
6092 {0xe160'c140'a120'8100,
6093 0xe362'c342'a322'8302,
6094 0xe564'c544'a524'8504,
6095 0xe766'c746'a726'8706,
6096 0xe968'c948'a928'8908,
6097 0xeb6a'cb4a'ab2a'8b0a,
6098 0xed6c'cd4c'ad2c'8d0c,
6099 0xef6e'cf4e'af2e'8f0e,
6100 0xf170'd150'b130'9110,
6101 0xf372'd352'b332'9312,
6102 0xf574'd554'b534'9514,
6103 0xf776'd756'b736'9716,
6104 0xf978'd958'b938'9918,
6105 0xfb7a'db5a'bb3a'9b1a,
6106 0xfd7c'dd5c'bd3c'9d1c,
6107 0xff7e'df5e'bf3e'9f1e});
6108 }
6109
TEST_F(Riscv64InterpreterTest,TestVssseg5e16)6110 TEST_F(Riscv64InterpreterTest, TestVssseg5e16) {
6111 TestVsssegXeXX<UInt16, 5, 1>(0x8820d427, // vssseg5e16.v v8, (x1), x2, v0.t
6112 16,
6113 {0xb130'a120'9110'8100,
6114 0x5555'5555'5555'c140,
6115 0xb332'a322'9312'8302,
6116 0x5555'5555'5555'c342,
6117 0xb534'a524'9514'8504,
6118 0x5555'5555'5555'c544,
6119 0xb736'a726'9716'8706,
6120 0x5555'5555'5555'c746,
6121 0xb938'a928'9918'8908,
6122 0x5555'5555'5555'c948,
6123 0xbb3a'ab2a'9b1a'8b0a,
6124 0x5555'5555'5555'cb4a,
6125 0xbd3c'ad2c'9d1c'8d0c,
6126 0x5555'5555'5555'cd4c,
6127 0xbf3e'af2e'9f1e'8f0e,
6128 0x5555'5555'5555'cf4e});
6129 }
6130
TEST_F(Riscv64InterpreterTest,TestVssseg6e16)6131 TEST_F(Riscv64InterpreterTest, TestVssseg6e16) {
6132 TestVsssegXeXX<UInt16, 6, 1>(0xa820d427, // vssseg6e16.v v8, (x1), x2, v0.t
6133 16,
6134 {0xb130'a120'9110'8100,
6135 0x5555'5555'd150'c140,
6136 0xb332'a322'9312'8302,
6137 0x5555'5555'd352'c342,
6138 0xb534'a524'9514'8504,
6139 0x5555'5555'd554'c544,
6140 0xb736'a726'9716'8706,
6141 0x5555'5555'd756'c746,
6142 0xb938'a928'9918'8908,
6143 0x5555'5555'd958'c948,
6144 0xbb3a'ab2a'9b1a'8b0a,
6145 0x5555'5555'db5a'cb4a,
6146 0xbd3c'ad2c'9d1c'8d0c,
6147 0x5555'5555'dd5c'cd4c,
6148 0xbf3e'af2e'9f1e'8f0e,
6149 0x5555'5555'df5e'cf4e});
6150 }
6151
TEST_F(Riscv64InterpreterTest,TestVssseg7e16)6152 TEST_F(Riscv64InterpreterTest, TestVssseg7e16) {
6153 TestVsssegXeXX<UInt16, 7, 1>(0xc820d427, // vssseg7e16.v v8, (x1), x2, v0.t
6154 16,
6155 {0xb130'a120'9110'8100,
6156 0x5555'e160'd150'c140,
6157 0xb332'a322'9312'8302,
6158 0x5555'e362'd352'c342,
6159 0xb534'a524'9514'8504,
6160 0x5555'e564'd554'c544,
6161 0xb736'a726'9716'8706,
6162 0x5555'e766'd756'c746,
6163 0xb938'a928'9918'8908,
6164 0x5555'e968'd958'c948,
6165 0xbb3a'ab2a'9b1a'8b0a,
6166 0x5555'eb6a'db5a'cb4a,
6167 0xbd3c'ad2c'9d1c'8d0c,
6168 0x5555'ed6c'dd5c'cd4c,
6169 0xbf3e'af2e'9f1e'8f0e,
6170 0x5555'ef6e'df5e'cf4e});
6171 }
6172
TEST_F(Riscv64InterpreterTest,TestVssseg8e16)6173 TEST_F(Riscv64InterpreterTest, TestVssseg8e16) {
6174 TestVsssegXeXX<UInt16, 8, 1>(0xe820d427, // vssseg8e16.v v8, (x1), x2, v0.t
6175 16,
6176 {0xb130'a120'9110'8100,
6177 0xf170'e160'd150'c140,
6178 0xb332'a322'9312'8302,
6179 0xf372'e362'd352'c342,
6180 0xb534'a524'9514'8504,
6181 0xf574'e564'd554'c544,
6182 0xb736'a726'9716'8706,
6183 0xf776'e766'd756'c746,
6184 0xb938'a928'9918'8908,
6185 0xf978'e968'd958'c948,
6186 0xbb3a'ab2a'9b1a'8b0a,
6187 0xfb7a'eb6a'db5a'cb4a,
6188 0xbd3c'ad2c'9d1c'8d0c,
6189 0xfd7c'ed6c'dd5c'cd4c,
6190 0xbf3e'af2e'9f1e'8f0e,
6191 0xff7e'ef6e'df5e'cf4e});
6192 }
6193
TEST_F(Riscv64InterpreterTest,TestVsse32_vlmul1)6194 TEST_F(Riscv64InterpreterTest, TestVsse32_vlmul1) {
6195 TestVsssegXeXX<UInt32, 1, 1>(0x820e427, // vsse32.v v8, (x1), x2, v0.t
6196 16,
6197 {0x5555'5555'8302'8100,
6198 0x5555'5555'5555'5555,
6199 0x5555'5555'8706'8504,
6200 0x5555'5555'5555'5555,
6201 0x5555'5555'8b0a'8908,
6202 0x5555'5555'5555'5555,
6203 0x5555'5555'8f0e'8d0c});
6204 }
6205
TEST_F(Riscv64InterpreterTest,TestVsse32_vlmul2)6206 TEST_F(Riscv64InterpreterTest, TestVsse32_vlmul2) {
6207 TestVsssegXeXX<UInt32, 1, 2>(0x820e427, // vsse32.v v8, (x1), x2, v0.t
6208 16,
6209 {0x5555'5555'8302'8100,
6210 0x5555'5555'5555'5555,
6211 0x5555'5555'8706'8504,
6212 0x5555'5555'5555'5555,
6213 0x5555'5555'8b0a'8908,
6214 0x5555'5555'5555'5555,
6215 0x5555'5555'8f0e'8d0c,
6216 0x5555'5555'5555'5555,
6217 0x5555'5555'9312'9110,
6218 0x5555'5555'5555'5555,
6219 0x5555'5555'9716'9514,
6220 0x5555'5555'5555'5555,
6221 0x5555'5555'9b1a'9918,
6222 0x5555'5555'5555'5555,
6223 0x5555'5555'9f1e'9d1c});
6224 }
6225
TEST_F(Riscv64InterpreterTest,TestVsse32_vlmul4)6226 TEST_F(Riscv64InterpreterTest, TestVsse32_vlmul4) {
6227 TestVsssegXeXX<UInt32, 1, 4>(
6228 0x820e427, // vsse32.v v8, (x1), x2, v0.t
6229 16,
6230 {0x5555'5555'8302'8100, 0x5555'5555'5555'5555, 0x5555'5555'8706'8504, 0x5555'5555'5555'5555,
6231 0x5555'5555'8b0a'8908, 0x5555'5555'5555'5555, 0x5555'5555'8f0e'8d0c, 0x5555'5555'5555'5555,
6232 0x5555'5555'9312'9110, 0x5555'5555'5555'5555, 0x5555'5555'9716'9514, 0x5555'5555'5555'5555,
6233 0x5555'5555'9b1a'9918, 0x5555'5555'5555'5555, 0x5555'5555'9f1e'9d1c, 0x5555'5555'5555'5555,
6234 0x5555'5555'a322'a120, 0x5555'5555'5555'5555, 0x5555'5555'a726'a524, 0x5555'5555'5555'5555,
6235 0x5555'5555'ab2a'a928, 0x5555'5555'5555'5555, 0x5555'5555'af2e'ad2c, 0x5555'5555'5555'5555,
6236 0x5555'5555'b332'b130, 0x5555'5555'5555'5555, 0x5555'5555'b736'b534, 0x5555'5555'5555'5555,
6237 0x5555'5555'bb3a'b938, 0x5555'5555'5555'5555, 0x5555'5555'bf3e'bd3c});
6238 }
6239
TEST_F(Riscv64InterpreterTest,TestVsse32_vlmul8)6240 TEST_F(Riscv64InterpreterTest, TestVsse32_vlmul8) {
6241 TestVsssegXeXX<UInt32, 1, 8>(
6242 0x820e427, // vsse32.v v8, (x1), x2, v0.t
6243 8,
6244 {0x5555'5555'8302'8100, 0x5555'5555'8706'8504, 0x5555'5555'8b0a'8908, 0x5555'5555'8f0e'8d0c,
6245 0x5555'5555'9312'9110, 0x5555'5555'9716'9514, 0x5555'5555'9b1a'9918, 0x5555'5555'9f1e'9d1c,
6246 0x5555'5555'a322'a120, 0x5555'5555'a726'a524, 0x5555'5555'ab2a'a928, 0x5555'5555'af2e'ad2c,
6247 0x5555'5555'b332'b130, 0x5555'5555'b736'b534, 0x5555'5555'bb3a'b938, 0x5555'5555'bf3e'bd3c,
6248 0x5555'5555'c342'c140, 0x5555'5555'c746'c544, 0x5555'5555'cb4a'c948, 0x5555'5555'cf4e'cd4c,
6249 0x5555'5555'd352'd150, 0x5555'5555'd756'd554, 0x5555'5555'db5a'd958, 0x5555'5555'df5e'dd5c,
6250 0x5555'5555'e362'e160, 0x5555'5555'e766'e564, 0x5555'5555'eb6a'e968, 0x5555'5555'ef6e'ed6c,
6251 0x5555'5555'f372'f170, 0x5555'5555'f776'f574, 0x5555'5555'fb7a'f978, 0x5555'5555'ff7e'fd7c});
6252 }
6253
TEST_F(Riscv64InterpreterTest,TestVssseg2e32_vlmul1)6254 TEST_F(Riscv64InterpreterTest, TestVssseg2e32_vlmul1) {
6255 TestVsssegXeXX<UInt32, 2, 1>(0x2820e427, // vssseg2e32.v v8, (x1), x2, v0.t
6256 16,
6257 {0x9312'9110'8302'8100,
6258 0x5555'5555'5555'5555,
6259 0x9716'9514'8706'8504,
6260 0x5555'5555'5555'5555,
6261 0x9b1a'9918'8b0a'8908,
6262 0x5555'5555'5555'5555,
6263 0x9f1e'9d1c'8f0e'8d0c});
6264 }
6265
TEST_F(Riscv64InterpreterTest,TestVssseg2e32_vlmul2)6266 TEST_F(Riscv64InterpreterTest, TestVssseg2e32_vlmul2) {
6267 TestVsssegXeXX<UInt32, 2, 2>(0x2820e427, // vssseg2e32.v v8, (x1), x2, v0.t
6268 16,
6269 {0xa322'a120'8302'8100,
6270 0x5555'5555'5555'5555,
6271 0xa726'a524'8706'8504,
6272 0x5555'5555'5555'5555,
6273 0xab2a'a928'8b0a'8908,
6274 0x5555'5555'5555'5555,
6275 0xaf2e'ad2c'8f0e'8d0c,
6276 0x5555'5555'5555'5555,
6277 0xb332'b130'9312'9110,
6278 0x5555'5555'5555'5555,
6279 0xb736'b534'9716'9514,
6280 0x5555'5555'5555'5555,
6281 0xbb3a'b938'9b1a'9918,
6282 0x5555'5555'5555'5555,
6283 0xbf3e'bd3c'9f1e'9d1c});
6284 }
6285
TEST_F(Riscv64InterpreterTest,TestVssseg2e32_vlmul4)6286 TEST_F(Riscv64InterpreterTest, TestVssseg2e32_vlmul4) {
6287 TestVsssegXeXX<UInt32, 2, 4>(
6288 0x2820e427, // vssseg2e32.v v8, (x1), x2, v0.t
6289 16,
6290 {0xc342'c140'8302'8100, 0x5555'5555'5555'5555, 0xc746'c544'8706'8504, 0x5555'5555'5555'5555,
6291 0xcb4a'c948'8b0a'8908, 0x5555'5555'5555'5555, 0xcf4e'cd4c'8f0e'8d0c, 0x5555'5555'5555'5555,
6292 0xd352'd150'9312'9110, 0x5555'5555'5555'5555, 0xd756'd554'9716'9514, 0x5555'5555'5555'5555,
6293 0xdb5a'd958'9b1a'9918, 0x5555'5555'5555'5555, 0xdf5e'dd5c'9f1e'9d1c, 0x5555'5555'5555'5555,
6294 0xe362'e160'a322'a120, 0x5555'5555'5555'5555, 0xe766'e564'a726'a524, 0x5555'5555'5555'5555,
6295 0xeb6a'e968'ab2a'a928, 0x5555'5555'5555'5555, 0xef6e'ed6c'af2e'ad2c, 0x5555'5555'5555'5555,
6296 0xf372'f170'b332'b130, 0x5555'5555'5555'5555, 0xf776'f574'b736'b534, 0x5555'5555'5555'5555,
6297 0xfb7a'f978'bb3a'b938, 0x5555'5555'5555'5555, 0xff7e'fd7c'bf3e'bd3c});
6298 }
6299
TEST_F(Riscv64InterpreterTest,TestVssseg3e32_vlmul1)6300 TEST_F(Riscv64InterpreterTest, TestVssseg3e32_vlmul1) {
6301 TestVsssegXeXX<UInt32, 3, 1>(0x4820e427, // vssseg3e32.v v8, (x1), x2, v0.t
6302 16,
6303 {0x9312'9110'8302'8100,
6304 0x5555'5555'a322'a120,
6305 0x9716'9514'8706'8504,
6306 0x5555'5555'a726'a524,
6307 0x9b1a'9918'8b0a'8908,
6308 0x5555'5555'ab2a'a928,
6309 0x9f1e'9d1c'8f0e'8d0c,
6310 0x5555'5555'af2e'ad2c});
6311 }
6312
TEST_F(Riscv64InterpreterTest,TestVssseg3e32_vlmul2)6313 TEST_F(Riscv64InterpreterTest, TestVssseg3e32_vlmul2) {
6314 TestVsssegXeXX<UInt32, 3, 2>(0x4820e427, // vssseg3e32.v v8, (x1), x2, v0.t
6315 16,
6316 {0xa322'a120'8302'8100,
6317 0x5555'5555'c342'c140,
6318 0xa726'a524'8706'8504,
6319 0x5555'5555'c746'c544,
6320 0xab2a'a928'8b0a'8908,
6321 0x5555'5555'cb4a'c948,
6322 0xaf2e'ad2c'8f0e'8d0c,
6323 0x5555'5555'cf4e'cd4c,
6324 0xb332'b130'9312'9110,
6325 0x5555'5555'd352'd150,
6326 0xb736'b534'9716'9514,
6327 0x5555'5555'd756'd554,
6328 0xbb3a'b938'9b1a'9918,
6329 0x5555'5555'db5a'd958,
6330 0xbf3e'bd3c'9f1e'9d1c,
6331 0x5555'5555'df5e'dd5c});
6332 }
6333
TEST_F(Riscv64InterpreterTest,TestVssseg4e32_vlmul1)6334 TEST_F(Riscv64InterpreterTest, TestVssseg4e32_vlmul1) {
6335 TestVsssegXeXX<UInt32, 4, 1>(0x6820e427, // vssseg4e32.v v8, (x1), x2, v0.t
6336 16,
6337 {0x9312'9110'8302'8100,
6338 0xb332'b130'a322'a120,
6339 0x9716'9514'8706'8504,
6340 0xb736'b534'a726'a524,
6341 0x9b1a'9918'8b0a'8908,
6342 0xbb3a'b938'ab2a'a928,
6343 0x9f1e'9d1c'8f0e'8d0c,
6344 0xbf3e'bd3c'af2e'ad2c});
6345 }
6346
TEST_F(Riscv64InterpreterTest,TestVssseg4e32_vlmul2)6347 TEST_F(Riscv64InterpreterTest, TestVssseg4e32_vlmul2) {
6348 TestVsssegXeXX<UInt32, 4, 2>(0x6820e427, // vssseg4e32.v v8, (x1), x2, v0.t
6349 16,
6350 {0xa322'a120'8302'8100,
6351 0xe362'e160'c342'c140,
6352 0xa726'a524'8706'8504,
6353 0xe766'e564'c746'c544,
6354 0xab2a'a928'8b0a'8908,
6355 0xeb6a'e968'cb4a'c948,
6356 0xaf2e'ad2c'8f0e'8d0c,
6357 0xef6e'ed6c'cf4e'cd4c,
6358 0xb332'b130'9312'9110,
6359 0xf372'f170'd352'd150,
6360 0xb736'b534'9716'9514,
6361 0xf776'f574'd756'd554,
6362 0xbb3a'b938'9b1a'9918,
6363 0xfb7a'f978'db5a'd958,
6364 0xbf3e'bd3c'9f1e'9d1c,
6365 0xff7e'fd7c'df5e'dd5c});
6366 }
6367
TEST_F(Riscv64InterpreterTest,TestVssseg5e32)6368 TEST_F(Riscv64InterpreterTest, TestVssseg5e32) {
6369 TestVsssegXeXX<UInt32, 5, 1>(0x8820e427, // vssseg5e32.v v8, (x1), x2, v0.t
6370 32,
6371 {0x9312'9110'8302'8100,
6372 0xb332'b130'a322'a120,
6373 0x5555'5555'c342'c140,
6374 0x5555'5555'5555'5555,
6375 0x9716'9514'8706'8504,
6376 0xb736'b534'a726'a524,
6377 0x5555'5555'c746'c544,
6378 0x5555'5555'5555'5555,
6379 0x9b1a'9918'8b0a'8908,
6380 0xbb3a'b938'ab2a'a928,
6381 0x5555'5555'cb4a'c948,
6382 0x5555'5555'5555'5555,
6383 0x9f1e'9d1c'8f0e'8d0c,
6384 0xbf3e'bd3c'af2e'ad2c,
6385 0x5555'5555'cf4e'cd4c});
6386 }
6387
TEST_F(Riscv64InterpreterTest,TestVssseg6e32)6388 TEST_F(Riscv64InterpreterTest, TestVssseg6e32) {
6389 TestVsssegXeXX<UInt32, 6, 1>(0xa820e427, // vssseg6e32.v v8, (x1), x2, v0.t
6390 32,
6391 {0x9312'9110'8302'8100,
6392 0xb332'b130'a322'a120,
6393 0xd352'd150'c342'c140,
6394 0x5555'5555'5555'5555,
6395 0x9716'9514'8706'8504,
6396 0xb736'b534'a726'a524,
6397 0xd756'd554'c746'c544,
6398 0x5555'5555'5555'5555,
6399 0x9b1a'9918'8b0a'8908,
6400 0xbb3a'b938'ab2a'a928,
6401 0xdb5a'd958'cb4a'c948,
6402 0x5555'5555'5555'5555,
6403 0x9f1e'9d1c'8f0e'8d0c,
6404 0xbf3e'bd3c'af2e'ad2c,
6405 0xdf5e'dd5c'cf4e'cd4c});
6406 }
6407
TEST_F(Riscv64InterpreterTest,TestVssseg7e32)6408 TEST_F(Riscv64InterpreterTest, TestVssseg7e32) {
6409 TestVsssegXeXX<UInt32, 7, 1>(0xc820e427, // vssseg7e32.v v8, (x1), x2, v0.t
6410 32,
6411 {0x9312'9110'8302'8100,
6412 0xb332'b130'a322'a120,
6413 0xd352'd150'c342'c140,
6414 0x5555'5555'e362'e160,
6415 0x9716'9514'8706'8504,
6416 0xb736'b534'a726'a524,
6417 0xd756'd554'c746'c544,
6418 0x5555'5555'e766'e564,
6419 0x9b1a'9918'8b0a'8908,
6420 0xbb3a'b938'ab2a'a928,
6421 0xdb5a'd958'cb4a'c948,
6422 0x5555'5555'eb6a'e968,
6423 0x9f1e'9d1c'8f0e'8d0c,
6424 0xbf3e'bd3c'af2e'ad2c,
6425 0xdf5e'dd5c'cf4e'cd4c,
6426 0x5555'5555'ef6e'ed6c});
6427 }
6428
TEST_F(Riscv64InterpreterTest,TestVssseg8e32)6429 TEST_F(Riscv64InterpreterTest, TestVssseg8e32) {
6430 TestVsssegXeXX<UInt32, 8, 1>(0xe820e427, // vssseg8e32.v v8, (x1), x2, v0.t
6431 32,
6432 {0x9312'9110'8302'8100,
6433 0xb332'b130'a322'a120,
6434 0xd352'd150'c342'c140,
6435 0xf372'f170'e362'e160,
6436 0x9716'9514'8706'8504,
6437 0xb736'b534'a726'a524,
6438 0xd756'd554'c746'c544,
6439 0xf776'f574'e766'e564,
6440 0x9b1a'9918'8b0a'8908,
6441 0xbb3a'b938'ab2a'a928,
6442 0xdb5a'd958'cb4a'c948,
6443 0xfb7a'f978'eb6a'e968,
6444 0x9f1e'9d1c'8f0e'8d0c,
6445 0xbf3e'bd3c'af2e'ad2c,
6446 0xdf5e'dd5c'cf4e'cd4c,
6447 0xff7e'fd7c'ef6e'ed6c});
6448 }
6449
TEST_F(Riscv64InterpreterTest,TestVsse64_vlmul1)6450 TEST_F(Riscv64InterpreterTest, TestVsse64_vlmul1) {
6451 TestVsssegXeXX<UInt64, 1, 1>(0x820f427, // vsse64.v v8, (x1), x2, v0.t
6452 32,
6453 {0x8706'8504'8302'8100,
6454 0x5555'5555'5555'5555,
6455 0x5555'5555'5555'5555,
6456 0x5555'5555'5555'5555,
6457 0x8f0e'8d0c'8b0a'8908});
6458 }
6459
TEST_F(Riscv64InterpreterTest,TestVsse64_vlmul2)6460 TEST_F(Riscv64InterpreterTest, TestVsse64_vlmul2) {
6461 TestVsssegXeXX<UInt64, 1, 2>(0x820f427, // vsse64.v v8, (x1), x2, v0.t
6462 32,
6463 {0x8706'8504'8302'8100,
6464 0x5555'5555'5555'5555,
6465 0x5555'5555'5555'5555,
6466 0x5555'5555'5555'5555,
6467 0x8f0e'8d0c'8b0a'8908,
6468 0x5555'5555'5555'5555,
6469 0x5555'5555'5555'5555,
6470 0x5555'5555'5555'5555,
6471 0x9716'9514'9312'9110,
6472 0x5555'5555'5555'5555,
6473 0x5555'5555'5555'5555,
6474 0x5555'5555'5555'5555,
6475 0x9f1e'9d1c'9b1a'9918});
6476 }
6477
TEST_F(Riscv64InterpreterTest,TestVsse64_vlmul4)6478 TEST_F(Riscv64InterpreterTest, TestVsse64_vlmul4) {
6479 TestVsssegXeXX<UInt64, 1, 4>(
6480 0x820f427, // vsse64.v v8, (x1), x2, v0.t
6481 32,
6482 {0x8706'8504'8302'8100, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6483 0x8f0e'8d0c'8b0a'8908, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6484 0x9716'9514'9312'9110, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6485 0x9f1e'9d1c'9b1a'9918, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6486 0xa726'a524'a322'a120, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6487 0xaf2e'ad2c'ab2a'a928, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6488 0xb736'b534'b332'b130, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555, 0x5555'5555'5555'5555,
6489 0xbf3e'bd3c'bb3a'b938});
6490 }
6491
TEST_F(Riscv64InterpreterTest,TestVsse64_vlmul8)6492 TEST_F(Riscv64InterpreterTest, TestVsse64_vlmul8) {
6493 TestVsssegXeXX<UInt64, 1, 8>(
6494 0x820f427, // vsse64.v v8, (x1), x2, v0.t
6495 16,
6496 {0x8706'8504'8302'8100, 0x5555'5555'5555'5555, 0x8f0e'8d0c'8b0a'8908, 0x5555'5555'5555'5555,
6497 0x9716'9514'9312'9110, 0x5555'5555'5555'5555, 0x9f1e'9d1c'9b1a'9918, 0x5555'5555'5555'5555,
6498 0xa726'a524'a322'a120, 0x5555'5555'5555'5555, 0xaf2e'ad2c'ab2a'a928, 0x5555'5555'5555'5555,
6499 0xb736'b534'b332'b130, 0x5555'5555'5555'5555, 0xbf3e'bd3c'bb3a'b938, 0x5555'5555'5555'5555,
6500 0xc746'c544'c342'c140, 0x5555'5555'5555'5555, 0xcf4e'cd4c'cb4a'c948, 0x5555'5555'5555'5555,
6501 0xd756'd554'd352'd150, 0x5555'5555'5555'5555, 0xdf5e'dd5c'db5a'd958, 0x5555'5555'5555'5555,
6502 0xe766'e564'e362'e160, 0x5555'5555'5555'5555, 0xef6e'ed6c'eb6a'e968, 0x5555'5555'5555'5555,
6503 0xf776'f574'f372'f170, 0x5555'5555'5555'5555, 0xff7e'fd7c'fb7a'f978});
6504 }
6505
TEST_F(Riscv64InterpreterTest,TestVssseg2e64_vlmul1)6506 TEST_F(Riscv64InterpreterTest, TestVssseg2e64_vlmul1) {
6507 TestVsssegXeXX<UInt64, 2, 1>(0x2820f427, // vssseg2e64.v v8, (x1), x2, v0.t
6508 32,
6509 {0x8706'8504'8302'8100,
6510 0x9716'9514'9312'9110,
6511 0x5555'5555'5555'5555,
6512 0x5555'5555'5555'5555,
6513 0x8f0e'8d0c'8b0a'8908,
6514 0x9f1e'9d1c'9b1a'9918});
6515 }
6516
TEST_F(Riscv64InterpreterTest,TestVssseg2e64_vlmul2)6517 TEST_F(Riscv64InterpreterTest, TestVssseg2e64_vlmul2) {
6518 TestVsssegXeXX<UInt64, 2, 2>(0x2820f427, // vssseg2e64.v v8, (x1), x2, v0.t
6519 32,
6520 {0x8706'8504'8302'8100,
6521 0xa726'a524'a322'a120,
6522 0x5555'5555'5555'5555,
6523 0x5555'5555'5555'5555,
6524 0x8f0e'8d0c'8b0a'8908,
6525 0xaf2e'ad2c'ab2a'a928,
6526 0x5555'5555'5555'5555,
6527 0x5555'5555'5555'5555,
6528 0x9716'9514'9312'9110,
6529 0xb736'b534'b332'b130,
6530 0x5555'5555'5555'5555,
6531 0x5555'5555'5555'5555,
6532 0x9f1e'9d1c'9b1a'9918,
6533 0xbf3e'bd3c'bb3a'b938});
6534 }
6535
TEST_F(Riscv64InterpreterTest,TestVssseg2e64_vlmul4)6536 TEST_F(Riscv64InterpreterTest, TestVssseg2e64_vlmul4) {
6537 TestVsssegXeXX<UInt64, 2, 4>(0x2820f427, // vssseg2e64.v v8, (x1), x2, v0.t
6538 16,
6539 {0x8706'8504'8302'8100,
6540 0xc746'c544'c342'c140,
6541 0x8f0e'8d0c'8b0a'8908,
6542 0xcf4e'cd4c'cb4a'c948,
6543 0x9716'9514'9312'9110,
6544 0xd756'd554'd352'd150,
6545 0x9f1e'9d1c'9b1a'9918,
6546 0xdf5e'dd5c'db5a'd958,
6547 0xa726'a524'a322'a120,
6548 0xe766'e564'e362'e160,
6549 0xaf2e'ad2c'ab2a'a928,
6550 0xef6e'ed6c'eb6a'e968,
6551 0xb736'b534'b332'b130,
6552 0xf776'f574'f372'f170,
6553 0xbf3e'bd3c'bb3a'b938,
6554 0xff7e'fd7c'fb7a'f978});
6555 }
6556
TEST_F(Riscv64InterpreterTest,TestVssseg3e64_vlmul1)6557 TEST_F(Riscv64InterpreterTest, TestVssseg3e64_vlmul1) {
6558 TestVsssegXeXX<UInt64, 3, 1>(0x4820f427, // vssseg3e64.v v8, (x1), x2, v0.t
6559 32,
6560 {0x8706'8504'8302'8100,
6561 0x9716'9514'9312'9110,
6562 0xa726'a524'a322'a120,
6563 0x5555'5555'5555'5555,
6564 0x8f0e'8d0c'8b0a'8908,
6565 0x9f1e'9d1c'9b1a'9918,
6566 0xaf2e'ad2c'ab2a'a928});
6567 }
6568
TEST_F(Riscv64InterpreterTest,TestVssseg3e64_vlmul2)6569 TEST_F(Riscv64InterpreterTest, TestVssseg3e64_vlmul2) {
6570 TestVsssegXeXX<UInt64, 3, 2>(0x4820f427, // vssseg3e64.v v8, (x1), x2, v0.t
6571 32,
6572 {0x8706'8504'8302'8100,
6573 0xa726'a524'a322'a120,
6574 0xc746'c544'c342'c140,
6575 0x5555'5555'5555'5555,
6576 0x8f0e'8d0c'8b0a'8908,
6577 0xaf2e'ad2c'ab2a'a928,
6578 0xcf4e'cd4c'cb4a'c948,
6579 0x5555'5555'5555'5555,
6580 0x9716'9514'9312'9110,
6581 0xb736'b534'b332'b130,
6582 0xd756'd554'd352'd150,
6583 0x5555'5555'5555'5555,
6584 0x9f1e'9d1c'9b1a'9918,
6585 0xbf3e'bd3c'bb3a'b938,
6586 0xdf5e'dd5c'db5a'd958});
6587 }
6588
TEST_F(Riscv64InterpreterTest,TestVssseg4e64_vlmul1)6589 TEST_F(Riscv64InterpreterTest, TestVssseg4e64_vlmul1) {
6590 TestVsssegXeXX<UInt64, 4, 1>(0x6820f427, // vssseg4e64.v v8, (x1), x2, v0.t
6591 32,
6592 {0x8706'8504'8302'8100,
6593 0x9716'9514'9312'9110,
6594 0xa726'a524'a322'a120,
6595 0xb736'b534'b332'b130,
6596 0x8f0e'8d0c'8b0a'8908,
6597 0x9f1e'9d1c'9b1a'9918,
6598 0xaf2e'ad2c'ab2a'a928,
6599 0xbf3e'bd3c'bb3a'b938});
6600 }
6601
TEST_F(Riscv64InterpreterTest,TestVssseg4e64_vlmul2)6602 TEST_F(Riscv64InterpreterTest, TestVssseg4e64_vlmul2) {
6603 TestVsssegXeXX<UInt64, 4, 2>(0x6820f427, // vssseg4e64.v v8, (x1), x2, v0.t
6604 32,
6605 {0x8706'8504'8302'8100,
6606 0xa726'a524'a322'a120,
6607 0xc746'c544'c342'c140,
6608 0xe766'e564'e362'e160,
6609 0x8f0e'8d0c'8b0a'8908,
6610 0xaf2e'ad2c'ab2a'a928,
6611 0xcf4e'cd4c'cb4a'c948,
6612 0xef6e'ed6c'eb6a'e968,
6613 0x9716'9514'9312'9110,
6614 0xb736'b534'b332'b130,
6615 0xd756'd554'd352'd150,
6616 0xf776'f574'f372'f170,
6617 0x9f1e'9d1c'9b1a'9918,
6618 0xbf3e'bd3c'bb3a'b938,
6619 0xdf5e'dd5c'db5a'd958,
6620 0xff7e'fd7c'fb7a'f978});
6621 }
6622
TEST_F(Riscv64InterpreterTest,TestVssseg5e64)6623 TEST_F(Riscv64InterpreterTest, TestVssseg5e64) {
6624 TestVsssegXeXX<UInt64, 5, 1>(0x8820f427, // vssseg5e64.v v8, (x1), x2, v0.t
6625 64,
6626 {0x8706'8504'8302'8100,
6627 0x9716'9514'9312'9110,
6628 0xa726'a524'a322'a120,
6629 0xb736'b534'b332'b130,
6630 0xc746'c544'c342'c140,
6631 0x5555'5555'5555'5555,
6632 0x5555'5555'5555'5555,
6633 0x5555'5555'5555'5555,
6634 0x8f0e'8d0c'8b0a'8908,
6635 0x9f1e'9d1c'9b1a'9918,
6636 0xaf2e'ad2c'ab2a'a928,
6637 0xbf3e'bd3c'bb3a'b938,
6638 0xcf4e'cd4c'cb4a'c948});
6639 }
6640
TEST_F(Riscv64InterpreterTest,TestVssseg6e64)6641 TEST_F(Riscv64InterpreterTest, TestVssseg6e64) {
6642 TestVsssegXeXX<UInt64, 6, 1>(0xa820f427, // vssseg6e64.v v8, (x1), x2, v0.t
6643 64,
6644 {0x8706'8504'8302'8100,
6645 0x9716'9514'9312'9110,
6646 0xa726'a524'a322'a120,
6647 0xb736'b534'b332'b130,
6648 0xc746'c544'c342'c140,
6649 0xd756'd554'd352'd150,
6650 0x5555'5555'5555'5555,
6651 0x5555'5555'5555'5555,
6652 0x8f0e'8d0c'8b0a'8908,
6653 0x9f1e'9d1c'9b1a'9918,
6654 0xaf2e'ad2c'ab2a'a928,
6655 0xbf3e'bd3c'bb3a'b938,
6656 0xcf4e'cd4c'cb4a'c948,
6657 0xdf5e'dd5c'db5a'd958});
6658 }
6659
TEST_F(Riscv64InterpreterTest,TestVssseg7e64)6660 TEST_F(Riscv64InterpreterTest, TestVssseg7e64) {
6661 TestVsssegXeXX<UInt64, 7, 1>(0xc820f427, // vssseg7e64.v v8, (x1), x2, v0.t
6662 64,
6663 {0x8706'8504'8302'8100,
6664 0x9716'9514'9312'9110,
6665 0xa726'a524'a322'a120,
6666 0xb736'b534'b332'b130,
6667 0xc746'c544'c342'c140,
6668 0xd756'd554'd352'd150,
6669 0xe766'e564'e362'e160,
6670 0x5555'5555'5555'5555,
6671 0x8f0e'8d0c'8b0a'8908,
6672 0x9f1e'9d1c'9b1a'9918,
6673 0xaf2e'ad2c'ab2a'a928,
6674 0xbf3e'bd3c'bb3a'b938,
6675 0xcf4e'cd4c'cb4a'c948,
6676 0xdf5e'dd5c'db5a'd958,
6677 0xef6e'ed6c'eb6a'e968});
6678 }
6679
TEST_F(Riscv64InterpreterTest,TestVssseg8e64)6680 TEST_F(Riscv64InterpreterTest, TestVssseg8e64) {
6681 TestVsssegXeXX<UInt64, 8, 1>(0xe820f427, // vssseg8e64.v v8, (x1), x2, v0.t
6682 64,
6683 {0x8706'8504'8302'8100,
6684 0x9716'9514'9312'9110,
6685 0xa726'a524'a322'a120,
6686 0xb736'b534'b332'b130,
6687 0xc746'c544'c342'c140,
6688 0xd756'd554'd352'd150,
6689 0xe766'e564'e362'e160,
6690 0xf776'f574'f372'f170,
6691 0x8f0e'8d0c'8b0a'8908,
6692 0x9f1e'9d1c'9b1a'9918,
6693 0xaf2e'ad2c'ab2a'a928,
6694 0xbf3e'bd3c'bb3a'b938,
6695 0xcf4e'cd4c'cb4a'c948,
6696 0xdf5e'dd5c'db5a'd958,
6697 0xef6e'ed6c'eb6a'e968,
6698 0xff7e'fd7c'fb7a'f978});
6699 }
6700
TEST_F(Riscv64InterpreterTest,TestVsm)6701 TEST_F(Riscv64InterpreterTest, TestVsm) {
6702 TestVsm(0x2b08427, // vsm.v v8, (x1)
6703 {0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143});
6704 }
6705
TEST_F(Riscv64InterpreterTest,TestVectorMaskInstructions)6706 TEST_F(Riscv64InterpreterTest, TestVectorMaskInstructions) {
6707 TestVectorMaskInstruction(128,
6708 intrinsics::InactiveProcessing::kAgnostic,
6709 0x630c2457, // vmandn.mm v8, v16, v24
6710 {0x8102'8504'8102'8100, 0x8102'8504'890a'8908});
6711 TestVectorMaskInstruction(128,
6712 intrinsics::InactiveProcessing::kAgnostic,
6713 0x670c2457, // vmand.mm v8, v16, v24
6714 {0x0604'0000'0200'0000, 0x0e0c'0808'0200'0000});
6715 TestVectorMaskInstruction(128,
6716 intrinsics::InactiveProcessing::kAgnostic,
6717 0x6b0c2457, // vmor.mm v8, v16, v24
6718 {0x8f0e'8f0d'8706'8300, 0x9f1e'9f1c'9f1e'9b19});
6719 TestVectorMaskInstruction(128,
6720 intrinsics::InactiveProcessing::kAgnostic,
6721 0x6f0c2457, // vmxor.mm v8, v16, v24
6722 {0x890a'8f0d'8506'8300, 0x9112'9714'9d1e'9b19});
6723 TestVectorMaskInstruction(128,
6724 intrinsics::InactiveProcessing::kAgnostic,
6725 0x730c2457, // vmorn.mm v8, v16, v24
6726 {0xf7f7'f5f6'fbfb'fdff, 0xefef'edef'ebeb'edee});
6727 TestVectorMaskInstruction(128,
6728 intrinsics::InactiveProcessing::kAgnostic,
6729 0x770c2457, // vmnand.mm v8, v16, v24
6730 {0xf9fb'ffff'fdff'ffff, 0xf1f3'f7f7'fdff'ffff});
6731 TestVectorMaskInstruction(128,
6732 intrinsics::InactiveProcessing::kAgnostic,
6733 0x7b0c2457, // vmnor.mm v8, v16, v24
6734 {0x70f1'70f2'78f9'7cff, 0x60e1'60e3'60e1'64e6});
6735 TestVectorMaskInstruction(128,
6736 intrinsics::InactiveProcessing::kAgnostic,
6737 0x7f0c2457, // vmxnor.mm v8, v16, v24
6738 {0x76f5'70f2'7af9'7cff, 0x6eed'68eb'62e1'64e6});
6739 TestVectorMaskInstruction(0,
6740 intrinsics::InactiveProcessing::kAgnostic,
6741 0x5300a457, // vmsbf.m v8, v16
6742 {0x0000'0000'0000'00ff, 0x0000'0000'0000'0000});
6743 TestVectorMaskInstruction(0,
6744 intrinsics::InactiveProcessing::kAgnostic,
6745 0x53012457, // vmsof.m v8, v16
6746 {0x0000'0000'0000'0100, 0x0000'0000'0000'0000});
6747 TestVectorMaskInstruction(0,
6748 intrinsics::InactiveProcessing::kAgnostic,
6749 0x5301a457, // vmsif.m v8, v16
6750 {0x0000'0000'0000'01ff, 0x0000'0000'0000'0000});
6751 TestVectorMaskInstruction(0,
6752 intrinsics::InactiveProcessing::kAgnostic,
6753 0x5100a457, // vmsbf.m v8, v16, v0.t
6754 {0xd5ad'd6b5'adff'ffff, 0x6af7'57bb'deed'7bb5});
6755 TestVectorMaskInstruction(0,
6756 intrinsics::InactiveProcessing::kAgnostic,
6757 0x51012457, // vmsof.m v8, v16, v0.t
6758 {0xd5ad'd6b5'af6b'b5ad, 0x6af7'57bb'deed'7bb5});
6759 TestVectorMaskInstruction(0,
6760 intrinsics::InactiveProcessing::kAgnostic,
6761 0x5101a457, // vmsif.m v8, v16, v0.t
6762 {0xd5ad'd6b5'afff'ffff, 0x6af7'57bb'deed'7bb5});
6763 TestVectorMaskInstruction(0,
6764 intrinsics::InactiveProcessing::kUndisturbed,
6765 0x5100a457, // vmsbf.m v8, v16, v0.t
6766 {0x5505'5415'05d5'5f57, 0x4055'5511'5445'5115});
6767 TestVectorMaskInstruction(0,
6768 intrinsics::InactiveProcessing::kUndisturbed,
6769 0x51012457, // vmsof.m v8, v16, v0.t
6770 {0x5505'5415'0741'1505, 0x4055'5511'5445'5115});
6771 TestVectorMaskInstruction(0,
6772 intrinsics::InactiveProcessing::kUndisturbed,
6773 0x5101a457, // vmsif.m v8, v16, v0.t
6774 {0x5505'5415'07d5'5f57, 0x4055'5511'5445'5115});
6775 }
6776
TEST_F(Riscv64InterpreterTest,TestVmseq)6777 TEST_F(Riscv64InterpreterTest, TestVmseq) {
6778 TestVectorMaskTargetInstruction(0x610c0457, // Vmseq.vv v8, v16, v24, v0.t
6779 {255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
6780 0x0000'0000'0000'00ff,
6781 0x0000'000f,
6782 0x0003,
6783 kVectorComparisonSource);
6784 TestVectorMaskTargetInstruction(0x6100c457, // Vmseq.vx v8, v16, x1, v0.t
6785 {0, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0},
6786 0x0000'0000'0f00'0000,
6787 0x0000'3000,
6788 0x0040,
6789 kVectorComparisonSource);
6790 TestVectorMaskTargetInstruction(0x610ab457, // Vmseq.vi v8, v16, -0xb, v0.t
6791 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 85, 0, 0, 0, 0},
6792 0x0000'f000'0000'0000,
6793 0x0000'0000,
6794 0x0000,
6795 kVectorComparisonSource);
6796 }
6797
TEST_F(Riscv64InterpreterTest,TestVmfne)6798 TEST_F(Riscv64InterpreterTest, TestVmfne) {
6799 TestVectorMaskTargetInstruction(0x710c1457, // Vmfne.vv v8, v16, v24, v0.t
6800 0xffff'fff8,
6801 0xfffe,
6802 kVectorComparisonSource);
6803 TestVectorMaskTargetInstruction(0x7100d457, // Vmfne.vf v8, v16, f1, v0.t
6804 0xffff'ffbf,
6805 0xffdf,
6806 kVectorComparisonSource);
6807 }
6808
TEST_F(Riscv64InterpreterTest,TestVmsne)6809 TEST_F(Riscv64InterpreterTest, TestVmsne) {
6810 TestVectorMaskTargetInstruction(
6811 0x650c0457, // Vmsne.vv v8, v16, v24, v0.t
6812 {0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255},
6813 0xffff'ffff'ffff'ff00,
6814 0xffff'fff0,
6815 0xfffc,
6816 kVectorComparisonSource);
6817 TestVectorMaskTargetInstruction(
6818 0x6500c457, // Vmsne.vx v8, v16, x1, v0.t
6819 {255, 255, 255, 255, 255, 255, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255},
6820 0xffff'ffff'f0ff'ffff,
6821 0xffff'cfff,
6822 0xffbf,
6823 kVectorComparisonSource);
6824 TestVectorMaskTargetInstruction(
6825 0x650ab457, // Vmsne.vi v8, v16, -0xb, v0.t
6826 {255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 170, 255, 255, 255, 255},
6827 0xffff'0fff'ffff'ffff,
6828 0xffff'ffff,
6829 0xffff,
6830 kVectorComparisonSource);
6831 }
6832
TEST_F(Riscv64InterpreterTest,TestVmflt)6833 TEST_F(Riscv64InterpreterTest, TestVmflt) {
6834 TestVectorMaskTargetInstruction(0x6d0c1457, // Vmflt.vv v8, v16, v24, v0.t
6835 0x0000'f000,
6836 0x00c0,
6837 kVectorComparisonSource);
6838 TestVectorMaskTargetInstruction(0x6d00d457, // Vmflt.vf v8, v16, f1, v0.t
6839 0xff00'ff07,
6840 0xf0d1,
6841 kVectorComparisonSource);
6842 }
6843
TEST_F(Riscv64InterpreterTest,TestVmsltu)6844 TEST_F(Riscv64InterpreterTest, TestVmsltu) {
6845 TestVectorMaskTargetInstruction(0x690c0457, // Vmsltu.vv v8, v16, v24, v0.t
6846 {0, 0, 0, 3, 255, 255, 0, 255, 0, 0, 0, 0, 255, 255, 255, 255},
6847 0xffff'0000'f0ff'1000,
6848 0xff00'cf00,
6849 0xf0b0,
6850 kVectorComparisonSource);
6851 TestVectorMaskTargetInstruction(
6852 0x6900c457, // Vmsltu.vx v8, v16, x1, v0.t
6853 {85, 15, 10, 11, 255, 255, 0, 255, 0, 0, 0, 0, 136, 136, 255, 255},
6854 0xffaa'0000'f0ff'3330,
6855 0xff00'cf54,
6856 0xf0b0,
6857 kVectorComparisonSource);
6858 }
6859
TEST_F(Riscv64InterpreterTest,TestVmslt)6860 TEST_F(Riscv64InterpreterTest, TestVmslt) {
6861 TestVectorMaskTargetInstruction(0x6d0c0457, // Vmslt.vv v8, v16, v24, v0.t
6862 {0, 0, 245, 247, 0, 32, 255, 255, 0, 0, 0, 0, 255, 255, 255, 255},
6863 0xffff'0000'ff40'dc00,
6864 0xff00'f0a0,
6865 0xf0cc,
6866 kVectorComparisonSource);
6867 TestVectorMaskTargetInstruction(0x6d00c457, // Vmslt.vx v8, v16, x1, v0.t
6868 {0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 136, 136, 255, 255},
6869 0xffaa'0000'0040'0000,
6870 0xff00'0000,
6871 0xf000,
6872 kVectorComparisonSource);
6873 }
6874
TEST_F(Riscv64InterpreterTest,TestVmfle)6875 TEST_F(Riscv64InterpreterTest, TestVmfle) {
6876 TestVectorMaskTargetInstruction(0x650c1457, // Vmfle.vv v8, v16, v24, v0.t
6877 0x0000'f007,
6878 0x00c1,
6879 kVectorComparisonSource);
6880 TestVectorMaskTargetInstruction(0x6500d457, // Vmfle.vf v8, v16, f1, v0.t
6881 0xff00'ff47,
6882 0xf0f1,
6883 kVectorComparisonSource);
6884 }
6885
TEST_F(Riscv64InterpreterTest,TestVmsleu)6886 TEST_F(Riscv64InterpreterTest, TestVmsleu) {
6887 TestVectorMaskTargetInstruction(
6888 0x710c0457, // Vmsleu.vv v8, v16, v24, v0.t
6889 {255, 255, 0, 3, 255, 255, 0, 255, 0, 0, 0, 0, 255, 255, 255, 255},
6890 0xffff'0000'f0ff'10ff,
6891 0xff00'cf0f,
6892 0xf0b3,
6893 kVectorComparisonSource);
6894 TestVectorMaskTargetInstruction(
6895 0x7100c457, // Vmsleu.vx v8, v16, x1, v0.t
6896 {85, 15, 10, 11, 255, 255, 255, 255, 0, 0, 0, 0, 136, 136, 255, 255},
6897 0xffaa'0000'ffff'3330,
6898 0xff00'ff54,
6899 0xf0f0,
6900 kVectorComparisonSource);
6901 TestVectorMaskTargetInstruction(
6902 0x710ab457, // Vmsleu.vi v8, v16, -0xb, v0.t
6903 {255, 15, 15, 15, 255, 255, 255, 255, 85, 0, 5, 85, 255, 255, 255, 255},
6904 0xffff'f30f'ffff'333f,
6905 0xffff'ff57,
6906 0xffff,
6907 kVectorComparisonSource);
6908 }
6909
TEST_F(Riscv64InterpreterTest,TestVmsle)6910 TEST_F(Riscv64InterpreterTest, TestVmsle) {
6911 TestVectorMaskTargetInstruction(
6912 0x750c0457, // Vmsle.vv v8, v16, v24, v0.t
6913 {255, 255, 245, 247, 0, 32, 255, 255, 0, 0, 0, 0, 255, 255, 255, 255},
6914 0xffff'0000'ff40'dcff,
6915 0xff00'f0af,
6916 0xf0cf,
6917 kVectorComparisonSource);
6918 TestVectorMaskTargetInstruction(0x7500c457, // Vmsle.vx v8, v16, x1, v0.t
6919 {0, 0, 0, 0, 0, 32, 255, 0, 0, 0, 0, 0, 136, 136, 255, 255},
6920 0xffaa'0000'0f40'0000,
6921 0xff00'3000,
6922 0xf040,
6923 kVectorComparisonSource);
6924 TestVectorMaskTargetInstruction(0x750ab457, // Vmsle.vi v8, v16, -0xb
6925 {170, 0, 5, 4, 0, 32, 255, 0, 85, 0, 5, 85, 255, 255, 255, 255},
6926 0xffff'f30f'0f40'000f,
6927 0xffff'3003,
6928 0xff4f,
6929 kVectorComparisonSource);
6930 }
6931
TEST_F(Riscv64InterpreterTest,TestVmfgt)6932 TEST_F(Riscv64InterpreterTest, TestVmfgt) {
6933 TestVectorMaskTargetInstruction(0x7500d457, // Vmfgt.vf v8, v16, f1, v0.t
6934 0x0000'0010,
6935 0x0000,
6936 kVectorComparisonSource);
6937 }
6938
TEST_F(Riscv64InterpreterTest,TestVmsgtu)6939 TEST_F(Riscv64InterpreterTest, TestVmsgtu) {
6940 TestVectorMaskTargetInstruction(
6941 0x7900c457, // Vmsgtu.vx v8, v16, x1, v0.t
6942 {170, 240, 245, 244, 0, 0, 0, 0, 255, 255, 255, 255, 119, 119, 0, 0},
6943 0x0055'ffff'0000'cccf,
6944 0x00ff'00ab,
6945 0x0f0f,
6946 kVectorComparisonSource);
6947 TestVectorMaskTargetInstruction(0x790ab457, // Vmsgtu.vi v8, v16, -0xb, v0.t
6948 {0, 240, 240, 240, 0, 0, 0, 0, 170, 255, 250, 170, 0, 0, 0, 0},
6949 0x0000'0cf0'0000'ccc0,
6950 0x0000'00a8,
6951 0x0000,
6952 kVectorComparisonSource);
6953 }
6954
TEST_F(Riscv64InterpreterTest,TestVmsgt)6955 TEST_F(Riscv64InterpreterTest, TestVmsgt) {
6956 TestVectorMaskTargetInstruction(
6957 0x7d00c457, // Vmsgt.vx v8, v16, x1, v0.t
6958 {255, 255, 255, 255, 255, 223, 0, 255, 255, 255, 255, 255, 119, 119, 0, 0},
6959 0x0055'ffff'f0bf'ffff,
6960 0x00ff'cfff,
6961 0x0fbf,
6962 kVectorComparisonSource);
6963 TestVectorMaskTargetInstruction(
6964 0x7d0ab457, // Vmsgt.vi v8, v16, -0xb, v0.t
6965 {85, 255, 250, 251, 255, 223, 0, 255, 170, 255, 250, 170, 0, 0, 0, 0},
6966 0x0000'0cf0'f0bf'fff0,
6967 0x0000'cffc,
6968 0x00b0,
6969 kVectorComparisonSource);
6970 }
6971
TEST_F(Riscv64InterpreterTest,TestVmfge)6972 TEST_F(Riscv64InterpreterTest, TestVmfge) {
6973 TestVectorMaskTargetInstruction(0x7d00d457, // Vmfge.vf v8, v16, f1, v0.t
6974 0x0000'0050,
6975 0x0020,
6976 kVectorComparisonSource);
6977 }
6978
TEST_F(Riscv64InterpreterTest,TestVfmacc)6979 TEST_F(Riscv64InterpreterTest, TestVfmacc) {
6980 TestVectorFloatInstruction(0xb1881457, // vfmacc.vv v8, v16, v24, v0.t
6981 {{0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6982 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6983 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6984 {0x6a1f'cefd, 0x7629'21c4, 0x6232'9db4, 0x6e3c'70f9},
6985 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
6986 {0x5555'5551, 0xd66b'bbc8, 0x5555'5555, 0x5555'5037},
6987 {0xfaad'fde4, 0xff80'0000, 0xf2c2'c69a, 0xfecd'99e3},
6988 {0xff80'0000, 0xff80'0000, 0xff80'0000, 0xff80'0000}},
6989 {{0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6990 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6991 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6992 {0x75b4'9040'f9f1'ea75, 0x6dcb'c6d1'12f0'a99b},
6993 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
6994 {0xd614'2330'4af7'4c90, 0x5555'5555'5555'5555},
6995 {0xfff0'0000'0000'0000, 0xfe5b'5815'60f1'ac51},
6996 {0xfff0'0000'0000'0000, 0xfff0'0000'0000'0000}},
6997 kVectorCalculationsSource);
6998 TestVectorFloatInstruction(0xb100d457, // vfmacc.vf v8, f1, v16, v0.t
6999 {{0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7000 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7001 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7002 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7003 {0x5555'5555, 0x5555'5555, 0x5555'550e, 0x5555'0ca1},
7004 {0x550b'37bf, 0xd895'6354, 0xdc99'df27, 0xe09c'b3a3},
7005 {0xe49f'8677, 0xe8a2'594a, 0xeca5'2c1d, 0xf0a7'fef0},
7006 {0xf4aa'd1c3, 0xf8ad'a496, 0xfcb0'7768, 0xff80'0000}},
7007 {{0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7008 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7009 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7010 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7011 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7012 {0xd780'0dff'a493'9082, 0xdf85'b3a5'4a3b'e0d2},
7013 {0xe790'194a'efe1'8677, 0xef95'bef0'9587'2c1d},
7014 {0xf7a0'2496'3b2c'd1c3, 0xffa5'ca3b'e0d2'7768}},
7015 kVectorCalculationsSource);
7016 }
7017
TEST_F(Riscv64InterpreterTest,TestVfnmacc)7018 TEST_F(Riscv64InterpreterTest, TestVfnmacc) {
7019 TestVectorFloatInstruction(0xb5881457, // vfnmacc.vv v8, v16, v24, v0.t
7020 {{0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7021 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7022 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7023 {0xea1f'cefd, 0xf629'21c4, 0xe232'9db4, 0xee3c'70f9},
7024 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7025 {0xd555'5551, 0x566b'bbc8, 0xd555'5555, 0xd555'5037},
7026 {0x7aad'fde4, 0x7f80'0000, 0x72c2'c69a, 0x7ecd'99e3},
7027 {0x7f80'0000, 0x7f80'0000, 0x7f80'0000, 0x7f80'0000}},
7028 {{0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7029 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7030 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7031 {0xf5b4'9040'f9f1'ea75, 0xedcb'c6d1'12f0'a99b},
7032 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7033 {0x5614'2330'4af7'4c90, 0xd555'5555'5555'5555},
7034 {0x7ff0'0000'0000'0000, 0x7e5b'5815'60f1'ac51},
7035 {0x7ff0'0000'0000'0000, 0x7ff0'0000'0000'0000}},
7036 kVectorCalculationsSource);
7037 TestVectorFloatInstruction(0xb500d457, // vfnmacc.vf v8, f1, v16, v0.t
7038 {{0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7039 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7040 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7041 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7042 {0xd555'5555, 0xd555'5555, 0xd555'550e, 0xd555'0ca1},
7043 {0xd50b'37bf, 0x5895'6354, 0x5c99'df27, 0x609c'b3a3},
7044 {0x649f'8677, 0x68a2'594a, 0x6ca5'2c1d, 0x70a7'fef0},
7045 {0x74aa'd1c3, 0x78ad'a496, 0x7cb0'7768, 0x7f80'0000}},
7046 {{0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7047 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7048 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7049 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7050 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7051 {0x5780'0dff'a493'9082, 0x5f85'b3a5'4a3b'e0d2},
7052 {0x6790'194a'efe1'8677, 0x6f95'bef0'9587'2c1d},
7053 {0x77a0'2496'3b2c'd1c3, 0x7fa5'ca3b'e0d2'7768}},
7054 kVectorCalculationsSource);
7055 }
7056
TEST_F(Riscv64InterpreterTest,TestVfwmacc)7057 TEST_F(Riscv64InterpreterTest, TestVfwmacc) {
7058 __m128i dst_result = {0x0000'0000'0000'0000, 0x0000'0000'0000'0000};
7059 TestWideningVectorFloatInstruction(0xf1881457, // vfwmacc.vv v8, v16, v24, v0.t
7060 {{0x3330'e53c'6480'0000, 0x34b2'786b'bbc5'4900},
7061 {0x3234'1766'da4a'6200, 0x33b5'cab6'2d6c'4800},
7062 {0x3937'92ba'5bd0'8000, 0x3ab9'666a'779a'0d00},
7063 {0x383b'4565'd61f'6600, 0x39bd'3935'e5bd'8800},
7064 {0x3f3f'423b'5522'0000, 0x40c0'ab36'1ab7'e880},
7065 {0x3e41'bab3'e9fa'b500, 0x3fc2'd4dc'5007'e400},
7066 {0x4543'f9df'a83a'4000, 0x46c5'2438'7aa3'4a80},
7067 {0x4446'53b6'69e6'3700, 0x45c7'8e1f'2e31'8400}},
7068 kVectorCalculationsSource,
7069 dst_result);
7070 TestWideningVectorFloatInstruction(0xf100d457, // vfwmacc.vf v8, f1, v16, v0.t
7071 {{0xb886'f0ad'0000'0000, 0xb907'a561'b400'0000},
7072 {0xb988'5a16'6800'0000, 0xba09'0ecb'1c00'0000},
7073 {0xba89'c37f'd000'0000, 0xbb0a'7834'8400'0000},
7074 {0xbb8b'2ce9'3800'0000, 0xbc0b'e19d'ec00'0000},
7075 {0xbc8c'9652'a000'0000, 0xbd0d'4b07'5400'0000},
7076 {0xbd8d'ffbc'0800'0000, 0xbe0e'b470'bc00'0000},
7077 {0xbe8f'6925'7000'0000, 0xbf10'0eed'1200'0000},
7078 {0xbf90'6947'6c00'0000, 0xc010'c3a1'c600'0000}},
7079 kVectorCalculationsSource,
7080 dst_result);
7081
7082 dst_result = {0x401c'6666'6666'6666, 0x401c'6666'6666'6666};
7083 TestWideningVectorFloatInstruction(0xf1881457, // vfwmacc.vv v8, v16, v24, v0.t
7084 {{0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7085 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7086 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7087 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7088 {0x401c'66e3'6f53'baee, 0x40c0'aec2'e784'b54d},
7089 {0x401c'6666'66f4'3c05, 0x401c'fd0d'48e6'a586},
7090 {0x4543'f9df'a83a'4000, 0x46c5'2438'7aa3'4a80},
7091 {0x4446'53b6'69e6'3700, 0x45c7'8e1f'2e31'8400}},
7092 kVectorCalculationsSource,
7093 dst_result);
7094 TestWideningVectorFloatInstruction(0xf100d457, // vfwmacc.vf v8, f1, v16, v0.t
7095 {{0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7096 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7097 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7098 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7099 {0x401c'6666'6666'6666, 0x401c'6666'6666'6657},
7100 {0x401c'6666'6666'5766, 0x401c'6666'6657'0c2e},
7101 {0x401c'6666'56b1'd3ae, 0x401c'6656'5779'5466},
7102 {0x401c'55fd'1efa'6666, 0x4007'4589'40cc'cccc}},
7103 kVectorCalculationsSource,
7104 dst_result);
7105 }
7106
TEST_F(Riscv64InterpreterTest,TestVfwnmacc)7107 TEST_F(Riscv64InterpreterTest, TestVfwnmacc) {
7108 __m128i dst_result = {0x0000'0000'0000'0000, 0x0000'0000'0000'0000};
7109 TestWideningVectorFloatInstruction(0xf5881457, // vfwnmacc.vv v8, v16, v24, v0.t
7110 {{0xb330'e53c'6480'0000, 0xb4b2'786b'bbc5'4900},
7111 {0xb234'1766'da4a'6200, 0xb3b5'cab6'2d6c'4800},
7112 {0xb937'92ba'5bd0'8000, 0xbab9'666a'779a'0d00},
7113 {0xb83b'4565'd61f'6600, 0xb9bd'3935'e5bd'8800},
7114 {0xbf3f'423b'5522'0000, 0xc0c0'ab36'1ab7'e880},
7115 {0xbe41'bab3'e9fa'b500, 0xbfc2'd4dc'5007'e400},
7116 {0xc543'f9df'a83a'4000, 0xc6c5'2438'7aa3'4a80},
7117 {0xc446'53b6'69e6'3700, 0xc5c7'8e1f'2e31'8400}},
7118 kVectorCalculationsSource,
7119 dst_result);
7120 TestWideningVectorFloatInstruction(0xf500d457, // vfwnmacc.vf v8, f1, v16, v0.t
7121 {{0x3886'f0ad'0000'0000, 0x3907'a561'b400'0000},
7122 {0x3988'5a16'6800'0000, 0x3a09'0ecb'1c00'0000},
7123 {0x3a89'c37f'd000'0000, 0x3b0a'7834'8400'0000},
7124 {0x3b8b'2ce9'3800'0000, 0x3c0b'e19d'ec00'0000},
7125 {0x3c8c'9652'a000'0000, 0x3d0d'4b07'5400'0000},
7126 {0x3d8d'ffbc'0800'0000, 0x3e0e'b470'bc00'0000},
7127 {0x3e8f'6925'7000'0000, 0x3f10'0eed'1200'0000},
7128 {0x3f90'6947'6c00'0000, 0x4010'c3a1'c600'0000}},
7129 kVectorCalculationsSource,
7130 dst_result);
7131
7132 dst_result = {0x401c'6666'6666'6666, 0x401c'6666'6666'6666};
7133 TestWideningVectorFloatInstruction(0xf5881457, // vfwnmacc.vv v8, v16, v24, v0.t
7134 {{0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7135 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7136 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7137 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7138 {0xc01c'66e3'6f53'baee, 0xc0c0'aec2'e784'b54d},
7139 {0xc01c'6666'66f4'3c05, 0xc01c'fd0d'48e6'a586},
7140 {0xc543'f9df'a83a'4000, 0xc6c5'2438'7aa3'4a80},
7141 {0xc446'53b6'69e6'3700, 0xc5c7'8e1f'2e31'8400}},
7142 kVectorCalculationsSource,
7143 dst_result);
7144 TestWideningVectorFloatInstruction(0xf500d457, // vfwnmacc.vf v8, f1, v16, v0.t
7145 {{0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7146 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7147 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7148 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7149 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6657},
7150 {0xc01c'6666'6666'5766, 0xc01c'6666'6657'0c2e},
7151 {0xc01c'6666'56b1'd3ae, 0xc01c'6656'5779'5466},
7152 {0xc01c'55fd'1efa'6666, 0xc007'4589'40cc'cccc}},
7153 kVectorCalculationsSource,
7154 dst_result);
7155 }
7156
TEST_F(Riscv64InterpreterTest,TestVfwmsac)7157 TEST_F(Riscv64InterpreterTest, TestVfwmsac) {
7158 __m128i dst_result = {0x0000'0000'0000'0000, 0x0000'0000'0000'0000};
7159 TestWideningVectorFloatInstruction(0xf9881457, // vfwmsac.vv v8, v16, v24, v0.t
7160 {{0x3330'e53c'6480'0000, 0x34b2'786b'bbc5'4900},
7161 {0x3234'1766'da4a'6200, 0x33b5'cab6'2d6c'4800},
7162 {0x3937'92ba'5bd0'8000, 0x3ab9'666a'779a'0d00},
7163 {0x383b'4565'd61f'6600, 0x39bd'3935'e5bd'8800},
7164 {0x3f3f'423b'5522'0000, 0x40c0'ab36'1ab7'e880},
7165 {0x3e41'bab3'e9fa'b500, 0x3fc2'd4dc'5007'e400},
7166 {0x4543'f9df'a83a'4000, 0x46c5'2438'7aa3'4a80},
7167 {0x4446'53b6'69e6'3700, 0x45c7'8e1f'2e31'8400}},
7168 kVectorCalculationsSource,
7169 dst_result);
7170 TestWideningVectorFloatInstruction(0xf900d457, // vfwmsac.vf v8, f1, v16, v0.t
7171 {{0xb886'f0ad'0000'0000, 0xb907'a561'b400'0000},
7172 {0xb988'5a16'6800'0000, 0xba09'0ecb'1c00'0000},
7173 {0xba89'c37f'd000'0000, 0xbb0a'7834'8400'0000},
7174 {0xbb8b'2ce9'3800'0000, 0xbc0b'e19d'ec00'0000},
7175 {0xbc8c'9652'a000'0000, 0xbd0d'4b07'5400'0000},
7176 {0xbd8d'ffbc'0800'0000, 0xbe0e'b470'bc00'0000},
7177 {0xbe8f'6925'7000'0000, 0xbf10'0eed'1200'0000},
7178 {0xbf90'6947'6c00'0000, 0xc010'c3a1'c600'0000}},
7179 kVectorCalculationsSource,
7180 dst_result);
7181
7182 dst_result = {0x401c'6666'6666'6666, 0x401c'6666'6666'6666};
7183 TestWideningVectorFloatInstruction(0xf9881457, // vfwmsac.vv v8, v16, v24, v0.t
7184 {{0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7185 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7186 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7187 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7188 {0xc01c'65e9'5d79'11de, 0x40c0'a7a9'4deb'1bb3},
7189 {0xc01c'6666'65d8'90c7, 0xc01b'cfbf'83e6'2746},
7190 {0x4543'f9df'a83a'4000, 0x46c5'2438'7aa3'4a80},
7191 {0x4446'53b6'69e6'3700, 0x45c7'8e1f'2e31'8400}},
7192 kVectorCalculationsSource,
7193 dst_result);
7194 TestWideningVectorFloatInstruction(0xf900d457, // vfwmsac.vf v8, f1, v16, v0.t
7195 {{0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7196 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7197 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7198 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6666},
7199 {0xc01c'6666'6666'6666, 0xc01c'6666'6666'6675},
7200 {0xc01c'6666'6666'7566, 0xc01c'6666'6675'c09e},
7201 {0xc01c'6666'761a'f91e, 0xc01c'6676'7553'7866},
7202 {0xc01c'76cf'add2'6666, 0xc026'9504'1633'3333}},
7203 kVectorCalculationsSource,
7204 dst_result);
7205 }
7206
TEST_F(Riscv64InterpreterTest,TestVfwnmsac)7207 TEST_F(Riscv64InterpreterTest, TestVfwnmsac) {
7208 __m128i dst_result = {0x0000'0000'0000'0000, 0x0000'0000'0000'0000};
7209 TestWideningVectorFloatInstruction(0xfd881457, // vfwnmsac.vv v8, v16, v24, v0.t
7210 {{0xb330'e53c'6480'0000, 0xb4b2'786b'bbc5'4900},
7211 {0xb234'1766'da4a'6200, 0xb3b5'cab6'2d6c'4800},
7212 {0xb937'92ba'5bd0'8000, 0xbab9'666a'779a'0d00},
7213 {0xb83b'4565'd61f'6600, 0xb9bd'3935'e5bd'8800},
7214 {0xbf3f'423b'5522'0000, 0xc0c0'ab36'1ab7'e880},
7215 {0xbe41'bab3'e9fa'b500, 0xbfc2'd4dc'5007'e400},
7216 {0xc543'f9df'a83a'4000, 0xc6c5'2438'7aa3'4a80},
7217 {0xc446'53b6'69e6'3700, 0xc5c7'8e1f'2e31'8400}},
7218 kVectorCalculationsSource,
7219 dst_result);
7220 TestWideningVectorFloatInstruction(0xfd00d457, // vfwnmsac.vf v8, f1, v16, v0.t
7221 {{0x3886'f0ad'0000'0000, 0x3907'a561'b400'0000},
7222 {0x3988'5a16'6800'0000, 0x3a09'0ecb'1c00'0000},
7223 {0x3a89'c37f'd000'0000, 0x3b0a'7834'8400'0000},
7224 {0x3b8b'2ce9'3800'0000, 0x3c0b'e19d'ec00'0000},
7225 {0x3c8c'9652'a000'0000, 0x3d0d'4b07'5400'0000},
7226 {0x3d8d'ffbc'0800'0000, 0x3e0e'b470'bc00'0000},
7227 {0x3e8f'6925'7000'0000, 0x3f10'0eed'1200'0000},
7228 {0x3f90'6947'6c00'0000, 0x4010'c3a1'c600'0000}},
7229 kVectorCalculationsSource,
7230 dst_result);
7231
7232 dst_result = {0x401c'6666'6666'6666, 0x401c'6666'6666'6666};
7233 TestWideningVectorFloatInstruction(0xfd881457, // vfwnmsac.vv v8, v16, v24, v0.t
7234 {{0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7235 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7236 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7237 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7238 {0x401c'65e9'5d79'11de, 0xc0c0'a7a9'4deb'1bb3},
7239 {0x401c'6666'65d8'90c7, 0x401b'cfbf'83e6'2746},
7240 {0xc543'f9df'a83a'4000, 0xc6c5'2438'7aa3'4a80},
7241 {0xc446'53b6'69e6'3700, 0xc5c7'8e1f'2e31'8400}},
7242 kVectorCalculationsSource,
7243 dst_result);
7244 TestWideningVectorFloatInstruction(0xfd00d457, // vfwnmsac.vf v8, f1, v16, v0.t
7245 {{0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7246 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7247 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7248 {0x401c'6666'6666'6666, 0x401c'6666'6666'6666},
7249 {0x401c'6666'6666'6666, 0x401c'6666'6666'6675},
7250 {0x401c'6666'6666'7566, 0x401c'6666'6675'c09e},
7251 {0x401c'6666'761a'f91e, 0x401c'6676'7553'7866},
7252 {0x401c'76cf'add2'6666, 0x4026'9504'1633'3333}},
7253 kVectorCalculationsSource,
7254 dst_result);
7255 }
7256
TEST_F(Riscv64InterpreterTest,TestVfmsac)7257 TEST_F(Riscv64InterpreterTest, TestVfmsac) {
7258 TestVectorFloatInstruction(0xb9881457, // vfmsac.vv v8, v16, v24, v0.t
7259 {{0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7260 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7261 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7262 {0x6a1f'cefd, 0x7629'21c4, 0x6232'9db3, 0x6e3c'70f9},
7263 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7264 {0xd555'5559, 0xd6ab'3339, 0xd555'5555, 0xd555'5a73},
7265 {0xfaad'fde4, 0xff80'0000, 0xf2c2'c69a, 0xfecd'99e3},
7266 {0xff80'0000, 0xff80'0000, 0xff80'0000, 0xff80'0000}},
7267 {{0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7268 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7269 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7270 {0x75b4'9040'f9f1'ea75, 0x6dcb'c6d1'12f0'a99b},
7271 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7272 {0xd614'25da'f5a1'f73b, 0xd555'5555'5555'5555},
7273 {0xfff0'0000'0000'0000, 0xfe5b'5815'60f1'ac51},
7274 {0xfff0'0000'0000'0000, 0xfff0'0000'0000'0000}},
7275 kVectorCalculationsSource);
7276 TestVectorFloatInstruction(0xb900d457, // vfmsac.vf v8, f1, v16, v0.t
7277 {{0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7278 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7279 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7280 {0xd555'5555, 0xd555'5555, 0xd555'5555, 0xd555'5555},
7281 {0xd555'5555, 0xd555'5555, 0xd555'559c, 0xd555'9e09},
7282 {0xd58f'b976, 0xd898'b8aa, 0xdc99'e27d, 0xe09c'b3a6},
7283 {0xe49f'8678, 0xe8a2'594a, 0xeca5'2c1d, 0xf0a7'fef0},
7284 {0xf4aa'd1c3, 0xf8ad'a496, 0xfcb0'7768, 0xff80'0000}},
7285 {{0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7286 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7287 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7288 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7289 {0xd555'5555'5555'5555, 0xd555'5555'5555'5555},
7290 {0xd780'0dff'a498'e5d7, 0xdf85'b3a5'4a3b'e0d2},
7291 {0xe790'194a'efe1'8678, 0xef95'bef0'9587'2c1d},
7292 {0xf7a0'2496'3b2c'd1c3, 0xffa5'ca3b'e0d2'7768}},
7293 kVectorCalculationsSource);
7294 }
7295
TEST_F(Riscv64InterpreterTest,TestVfnmsac)7296 TEST_F(Riscv64InterpreterTest, TestVfnmsac) {
7297 TestVectorFloatInstruction(0xbd881457, // vfnmsac.vv v8, v16, v24, v0.t
7298 {{0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7299 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7300 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7301 {0xea1f'cefd, 0xf629'21c4, 0xe232'9db3, 0xee3c'70f9},
7302 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7303 {0x5555'5559, 0x56ab'3339, 0x5555'5555, 0x5555'5a73},
7304 {0x7aad'fde4, 0x7f80'0000, 0x72c2'c69a, 0x7ecd'99e3},
7305 {0x7f80'0000, 0x7f80'0000, 0x7f80'0000, 0x7f80'0000}},
7306 {{0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7307 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7308 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7309 {0xf5b4'9040'f9f1'ea75, 0xedcb'c6d1'12f0'a99b},
7310 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7311 {0x5614'25da'f5a1'f73b, 0x5555'5555'5555'5555},
7312 {0x7ff0'0000'0000'0000, 0x7e5b'5815'60f1'ac51},
7313 {0x7ff0'0000'0000'0000, 0x7ff0'0000'0000'0000}},
7314 kVectorCalculationsSource);
7315 TestVectorFloatInstruction(0xbd00d457, // vfnmsac.vf v8, f1, v16, v0.t
7316 {{0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7317 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7318 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7319 {0x5555'5555, 0x5555'5555, 0x5555'5555, 0x5555'5555},
7320 {0x5555'5555, 0x5555'5555, 0x5555'559c, 0x5555'9e09},
7321 {0x558f'b976, 0x5898'b8aa, 0x5c99'e27d, 0x609c'b3a6},
7322 {0x649f'8678, 0x68a2'594a, 0x6ca5'2c1d, 0x70a7'fef0},
7323 {0x74aa'd1c3, 0x78ad'a496, 0x7cb0'7768, 0x7f80'0000}},
7324 {{0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7325 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7326 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7327 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7328 {0x5555'5555'5555'5555, 0x5555'5555'5555'5555},
7329 {0x5780'0dff'a498'e5d7, 0x5f85'b3a5'4a3b'e0d2},
7330 {0x6790'194a'efe1'8678, 0x6f95'bef0'9587'2c1d},
7331 {0x77a0'2496'3b2c'd1c3, 0x7fa5'ca3b'e0d2'7768}},
7332 kVectorCalculationsSource);
7333 }
7334
TEST_F(Riscv64InterpreterTest,TestVfmadd)7335 TEST_F(Riscv64InterpreterTest, TestVfmadd) {
7336 TestVectorFloatInstruction(0xa1881457, // vfmadd.vv v8, v16, v24, v0.t
7337 {{0x98dd'a63a, 0x9e28'a06a, 0xa0e6'e462, 0xa4ed'95be},
7338 {0xb624'b220, 0xbe2c'ba29, 0xb100'd4ec, 0xb504'308a},
7339 {0xd644'd240, 0xde4c'da49, 0xc654'e5df, 0xce5c'ca7c},
7340 {0xf664'f260, 0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78},
7341 {0xd922'4bb5, 0xdd25'a463, 0xe128'fd11, 0xe52c'55bf},
7342 {0xe92f'ae6d, 0xed33'071b, 0xf136'5fc9, 0xf539'b877},
7343 {0xf93d'1125, 0xfd40'69d3, 0xff80'0000, 0xff80'0000},
7344 {0xff80'0000, 0xff80'0000, 0xff80'0000, 0xff80'0000}},
7345 {{0x9e0c'9a09'9d86'3e2c, 0xa474'5e08'5cb1'b0b0},
7346 {0xbe2c'ba29'b624'b220, 0xb484'68bd'bcbc'6610},
7347 {0xde4c'da49'd644'd240, 0xce5c'ca58'c654'c251},
7348 {0xfe6c'fa69'f664'f260, 0xee7c'ea78'e674'e271},
7349 {0xdcae'5c5b'af03'ac55, 0xe4b4'88dd'dcdc'8630},
7350 {0xecbe'71c6'6f19'1715, 0xf4c4'9393'3ce7'3b90},
7351 {0xfcce'8731'2f2e'81d5, 0xfff0'0000'0000'0000},
7352 {0xfff0'0000'0000'0000, 0xfff0'0000'0000'0000}},
7353
7354 kVectorCalculationsSource);
7355
7356 TestVectorFloatInstruction(0xa100d457, // vfmadd.vf v8, f1, v16, v0.t
7357 {{0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7358 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7359 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7360 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7361 {0x5696'0000, 0x5696'0000, 0x5695'fffe, 0x5695'fe62},
7362 {0x5694'5a5d, 0xd70b'd554, 0xdb5a'8e58, 0xdf5e'dd11},
7363 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7364 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7365 {{0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7366 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7367 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7368 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7369 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7370 {0xd756'd554'd2da'd150, 0xdf5e'dd5c'db5a'd958},
7371 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7372 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7373
7374 kVectorCalculationsSource);
7375 }
7376
TEST_F(Riscv64InterpreterTest,TestVfnmadd)7377 TEST_F(Riscv64InterpreterTest, TestVfnmadd) {
7378 TestVectorFloatInstruction(0xa5881457, // vfnmadd.vv v8, v16, v24, v0.t
7379 {{0x18dd'a63a, 0x1e28'a06a, 0x20e6'e462, 0x24ed'95be},
7380 {0x3624'b220, 0x3e2c'ba29, 0x3100'd4ec, 0x3504'308a},
7381 {0x5644'd240, 0x5e4c'da49, 0x4654'e5df, 0x4e5c'ca7c},
7382 {0x7664'f260, 0x7e6c'fa69, 0x6674'e271, 0x6e7c'ea78},
7383 {0x5922'4bb5, 0x5d25'a463, 0x6128'fd11, 0x652c'55bf},
7384 {0x692f'ae6d, 0x6d33'071b, 0x7136'5fc9, 0x7539'b877},
7385 {0x793d'1125, 0x7d40'69d3, 0x7f80'0000, 0x7f80'0000},
7386 {0x7f80'0000, 0x7f80'0000, 0x7f80'0000, 0x7f80'0000}},
7387 {{0x1e0c'9a09'9d86'3e2c, 0x2474'5e08'5cb1'b0b0},
7388 {0x3e2c'ba29'b624'b220, 0x3484'68bd'bcbc'6610},
7389 {0x5e4c'da49'd644'd240, 0x4e5c'ca58'c654'c251},
7390 {0x7e6c'fa69'f664'f260, 0x6e7c'ea78'e674'e271},
7391 {0x5cae'5c5b'af03'ac55, 0x64b4'88dd'dcdc'8630},
7392 {0x6cbe'71c6'6f19'1715, 0x74c4'9393'3ce7'3b90},
7393 {0x7cce'8731'2f2e'81d5, 0x7ff0'0000'0000'0000},
7394 {0x7ff0'0000'0000'0000, 0x7ff0'0000'0000'0000}},
7395 kVectorCalculationsSource);
7396
7397 TestVectorFloatInstruction(0xa500d457, // vfmadd.vf v8, f1, v16, v0.t
7398 {{0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7399 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7400 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7401 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7402 {0xd696'0000, 0xd696'0000, 0xd695'fffe, 0xd695'fe62},
7403 {0xd694'5a5d, 0x570b'd554, 0x5b5a'8e58, 0x5f5e'dd11},
7404 {0x6362'e160, 0x6766'e564, 0x6b6a'e968, 0x6f6e'ed6c},
7405 {0x7372'f170, 0x7776'f574, 0x7b7a'f978, 0x7f7e'fd7c}},
7406 {{0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7407 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7408 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7409 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7410 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7411 {0x5756'd554'd2da'd150, 0x5f5e'dd5c'db5a'd958},
7412 {0x6766'e564'e362'e160, 0x6f6e'ed6c'eb6a'e968},
7413 {0x7776'f574'f372'f170, 0x7f7e'fd7c'fb7a'f978}},
7414 kVectorCalculationsSource);
7415 }
7416
TEST_F(Riscv64InterpreterTest,TestVfmsub)7417 TEST_F(Riscv64InterpreterTest, TestVfmsub) {
7418 TestVectorFloatInstruction(0xa9881457, // vfmsub.vv v8, v16, v24, v0.t
7419 {{0x98d5'5d1a, 0x1de1'2750, 0xa0e6'e462, 0xa4ed'95be},
7420 {0x3624'b220, 0x3e2c'ba29, 0xb100'd4e6, 0xb504'2aa4},
7421 {0x5644'd240, 0x5e4c'da49, 0x4654'9ec3, 0x4e5c'ca34},
7422 {0x7664'f260, 0x7e6c'fa69, 0x6674'e271, 0x6e7c'ea78},
7423 {0xd922'4bb5, 0xdd25'a463, 0xe128'fd11, 0xe52c'55bf},
7424 {0xe92f'ae6d, 0xed33'071b, 0xf136'5fc9, 0xf539'b877},
7425 {0xf93d'1125, 0xfd40'69d3, 0xff80'0000, 0xff80'0000},
7426 {0xff80'0000, 0xff80'0000, 0xff80'0000, 0xff80'0000}},
7427 {{0x1e0c'9a09'8e82'e5d4, 0xa474'5e08'5cb1'b0b0},
7428 {0x3e2c'ba29'b624'b220, 0xb484'68bd'bcbc'6610},
7429 {0x5e4c'da49'd644'd240, 0x4e5c'ca58'c654'c251},
7430 {0x7e6c'fa69'f664'f260, 0x6e7c'ea78'e674'e271},
7431 {0xdcae'5c5b'af03'ac55, 0xe4b4'88dd'dcdc'8630},
7432 {0xecbe'71c6'6f19'1715, 0xf4c4'9393'3ce7'3b90},
7433 {0xfcce'8731'2f2e'81d5, 0xfff0'0000'0000'0000},
7434 {0xfff0'0000'0000'0000, 0xfff0'0000'0000'0000}},
7435 kVectorCalculationsSource);
7436
7437 TestVectorFloatInstruction(0xa900d457, // vfmsub.vf v8, f1, v16, v0.t
7438 {{0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7439 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7440 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7441 {0x5696'0000, 0x5696'0000, 0x5696'0000, 0x5696'0000},
7442 {0x5696'0000, 0x5696'0000, 0x5696'0001, 0x5696'019d},
7443 {0x5697'a5a2, 0x5790'eaaa, 0x5b5b'2458, 0x5f5e'dda7},
7444 {0x6362'e160, 0x6766'e564, 0x6b6a'e968, 0x6f6e'ed6c},
7445 {0x7372'f170, 0x7776'f574, 0x7b7a'f978, 0x7f7e'fd7c}},
7446 {{0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7447 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7448 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7449 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7450 {0x557e'0000'0000'0000, 0x557e'0000'0000'0000},
7451 {0x5756'd554'd3ca'd150, 0x5f5e'dd5c'db5a'd958},
7452 {0x6766'e564'e362'e160, 0x6f6e'ed6c'eb6a'e968},
7453 {0x7776'f574'f372'f170, 0x7f7e'fd7c'fb7a'f978}},
7454 kVectorCalculationsSource);
7455 }
7456
TEST_F(Riscv64InterpreterTest,TestVfnmsub)7457 TEST_F(Riscv64InterpreterTest, TestVfnmsub) {
7458 TestVectorFloatInstruction(0xad881457, // vfnmsub.vv v8, v16, v24, v0.t
7459 {{0x18d5'5d1a, 0x9de1'2750, 0x20e6'e462, 0x24ed'95be},
7460 {0xb624'b220, 0xbe2c'ba29, 0x3100'd4e6, 0x3504'2aa4},
7461 {0xd644'd240, 0xde4c'da49, 0xc654'9ec3, 0xce5c'ca34},
7462 {0xf664'f260, 0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78},
7463 {0x5922'4bb5, 0x5d25'a463, 0x6128'fd11, 0x652c'55bf},
7464 {0x692f'ae6d, 0x6d33'071b, 0x7136'5fc9, 0x7539'b877},
7465 {0x793d'1125, 0x7d40'69d3, 0x7f80'0000, 0x7f80'0000},
7466 {0x7f80'0000, 0x7f80'0000, 0x7f80'0000, 0x7f80'0000}},
7467 {{0x9e0c'9a09'8e82'e5d4, 0x2474'5e08'5cb1'b0b0},
7468 {0xbe2c'ba29'b624'b220, 0x3484'68bd'bcbc'6610},
7469 {0xde4c'da49'd644'd240, 0xce5c'ca58'c654'c251},
7470 {0xfe6c'fa69'f664'f260, 0xee7c'ea78'e674'e271},
7471 {0x5cae'5c5b'af03'ac55, 0x64b4'88dd'dcdc'8630},
7472 {0x6cbe'71c6'6f19'1715, 0x74c4'9393'3ce7'3b90},
7473 {0x7cce'8731'2f2e'81d5, 0x7ff0'0000'0000'0000},
7474 {0x7ff0'0000'0000'0000, 0x7ff0'0000'0000'0000}},
7475 kVectorCalculationsSource);
7476
7477 TestVectorFloatInstruction(0xad00d457, // vfnmsub.vf v8, f1, v16, v0.t
7478 {{0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7479 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7480 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7481 {0xd696'0000, 0xd696'0000, 0xd696'0000, 0xd696'0000},
7482 {0xd696'0000, 0xd696'0000, 0xd696'0001, 0xd696'019d},
7483 {0xd697'a5a2, 0xd790'eaaa, 0xdb5b'2458, 0xdf5e'dda7},
7484 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7485 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7486 {{0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7487 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7488 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7489 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7490 {0xd57e'0000'0000'0000, 0xd57e'0000'0000'0000},
7491 {0xd756'd554'd3ca'd150, 0xdf5e'dd5c'db5a'd958},
7492 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7493 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7494 kVectorCalculationsSource);
7495 }
7496
TEST_F(Riscv64InterpreterTest,TestVfmin)7497 TEST_F(Riscv64InterpreterTest, TestVfmin) {
7498 TestVectorFloatInstruction(0x1100d457, // vfmin.vf v8, v16, f1, v0.t
7499 {{0xf005'f005, 0xf005'f005, 0x4040'4040, 0x40b4'0000},
7500 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7501 {0x4016'4016, 0x4016'4016, 0x0000'0000, 0x4016'8000},
7502 {0xaaaa'aaaa, 0xaaaa'aaaa, 0x1111'1111, 0x1111'1111},
7503 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7504 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7505 {0xa9bb'bbbb, 0xa9bb'bbbb, 0xa9bb'bbbb, 0xa9bb'bbbb},
7506 {0xa9a9'a9a9, 0xa9a9'a9a9, 0xa9a9'a9a9, 0xa9a9'a9a9}},
7507 {{0xf005'f005'f005'f005, 0x4016'8000'0000'0000},
7508 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7509 {0x4016'4016'4016'4016, 0x4016'8000'0000'0000},
7510 {0xaaaa'aaaa'aaaa'aaaa, 0x1111'1111'1111'1111},
7511 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7512 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7513 {0xa9bb'bbbb'a9bb'bbbb, 0xa9bb'bbbb'a9bb'bbbb},
7514 {0xa9a9'a9a9'a9a9'a9a9, 0xa9a9'a9a9'a9a9'a9a9}},
7515 kVectorComparisonSource);
7516 TestVectorFloatInstruction(0x110c1457, // vfmin.vv v8,v16,v24,v0.t
7517 {{0xf005'f005, 0xf005'f005, 0x4040'4040, 0x7fc0'0000},
7518 {0x1111'1111, 0x1111'1111, 0x1111'1111, 0x1111'1111},
7519 {0x4016'4016, 0x4016'4016, 0x0000'0000, 0x4016'8000},
7520 {0xaaaa'aaaa, 0xaaaa'aaaa, 0x1111'1111, 0x1111'1111},
7521 {0x8684'8280, 0x8e8c'8a89, 0x9694'9291, 0x9e9c'9a98},
7522 {0xa6a4'a2a0, 0xaeac'aaa9, 0xb6b4'b2b1, 0xbebc'bab8},
7523 {0xc6c4'c2c0, 0xcecc'cac9, 0xd6d4'd2d1, 0xdedc'dad8},
7524 {0xe6e4'e2e0, 0xeeec'eae9, 0xf6f4'f2f1, 0xfefc'faf8}},
7525 {{0xf005'f005'f005'f005, 0x7ff8'0000'0000'0000},
7526 {0x1111'1111'1111'1111, 0x1111'1111'1111'1111},
7527 {0x4016'4016'4016'4016, 0x4016'8000'0000'0000},
7528 {0xaaaa'aaaa'aaaa'aaaa, 0x1111'1111'1111'1111},
7529 {0x8e8c'8a89'8684'8280, 0x9e9c'9a98'9694'9291},
7530 {0xaeac'aaa9'a6a4'a2a0, 0xbebc'bab8'b6b4'b2b1},
7531 {0xcecc'cac9'c6c4'c2c0, 0xdedc'dad8'd6d4'd2d1},
7532 {0xeeec'eae9'e6e4'e2e0, 0xfefc'faf8'f6f4'f2f1}},
7533 kVectorComparisonSource);
7534 }
7535
TEST_F(Riscv64InterpreterTest,TestVfmax)7536 TEST_F(Riscv64InterpreterTest, TestVfmax) {
7537 TestVectorFloatInstruction(0x1900d457, // vfmax.vf v8, v16, f1, v0.t
7538 {{0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7539 {0x40b4'40b4, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7540 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7541 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7542 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7543 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7544 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
7545 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000}},
7546 {{0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7547 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7548 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7549 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7550 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7551 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7552 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
7553 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000}},
7554 kVectorComparisonSource);
7555 TestVectorFloatInstruction(0x190c1457, // vfmax.vv v8,v16,v24,v0.t
7556 {{0xf005'f005, 0xf005'f005, 0x4040'4040, 0x7fc0'0000},
7557 {0x40b4'40b4, 0x1111'1111, 0x40b4'0000, 0x1111'1111},
7558 {0x4016'4016, 0x4016'4016, 0x0000'0000, 0x4016'8000},
7559 {0x6664'6260, 0x6e6c'6a69, 0x7674'7271, 0x7e7c'7a78},
7560 {0x8684'8280, 0x8e8c'8a89, 0x9694'9291, 0x9e9c'9a98},
7561 {0xa6a4'a2a0, 0xaeac'aaa9, 0xb6b4'b2b1, 0xbebc'bab8},
7562 {0xa9bb'bbbb, 0xa9bb'bbbb, 0xa9bb'bbbb, 0xa9bb'bbbb},
7563 {0xa9a9'a9a9, 0xa9a9'a9a9, 0xa9a9'a9a9, 0xa9a9'a9a9}},
7564 {{0xf005'f005'f005'f005, 0x7ff8'0000'0000'0000},
7565 {0x1111'1111'1111'1111, 0x1111'1111'1111'1111},
7566 {0x4016'4016'4016'4016, 0x4016'8000'0000'0000},
7567 {0x6e6c'6a69'6664'6260, 0x7e7c'7a78'7674'7271},
7568 {0x8e8c'8a89'8684'8280, 0x9e9c'9a98'9694'9291},
7569 {0xaeac'aaa9'a6a4'a2a0, 0xbebc'bab8'b6b4'b2b1},
7570 {0xa9bb'bbbb'a9bb'bbbb, 0xa9bb'bbbb'a9bb'bbbb},
7571 {0xa9a9'a9a9'a9a9'a9a9, 0xa9a9'a9a9'a9a9'a9a9}},
7572 kVectorComparisonSource);
7573 }
7574
TEST_F(Riscv64InterpreterTest,TestVfsgnj)7575 TEST_F(Riscv64InterpreterTest, TestVfsgnj) {
7576 TestVectorFloatInstruction(0x210c1457, // vfsgnj.vv v8, v16, v24, v0.t
7577 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
7578 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
7579 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
7580 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
7581 {0x4342'c140, 0x4746'c544, 0x4b4a'c948, 0x4f4e'cd4c},
7582 {0x5352'd150, 0x5756'd554, 0x5b5a'd958, 0x5f5e'dd5c},
7583 {0x6362'e160, 0x6766'e564, 0x6b6a'e968, 0x6f6e'ed6c},
7584 {0x7372'f170, 0x7776'f574, 0x7b7a'f978, 0x7f7e'fd7c}},
7585 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
7586 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
7587 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
7588 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
7589 {0x4746'c544'c342'c140, 0x4f4e'cd4c'cb4a'c948},
7590 {0x5756'd554'd352'd150, 0x5f5e'dd5c'db5a'd958},
7591 {0x6766'e564'e362'e160, 0x6f6e'ed6c'eb6a'e968},
7592 {0x7776'f574'f372'f170, 0x7f7e'fd7c'fb7a'f978}},
7593 kVectorCalculationsSource);
7594 TestVectorFloatInstruction(0x2100d457, // vfsgnj.vf v8, v16, f1, v0.t
7595 {{0x0302'8100, 0x0706'8504, 0x0b0a'8908, 0x0f0e'8d0c},
7596 {0x1312'9110, 0x1716'9514, 0x1b1a'9918, 0x1f1e'9d1c},
7597 {0x2322'a120, 0x2726'a524, 0x2b2a'a928, 0x2f2e'ad2c},
7598 {0x3332'b130, 0x3736'b534, 0x3b3a'b938, 0x3f3e'bd3c},
7599 {0x4342'c140, 0x4746'c544, 0x4b4a'c948, 0x4f4e'cd4c},
7600 {0x5352'd150, 0x5756'd554, 0x5b5a'd958, 0x5f5e'dd5c},
7601 {0x6362'e160, 0x6766'e564, 0x6b6a'e968, 0x6f6e'ed6c},
7602 {0x7372'f170, 0x7776'f574, 0x7b7a'f978, 0x7f7e'fd7c}},
7603 {{0x0706'8504'8302'8100, 0x0f0e'8d0c'8b0a'8908},
7604 {0x1716'9514'9312'9110, 0x1f1e'9d1c'9b1a'9918},
7605 {0x2726'a524'a322'a120, 0x2f2e'ad2c'ab2a'a928},
7606 {0x3736'b534'b332'b130, 0x3f3e'bd3c'bb3a'b938},
7607 {0x4746'c544'c342'c140, 0x4f4e'cd4c'cb4a'c948},
7608 {0x5756'd554'd352'd150, 0x5f5e'dd5c'db5a'd958},
7609 {0x6766'e564'e362'e160, 0x6f6e'ed6c'eb6a'e968},
7610 {0x7776'f574'f372'f170, 0x7f7e'fd7c'fb7a'f978}},
7611 kVectorCalculationsSource);
7612 TestVectorFloatInstruction(0x250c1457, // vfsgnjn.vv v8, v16, v24, v0.t
7613 {{0x0302'8100, 0x0706'8504, 0x0b0a'8908, 0x0f0e'8d0c},
7614 {0x1312'9110, 0x1716'9514, 0x1b1a'9918, 0x1f1e'9d1c},
7615 {0x2322'a120, 0x2726'a524, 0x2b2a'a928, 0x2f2e'ad2c},
7616 {0x3332'b130, 0x3736'b534, 0x3b3a'b938, 0x3f3e'bd3c},
7617 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
7618 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
7619 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7620 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7621 {{0x0706'8504'8302'8100, 0x0f0e'8d0c'8b0a'8908},
7622 {0x1716'9514'9312'9110, 0x1f1e'9d1c'9b1a'9918},
7623 {0x2726'a524'a322'a120, 0x2f2e'ad2c'ab2a'a928},
7624 {0x3736'b534'b332'b130, 0x3f3e'bd3c'bb3a'b938},
7625 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
7626 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
7627 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7628 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7629 kVectorCalculationsSource);
7630 TestVectorFloatInstruction(0x2500d457, // vfsgnjn.vf v8, v16, f1, v0.t
7631 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
7632 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
7633 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
7634 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
7635 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
7636 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
7637 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7638 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7639 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
7640 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
7641 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
7642 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
7643 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
7644 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
7645 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7646 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7647 kVectorCalculationsSource);
7648 TestVectorFloatInstruction(0x290c1457, // vfsgnjx.vv v8, v16, v24, v0.t
7649 {{0x0302'8100, 0x0706'8504, 0x0b0a'8908, 0x0f0e'8d0c},
7650 {0x1312'9110, 0x1716'9514, 0x1b1a'9918, 0x1f1e'9d1c},
7651 {0x2322'a120, 0x2726'a524, 0x2b2a'a928, 0x2f2e'ad2c},
7652 {0x3332'b130, 0x3736'b534, 0x3b3a'b938, 0x3f3e'bd3c},
7653 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
7654 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
7655 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7656 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7657 {{0x0706'8504'8302'8100, 0x0f0e'8d0c'8b0a'8908},
7658 {0x1716'9514'9312'9110, 0x1f1e'9d1c'9b1a'9918},
7659 {0x2726'a524'a322'a120, 0x2f2e'ad2c'ab2a'a928},
7660 {0x3736'b534'b332'b130, 0x3f3e'bd3c'bb3a'b938},
7661 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
7662 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
7663 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7664 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7665 kVectorCalculationsSource);
7666 TestVectorFloatInstruction(0x2900d457, // vfsgnjx.vf v8, v16, f1, v0.t
7667 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
7668 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
7669 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
7670 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
7671 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
7672 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
7673 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
7674 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
7675 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
7676 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
7677 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
7678 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
7679 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
7680 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
7681 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
7682 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
7683 kVectorCalculationsSource);
7684 }
7685
TEST_F(Riscv64InterpreterTest,TestVredsum)7686 TEST_F(Riscv64InterpreterTest, TestVredsum) {
7687 TestVectorReductionInstruction(
7688 0x1882457, // vredsum.vs v8,v24,v16,v0.t
7689 // expected_result_vd0_int8
7690 {242, 228, 200, 144, /* unused */ 0, 146, 44, 121},
7691 // expected_result_vd0_int16
7692 {0x0172, 0x82e4, 0x88c8, 0xa090, /* unused */ 0, 0x1300, 0xa904, 0xe119},
7693 // expected_result_vd0_int32
7694 {0xcb44'b932,
7695 0x9407'71e4,
7696 0xa70e'64c8,
7697 0xd312'5090,
7698 /* unused */ 0,
7699 /* unused */ 0,
7700 0x1907'1300,
7701 0xb713'ad09},
7702 // expected_result_vd0_int64
7703 {0xb32f'a926'9f1b'9511,
7704 0x1f99'0d88'fb74'e962,
7705 0xb92c'970e'74e8'52c4,
7706 0xef4e'ad14'6aca'2888,
7707 /* unused */ 0,
7708 /* unused */ 0,
7709 /* unused */ 0,
7710 0x2513'1f0e'1907'1300},
7711 // expected_result_vd0_with_mask_int8
7712 {39, 248, 142, 27, /* unused */ 0, 0, 154, 210},
7713 // expected_result_vd0_with_mask_int16
7714 {0x5f45, 0xc22f, 0x99d0, 0x98bf, /* unused */ 0, 0x1300, 0x1300, 0x4b15},
7715 // expected_result_vd0_with_mask_int32
7716 {0x2d38'1f29,
7717 0x99a1'838a,
7718 0x1989'ef5c,
7719 0x9cf4'4aa1,
7720 /* unused */ 0,
7721 /* unused */ 0,
7722 0x1907'1300,
7723 0x1907'1300},
7724 // expected_result_vd0_with_mask_int64
7725 {0x2513'1f0e'1907'1300,
7726 0x917c'8370'7560'6751,
7727 0x4e56'3842'222a'0c13,
7728 0xc833'9e0e'73df'49b5,
7729 /* unused */ 0,
7730 /* unused */ 0,
7731 /* unused */ 0,
7732 0x2513'1f0e'1907'1300},
7733 kVectorCalculationsSource);
7734 }
7735
TEST_F(Riscv64InterpreterTest,TestVfredosum)7736 TEST_F(Riscv64InterpreterTest, TestVfredosum) {
7737 TestVectorReductionInstruction(0xd881457, // vfredosum.vs v8, v24, v16, v0.t
7738 // expected_result_vd0_int32
7739 {0x9e0c'9a8e,
7740 0xbe2c'bace,
7741 0xfe6c'fb4e,
7742 0x7e6b'fc4d,
7743 /* unused */ 0,
7744 /* unused */ 0,
7745 0x9604'9200,
7746 0x9e0c'9a8e},
7747 // expected_result_vd0_int64
7748 {0x9e0c'9a09'9604'9200,
7749 0xbe2c'ba29'b624'b220,
7750 0xfe6c'fa69'f664'f260,
7751 0x7eec'5def'0cee'0dee,
7752 /* unused */ 0,
7753 /* unused */ 0,
7754 /* unused */ 0,
7755 0x9e0c'9a09'9604'9200},
7756 // expected_result_vd0_with_mask_int32
7757 {0x9604'929d,
7758 0xbe2c'ba29,
7759 0xfe6c'fb4e,
7760 0x7e6b'fa84,
7761 /* unused */ 0,
7762 /* unused */ 0,
7763 0x9604'9200,
7764 0x9604'9200},
7765 // expected_result_vd0_with_mask_int64
7766 {0x9e0c'9a09'9604'9200,
7767 0xbe2c'ba29'b624'b220,
7768 0xee7c'ea78'e674'e271,
7769 0x6efc'4e0d'ee0d'ee0f,
7770 /* unused */ 0,
7771 /* unused */ 0,
7772 /* unused */ 0,
7773 0x9e0c'9a09'9604'9200},
7774 kVectorCalculationsSource);
7775 }
7776
7777 // Currently Vfredusum is implemented as Vfredosum (as explicitly permitted by RVV 1.0).
7778 // If we would implement some speedups which would change results then we may need to alter tests.
TEST_F(Riscv64InterpreterTest,TestVfredusum)7779 TEST_F(Riscv64InterpreterTest, TestVfredusum) {
7780 TestVectorReductionInstruction(0x5881457, // vfredusum.vs v8, v24, v16, v0.t
7781 // expected_result_vd0_int32
7782 {0x9e0c'9a8e,
7783 0xbe2c'bace,
7784 0xfe6c'fb4e,
7785 0x7e6b'fc4d,
7786 /* unused */ 0,
7787 /* unused */ 0,
7788 0x9604'9200,
7789 0x9e0c'9a8e},
7790 // expected_result_vd0_int64
7791 {0x9e0c'9a09'9604'9200,
7792 0xbe2c'ba29'b624'b220,
7793 0xfe6c'fa69'f664'f260,
7794 0x7eec'5def'0cee'0dee,
7795 /* unused */ 0,
7796 /* unused */ 0,
7797 /* unused */ 0,
7798 0x9e0c'9a09'9604'9200},
7799 // expected_result_vd0_with_mask_int32
7800 {0x9604'929d,
7801 0xbe2c'ba29,
7802 0xfe6c'fb4e,
7803 0x7e6b'fa84,
7804 /* unused */ 0,
7805 /* unused */ 0,
7806 0x9604'9200,
7807 0x9604'9200},
7808 // expected_result_vd0_with_mask_int64
7809 {0x9e0c'9a09'9604'9200,
7810 0xbe2c'ba29'b624'b220,
7811 0xee7c'ea78'e674'e271,
7812 0x6efc'4e0d'ee0d'ee0f,
7813 /* unused */ 0,
7814 /* unused */ 0,
7815 /* unused */ 0,
7816 0x9e0c'9a09'9604'9200},
7817 kVectorCalculationsSource);
7818 }
7819
TEST_F(Riscv64InterpreterTest,TestVredand)7820 TEST_F(Riscv64InterpreterTest, TestVredand) {
7821 TestVectorReductionInstruction(
7822 0x5882457, // vredand.vs v8,v24,v16,v0.t
7823 // expected_result_vd0_int8
7824 {0, 0, 0, 0, /* unused */ 0, 0, 0, 0},
7825 // expected_result_vd0_int16
7826 {0x8000, 0x8000, 0x8000, 0x0000, /* unused */ 0, 0x8000, 0x8000, 0x8000},
7827 // expected_result_vd0_int32
7828 {0x8200'8000,
7829 0x8200'8000,
7830 0x8200'8000,
7831 0x0200'0000,
7832 /* unused */ 0,
7833 /* unused */ 0,
7834 0x8200'8000,
7835 0x8200'8000},
7836 // expected_result_vd0_int64
7837 {0x8604'8000'8200'8000,
7838 0x8604'8000'8200'8000,
7839 0x8604'8000'8200'8000,
7840 0x0604'0000'0200'0000,
7841 /* unused */ 0,
7842 /* unused */ 0,
7843 /* unused */ 0,
7844 0x8604'8000'8200'8000},
7845 // expected_result_vd0_with_mask_int8
7846 {0, 0, 0, 0, /* unused */ 0, 0, 0, 0},
7847 // expected_result_vd0_with_mask_int16
7848 {0x8000, 0x8000, 0x8000, 0x0000, /* unused */ 0, 0x8000, 0x8000, 0x8000},
7849 // expected_result_vd0_with_mask_int32
7850 {0x8200'8000,
7851 0x8200'8000,
7852 0x8200'8000,
7853 0x0200'0000,
7854 /* unused */ 0,
7855 /* unused */ 0,
7856 0x8200'8000,
7857 0x8200'8000},
7858 // expected_result_vd0_with_mask_int64
7859 {0x8604'8000'8200'8000,
7860 0x8604'8000'8200'8000,
7861 0x8604'8000'8200'8000,
7862 0x0604'0000'0200'0000,
7863 /* unused */ 0,
7864 /* unused */ 0,
7865 /* unused */ 0,
7866 0x8604'8000'8200'8000},
7867 kVectorCalculationsSource);
7868 }
7869
TEST_F(Riscv64InterpreterTest,TestVredor)7870 TEST_F(Riscv64InterpreterTest, TestVredor) {
7871 TestVectorReductionInstruction(
7872 0x9882457, // vredor.vs v8,v24,v16,v0.t
7873 // expected_result_vd0_int8
7874 {159, 191, 255, 255, /* unused */ 0, 146, 150, 159},
7875 // expected_result_vd0_int16
7876 {0x9f1d, 0xbf3d, 0xff7d, 0xfffd, /* unused */ 0, 0x9300, 0x9704, 0x9f0d},
7877 // expected_result_vd0_int32
7878 {0x9f1e'9b19,
7879 0xbf3e'bb39,
7880 0xff7e'fb79,
7881 0xfffe'fbf9,
7882 /* unused */ 0,
7883 /* unused */ 0,
7884 0x9706'9300,
7885 0x9f0e'9b09},
7886 // expected_result_vd0_int64
7887 {0x9f1e'9f1d'9716'9311,
7888 0xbf3e'bf3d'b736'b331,
7889 0xff7e'ff7d'f776'f371,
7890 0xfffe'fffd'f7f6'f3f1,
7891 /* unused */ 0,
7892 /* unused */ 0,
7893 /* unused */ 0,
7894 0x9f0e'9f0d'9706'9300},
7895 // expected_result_vd0_with_mask_int8
7896 {159, 191, 255, 255, /* unused */ 0, 0, 150, 158},
7897 // expected_result_vd0_with_mask_int16
7898 {0x9f1d, 0xbf3d, 0xff7d, 0xfffd, /* unused */ 0, 0x9300, 0x9300, 0x9f0d},
7899 // expected_result_vd0_with_mask_int32
7900 {0x9f1e'9b19,
7901 0xbf3e'bb39,
7902 0xff7e'fb79,
7903 0xfffe'fbf9,
7904 /* unused */ 0,
7905 /* unused */ 0,
7906 0x9706'9300,
7907 0x9706'9300},
7908 // expected_result_vd0_with_mask_int64
7909 {0x9f0e'9f0d'9706'9300,
7910 0xbf3e'bf3d'b736'b331,
7911 0xff7e'ff7d'f776'f371,
7912 0xfffe'fffd'f7f6'f3f1,
7913 /* unused */ 0,
7914 /* unused */ 0,
7915 /* unused */ 0,
7916 0x9f0e'9f0d'9706'9300},
7917 kVectorCalculationsSource);
7918 }
7919
TEST_F(Riscv64InterpreterTest,TestVredxor)7920 TEST_F(Riscv64InterpreterTest, TestVredxor) {
7921 TestVectorReductionInstruction(
7922 0xd882457, // vredxor.vs v8,v24,v16,v0.t
7923 // expected_result_vd0_int8
7924 {0, 0, 0, 0, /* unused */ 0, 146, 0, 1},
7925 // expected_result_vd0_int16
7926 {0x8100, 0x8100, 0x8100, 0x8100, /* unused */ 0, 0x1300, 0x8504, 0x8101},
7927 // expected_result_vd0_int32
7928 {0x8302'8100,
7929 0x8302'8100,
7930 0x8302'8100,
7931 0x8302'8100,
7932 /* unused */ 0,
7933 /* unused */ 0,
7934 0x1506'1300,
7935 0x8b0a'8909},
7936 // expected_result_vd0_int64
7937 {0x9716'9515'9312'9111,
7938 0x8706'8504'8302'8100,
7939 0x8706'8504'8302'8100,
7940 0x8706'8504'8302'8100,
7941 /* unused */ 0,
7942 /* unused */ 0,
7943 /* unused */ 0,
7944 0x190a'1f0d'1506'1300},
7945 // expected_result_vd0_with_mask_int8
7946 {143, 154, 150, 43, /* unused */ 0, 0, 146, 150},
7947 // expected_result_vd0_with_mask_int16
7948 {0x1f0d, 0xbd3d, 0x9514, 0x8d0d, /* unused */ 0, 0x1300, 0x1300, 0x1705},
7949 // expected_result_vd0_with_mask_int32
7950 {0x1d0e'1b09,
7951 0x0d1e'0b18,
7952 0xfb7a'f978,
7953 0xab2a'a929,
7954 /* unused */ 0,
7955 /* unused */ 0,
7956 0x1506'1300,
7957 0x1506'1300},
7958 // expected_result_vd0_with_mask_int64
7959 {0x190a'1f0d'1506'1300,
7960 0x091a'0f1c'0516'0311,
7961 0x293a'2f3c'2536'2331,
7962 0x77f6'75f5'73f2'71f1,
7963 /* unused */ 0,
7964 /* unused */ 0,
7965 /* unused */ 0,
7966 0x190a'1f0d'1506'1300},
7967 kVectorCalculationsSource);
7968 }
7969
TEST_F(Riscv64InterpreterTest,TestVredminu)7970 TEST_F(Riscv64InterpreterTest, TestVredminu) {
7971 TestVectorReductionInstruction(
7972 0x11882457, // vredminu.vs v8,v24,v16,v0.t
7973 // expected_result_vd0_int8
7974 {0, 0, 0, 0, /* unused */ 0, 0, 0, 0},
7975 // expected_result_vd0_int16
7976 {0x8100, 0x8100, 0x8100, 0x0291, /* unused */ 0, 0x8100, 0x8100, 0x8100},
7977 // expected_result_vd0_int32
7978 {0x83028100,
7979 0x83028100,
7980 0x83028100,
7981 0x06940291,
7982 /* unused */ 0,
7983 /* unused */ 0,
7984 0x83028100,
7985 0x83028100},
7986 // expected_result_vd0_int64
7987 {0x8706'8504'8302'8100,
7988 0x8706'8504'8302'8100,
7989 0x8706'8504'8302'8100,
7990 0x0e9c'0a98'0694'0291,
7991 /* unused */ 0,
7992 /* unused */ 0,
7993 /* unused */ 0,
7994 0x8706'8504'8302'8100},
7995 // expected_result_vd0_with_mask_int8
7996 {0, 0, 0, 0, /* unused */ 0, 0, 0, 0},
7997 // expected_result_vd0_with_mask_int16
7998 {0x8100, 0x8100, 0x8100, 0x0291, /* unused */ 0, 0x8100, 0x8100, 0x8100},
7999 // expected_result_vd0_with_mask_int32
8000 {0x8302'8100,
8001 0x8302'8100,
8002 0x8302'8100,
8003 0x0e9c'0a98,
8004 /* unused */ 0,
8005 /* unused */ 0,
8006 0x8302'8100,
8007 0x8302'8100},
8008 // expected_result_vd0_with_mask_int64
8009 {0x8706'8504'8302'8100,
8010 0x8706'8504'8302'8100,
8011 0x8706'8504'8302'8100,
8012 0x1e8c'1a89'1684'1280,
8013 /* unused */ 0,
8014 /* unused */ 0,
8015 /* unused */ 0,
8016 0x8706'8504'8302'8100},
8017 kVectorCalculationsSource);
8018 }
8019
TEST_F(Riscv64InterpreterTest,TestVredmin)8020 TEST_F(Riscv64InterpreterTest, TestVredmin) {
8021 TestVectorReductionInstruction(
8022 0x15882457, // vredmin.vs v8,v24,v16,v0.t
8023 // expected_result_vd0_int8
8024 {130, 130, 130, 128, /* unused */ 0, 146, 146, 146},
8025 // expected_result_vd0_int16
8026 {0x8100, 0x8100, 0x8100, 0x8100, /* unused */ 0, 0x8100, 0x8100, 0x8100},
8027 // expected_result_vd0_int32
8028 {0x8302'8100,
8029 0x8302'8100,
8030 0x8302'8100,
8031 0x8302'8100,
8032 /* unused */ 0,
8033 /* unused */ 0,
8034 0x8302'8100,
8035 0x8302'8100},
8036 // expected_result_vd0_int64
8037 {0x8706'8504'8302'8100,
8038 0x8706'8504'8302'8100,
8039 0x8706'8504'8302'8100,
8040 0x8706'8504'8302'8100,
8041 /* unused */ 0,
8042 /* unused */ 0,
8043 /* unused */ 0,
8044 0x8706'8504'8302'8100},
8045 // expected_result_vd0_with_mask_int8
8046 {138, 138, 138, 128, /* unused */ 0, 0, 150, 150},
8047 // expected_result_vd0_with_mask_int16
8048 {0x8100, 0x8100, 0x8100, 0x8100, /* unused */ 0, 0x8100, 0x8100, 0x8100},
8049 // expected_result_vd0_with_mask_int32
8050 {0x8302'8100,
8051 0x8302'8100,
8052 0x8302'8100,
8053 0x8302'8100,
8054 /* unused */ 0,
8055 /* unused */ 0,
8056 0x8302'8100,
8057 0x8302'8100},
8058 // expected_result_vd0_with_mask_int64
8059 {0x8706'8504'8302'8100,
8060 0x8706'8504'8302'8100,
8061 0x8706'8504'8302'8100,
8062 0x8706'8504'8302'8100,
8063 /* unused */ 0,
8064 /* unused */ 0,
8065 /* unused */ 0,
8066 0x8706'8504'8302'8100},
8067 kVectorCalculationsSource);
8068 }
8069
TEST_F(Riscv64InterpreterTest,TestVfredmin)8070 TEST_F(Riscv64InterpreterTest, TestVfredmin) {
8071 TestVectorReductionInstruction(0x15881457, // vfredmin.vs v8, v24, v16, v0.t
8072 // expected_result_vd0_int32
8073 {0x9e0c'9a09,
8074 0xbe2c'ba29,
8075 0xfe6c'fa69,
8076 0xfe6c'fa69,
8077 /* unused */ 0,
8078 /* unused */ 0,
8079 0x9604'9200,
8080 0x9e0c'9a09},
8081 // expected_result_vd0_int64
8082 {0x9e0c'9a09'9604'9200,
8083 0xbe2c'ba29'b624'b220,
8084 0xfe6c'fa69'f664'f260,
8085 0xfe6c'fa69'f664'f260,
8086 /* unused */ 0,
8087 /* unused */ 0,
8088 /* unused */ 0,
8089 0x9e0c'9a09'9604'9200},
8090 // expected_result_vd0_with_mask_int32
8091 {0x9604'9200,
8092 0xbe2c'ba29,
8093 0xfe6c'fa69,
8094 0xfe6c'fa69,
8095 /* unused */ 0,
8096 /* unused */ 0,
8097 0x9604'9200,
8098 0x9604'9200},
8099 // expected_result_vd0_with_mask_int64
8100 {0x9e0c'9a09'9604'9200,
8101 0xbe2c'ba29'b624'b220,
8102 0xee7c'ea78'e674'e271,
8103 0xee7c'ea78'e674'e271,
8104 /* unused */ 0,
8105 /* unused */ 0,
8106 /* unused */ 0,
8107 0x9e0c'9a09'9604'9200},
8108 kVectorCalculationsSource);
8109 }
8110
TEST_F(Riscv64InterpreterTest,TestVredmaxu)8111 TEST_F(Riscv64InterpreterTest, TestVredmaxu) {
8112 TestVectorReductionInstruction(
8113 0x19882457, // vredmaxu.vs v8,v24,v16,v0.t
8114 // expected_result_vd0_int8
8115 {158, 190, 254, 254, /* unused */ 0, 146, 150, 158},
8116 // expected_result_vd0_int16
8117 {0x9e0c, 0xbe2c, 0xfe6c, 0xfe6c, /* unused */ 0, 0x9200, 0x9604, 0x9e0c},
8118 // expected_result_vd0_int32
8119 {0x9e0c'9a09,
8120 0xbe2c'ba29,
8121 0xfe6c'fa69,
8122 0xfe6c'fa69,
8123 /* unused */ 0,
8124 /* unused */ 0,
8125 0x9604'9200,
8126 0x9e0c'9a09},
8127 // expected_result_vd0_int64
8128 {0x9e0c'9a09'9604'9200,
8129 0xbe2c'ba29'b624'b220,
8130 0xfe6c'fa69'f664'f260,
8131 0xfe6c'fa69'f664'f260,
8132 /* unused */ 0,
8133 /* unused */ 0,
8134 /* unused */ 0,
8135 0x9e0c'9a09'9604'9200},
8136 // expected_result_vd0_with_mask_int8
8137 {158, 186, 254, 254, /* unused */ 0, 0, 150, 158},
8138 // expected_result_vd0_with_mask_int16
8139 {0x9e0c, 0xba29, 0xfe6c, 0xfe6c, /* unused */ 0, 0x9200, 0x9200, 0x9e0c},
8140 // expected_result_vd0_with_mask_int32
8141 {0x9604'9200,
8142 0xbe2c'ba29,
8143 0xfe6c'fa69,
8144 0xfe6c'fa69,
8145 /* unused */ 0,
8146 /* unused */ 0,
8147 0x9604'9200,
8148 0x9604'9200},
8149 // expected_result_vd0_with_mask_int64
8150 {0x9e0c'9a09'9604'9200,
8151 0xbe2c'ba29'b624'b220,
8152 0xee7c'ea78'e674'e271,
8153 0xee7c'ea78'e674'e271,
8154 /* unused */ 0,
8155 /* unused */ 0,
8156 /* unused */ 0,
8157 0x9e0c'9a09'9604'9200},
8158 kVectorCalculationsSource);
8159 }
8160
TEST_F(Riscv64InterpreterTest,TestVredmax)8161 TEST_F(Riscv64InterpreterTest, TestVredmax) {
8162 TestVectorReductionInstruction(
8163 0x1d882457, // vredmax.vs v8,v24,v16,v0.t
8164 // expected_result_vd0_int8
8165 {28, 60, 124, 126, /* unused */ 0, 0, 4, 12},
8166 // expected_result_vd0_int16
8167 {0x9e0c, 0xbe2c, 0xfe6c, 0x7eec, /* unused */ 0, 0x9200, 0x9604, 0x9e0c},
8168 // expected_result_vd0_int32
8169 {0x9e0c'9a09,
8170 0xbe2c'ba29,
8171 0xfe6c'fa69,
8172 0x7eec'7ae9,
8173 /* unused */ 0,
8174 /* unused */ 0,
8175 0x9604'9200,
8176 0x9e0c'9a09},
8177 // expected_result_vd0_int64
8178 {0x9e0c'9a09'9604'9200,
8179 0xbe2c'ba29'b624'b220,
8180 0xfe6c'fa69'f664'f260,
8181 0x7eec'7ae9'76e4'72e0,
8182 /* unused */ 0,
8183 /* unused */ 0,
8184 /* unused */ 0,
8185 0x9e0c'9a09'9604'9200},
8186 // expected_result_vd0_with_mask_int8
8187 {24, 52, 124, 126, /* unused */ 0, 0, 4, 4},
8188 // expected_result_vd0_with_mask_int16
8189 {0x9e0c, 0xba29, 0xfe6c, 0x7ae9, /* unused */ 0, 0x9200, 0x9200, 0x9e0c},
8190 // expected_result_vd0_with_mask_int32
8191 {0x9604'9200,
8192 0xbe2c'ba29,
8193 0xfe6c'fa69,
8194 0x7eec'7ae9,
8195 /* unused */ 0,
8196 /* unused */ 0,
8197 0x9604'9200,
8198 0x9604'9200},
8199 // expected_result_vd0_with_mask_int64
8200 {0x9e0c'9a09'9604'9200,
8201 0xbe2c'ba29'b624'b220,
8202 0xee7c'ea78'e674'e271,
8203 0x6efc'6af8'66f4'62f1,
8204 /* unused */ 0,
8205 /* unused */ 0,
8206 /* unused */ 0,
8207 0x9e0c'9a09'9604'9200},
8208 kVectorCalculationsSource);
8209 }
8210
TEST_F(Riscv64InterpreterTest,TestVfredmax)8211 TEST_F(Riscv64InterpreterTest, TestVfredmax) {
8212 TestVectorReductionInstruction(0x1d881457, // vfredmax.vs v8, v24, v16, v0.t
8213 // expected_result_vd0_int32
8214 {0x8302'8100,
8215 0x8302'8100,
8216 0x8302'8100,
8217 0x7eec'7ae9,
8218 /* unused */ 0,
8219 /* unused */ 0,
8220 0x8302'8100,
8221 0x8302'8100},
8222 // expected_result_vd0_int64
8223 {0x8706'8504'8302'8100,
8224 0x8706'8504'8302'8100,
8225 0x8706'8504'8302'8100,
8226 0x7eec'7ae9'76e4'72e0,
8227 /* unused */ 0,
8228 /* unused */ 0,
8229 /* unused */ 0,
8230 0x8706'8504'8302'8100},
8231 // expected_result_vd0_with_mask_int32
8232 {0x8302'8100,
8233 0x8302'8100,
8234 0x8302'8100,
8235 0x7eec'7ae9,
8236 /* unused */ 0,
8237 /* unused */ 0,
8238 0x8302'8100,
8239 0x8302'8100},
8240 // expected_result_vd0_with_mask_int64
8241 {0x8706'8504'8302'8100,
8242 0x8706'8504'8302'8100,
8243 0x8706'8504'8302'8100,
8244 0x6efc'6af8'66f4'62f1,
8245 /* unused */ 0,
8246 /* unused */ 0,
8247 /* unused */ 0,
8248 0x8706'8504'8302'8100},
8249 kVectorCalculationsSource);
8250 }
8251
8252 // Note that the expected test outputs for v[f]merge.vXm are identical to those for v[f]mv.v.X.
8253 // This happens because v[f]merge.vXm is just a v[f]mv.v.X with mask (second operand is not used
8254 // by v[f]mv.v.X but the difference between v[f]merge.vXm and v[f]mv.v.X is captured in masking
8255 // logic within TestVectorInstruction itself via the parameter TestVectorInstructionMode::kVMerge
8256 // for V[f]merge/V[f]mv).
TEST_F(Riscv64InterpreterTest,TestVmerge)8257 TEST_F(Riscv64InterpreterTest, TestVmerge) {
8258 TestVectorMergeFloatInstruction(0x5d00d457, // Vfmerge.vfm v8, v16, f1, v0
8259 {{0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
8260 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
8261 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
8262 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
8263 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
8264 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
8265 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000},
8266 {0x40b4'0000, 0x40b4'0000, 0x40b4'0000, 0x40b4'0000}},
8267 {{0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
8268 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
8269 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
8270 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
8271 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
8272 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
8273 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000},
8274 {0x4016'8000'0000'0000, 0x4016'8000'0000'0000}},
8275 kVectorCalculationsSource);
8276 TestVectorMergeInstruction(
8277 0x5d0c0457, // Vmerge.vvm v8, v16, v24, v0
8278 {{0, 146, 4, 150, 9, 154, 12, 158, 17, 130, 20, 134, 24, 138, 28, 142},
8279 {32, 178, 36, 182, 41, 186, 44, 190, 49, 162, 52, 166, 56, 170, 60, 174},
8280 {64, 210, 68, 214, 73, 218, 76, 222, 81, 194, 84, 198, 88, 202, 92, 206},
8281 {96, 242, 100, 246, 105, 250, 108, 254, 113, 226, 116, 230, 120, 234, 124, 238},
8282 {128, 18, 132, 22, 137, 26, 140, 30, 145, 2, 148, 6, 152, 10, 156, 14},
8283 {160, 50, 164, 54, 169, 58, 172, 62, 177, 34, 180, 38, 184, 42, 188, 46},
8284 {192, 82, 196, 86, 201, 90, 204, 94, 209, 66, 212, 70, 216, 74, 220, 78},
8285 {224, 114, 228, 118, 233, 122, 236, 126, 241, 98, 244, 102, 248, 106, 252, 110}},
8286 {{0x9200, 0x9604, 0x9a09, 0x9e0c, 0x8211, 0x8614, 0x8a18, 0x8e1c},
8287 {0xb220, 0xb624, 0xba29, 0xbe2c, 0xa231, 0xa634, 0xaa38, 0xae3c},
8288 {0xd240, 0xd644, 0xda49, 0xde4c, 0xc251, 0xc654, 0xca58, 0xce5c},
8289 {0xf260, 0xf664, 0xfa69, 0xfe6c, 0xe271, 0xe674, 0xea78, 0xee7c},
8290 {0x1280, 0x1684, 0x1a89, 0x1e8c, 0x0291, 0x0694, 0x0a98, 0x0e9c},
8291 {0x32a0, 0x36a4, 0x3aa9, 0x3eac, 0x22b1, 0x26b4, 0x2ab8, 0x2ebc},
8292 {0x52c0, 0x56c4, 0x5ac9, 0x5ecc, 0x42d1, 0x46d4, 0x4ad8, 0x4edc},
8293 {0x72e0, 0x76e4, 0x7ae9, 0x7eec, 0x62f1, 0x66f4, 0x6af8, 0x6efc}},
8294 {{0x9604'9200, 0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18},
8295 {0xb624'b220, 0xbe2c'ba29, 0xa634'a231, 0xae3c'aa38},
8296 {0xd644'd240, 0xde4c'da49, 0xc654'c251, 0xce5c'ca58},
8297 {0xf664'f260, 0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78},
8298 {0x1684'1280, 0x1e8c'1a89, 0x0694'0291, 0x0e9c'0a98},
8299 {0x36a4'32a0, 0x3eac'3aa9, 0x26b4'22b1, 0x2ebc'2ab8},
8300 {0x56c4'52c0, 0x5ecc'5ac9, 0x46d4'42d1, 0x4edc'4ad8},
8301 {0x76e4'72e0, 0x7eec'7ae9, 0x66f4'62f1, 0x6efc'6af8}},
8302 {{0x9e0c'9a09'9604'9200, 0x8e1c'8a18'8614'8211},
8303 {0xbe2c'ba29'b624'b220, 0xae3c'aa38'a634'a231},
8304 {0xde4c'da49'd644'd240, 0xce5c'ca58'c654'c251},
8305 {0xfe6c'fa69'f664'f260, 0xee7c'ea78'e674'e271},
8306 {0x1e8c'1a89'1684'1280, 0x0e9c'0a98'0694'0291},
8307 {0x3eac'3aa9'36a4'32a0, 0x2ebc'2ab8'26b4'22b1},
8308 {0x5ecc'5ac9'56c4'52c0, 0x4edc'4ad8'46d4'42d1},
8309 {0x7eec'7ae9'76e4'72e0, 0x6efc'6af8'66f4'62f1}},
8310 kVectorCalculationsSource);
8311 TestVectorMergeInstruction(
8312 0x5d00c457, // Vmerge.vxm v8, v16, x1, v0
8313 {{170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
8314 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
8315 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
8316 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
8317 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
8318 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
8319 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170},
8320 {170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, 170}},
8321 {{0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
8322 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
8323 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
8324 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
8325 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
8326 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
8327 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa},
8328 {0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa}},
8329 {{0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
8330 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
8331 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
8332 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
8333 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
8334 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
8335 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa},
8336 {0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa, 0xaaaa'aaaa}},
8337 {{0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
8338 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
8339 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
8340 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
8341 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
8342 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
8343 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa},
8344 {0xaaaa'aaaa'aaaa'aaaa, 0xaaaa'aaaa'aaaa'aaaa}},
8345 kVectorCalculationsSource);
8346 TestVectorMergeInstruction(
8347 0x5d0ab457, // Vmerge.vim v8, v16, -0xb, v0
8348 {{245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
8349 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
8350 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
8351 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
8352 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
8353 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
8354 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245},
8355 {245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245, 245}},
8356 {{0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
8357 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
8358 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
8359 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
8360 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
8361 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
8362 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5},
8363 {0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5, 0xfff5}},
8364 {{0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
8365 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
8366 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
8367 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
8368 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
8369 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
8370 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5},
8371 {0xffff'fff5, 0xffff'fff5, 0xffff'fff5, 0xffff'fff5}},
8372 {{0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
8373 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
8374 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
8375 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
8376 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
8377 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
8378 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5},
8379 {0xffff'ffff'ffff'fff5, 0xffff'ffff'ffff'fff5}},
8380 kVectorCalculationsSource);
8381 }
8382
TEST_F(Riscv64InterpreterTest,TestVslide1down)8383 TEST_F(Riscv64InterpreterTest, TestVslide1down) {
8384 // Where the element at the top gets inserted will depend on VLMUL so we use
8385 // TestVectorPermutationInstruction instead of TestVectorInstruction.
8386
8387 // VLMUL = 0
8388 TestVectorPermutationInstruction(
8389 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8390 {{2, 4, 6, 9, 10, 12, 14, 17, 18, 20, 22, 24, 26, 28, 30, 0xaa}, {}, {}, {}, {}, {}, {}, {}},
8391 {{0x0604, 0x0a09, 0x0e0c, 0x1211, 0x1614, 0x1a18, 0x1e1c, 0xaaaa},
8392 {},
8393 {},
8394 {},
8395 {},
8396 {},
8397 {},
8398 {}},
8399 {{0x0e0c'0a09, 0x1614'1211, 0x1e1c'1a18, 0xaaaa'aaaa}, {}, {}, {}, {}, {}, {}, {}},
8400 {{0x1e1c'1a18'1614'1211, 0xaaaa'aaaa'aaaa'aaaa}, {}, {}, {}, {}, {}, {}, {}},
8401 kVectorCalculationsSourceLegacy,
8402 /*vlmul=*/0,
8403 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8404 /*skip=*/0,
8405 /*ignore_vma_for_last=*/true,
8406 /*last_elem_is_x1=*/true);
8407
8408 // VLMUL = 1
8409 TestVectorPermutationInstruction(
8410 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8411 {{2, 4, 6, 9, 10, 12, 14, 17, 18, 20, 22, 24, 26, 28, 30, 32},
8412 {34, 36, 38, 41, 42, 44, 46, 49, 50, 52, 54, 56, 58, 60, 62, 0xaa},
8413 {},
8414 {},
8415 {},
8416 {},
8417 {},
8418 {}},
8419 {{0x0604, 0x0a09, 0x0e0c, 0x1211, 0x1614, 0x1a18, 0x1e1c, 0x2220},
8420 {0x2624, 0x2a29, 0x2e2c, 0x3231, 0x3634, 0x3a38, 0x3e3c, 0xaaaa},
8421 {},
8422 {},
8423 {},
8424 {},
8425 {},
8426 {}},
8427 {{0x0e0c'0a09, 0x1614'1211, 0x1e1c'1a18, 0x2624'2220},
8428 {0x2e2c'2a29, 0x3634'3231, 0x3e3c'3a38, 0xaaaa'aaaa},
8429 {},
8430 {},
8431 {},
8432 {},
8433 {},
8434 {}},
8435 {{0x1e1c'1a18'1614'1211, 0x2e2c'2a29'2624'2220},
8436 {0x3e3c'3a38'3634'3231, 0xaaaa'aaaa'aaaa'aaaa},
8437 {},
8438 {},
8439 {},
8440 {},
8441 {},
8442 {}},
8443 kVectorCalculationsSourceLegacy,
8444 /*vlmul=*/1,
8445 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8446 /*skip=*/0,
8447 /*ignore_vma_for_last=*/true,
8448 /*last_elem_is_x1=*/true);
8449
8450 // VLMUL = 2
8451 TestVectorPermutationInstruction(
8452 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8453 {{2, 4, 6, 9, 10, 12, 14, 17, 18, 20, 22, 24, 26, 28, 30, 32},
8454 {34, 36, 38, 41, 42, 44, 46, 49, 50, 52, 54, 56, 58, 60, 62, 64},
8455 {66, 68, 70, 73, 74, 76, 78, 81, 82, 84, 86, 88, 90, 92, 94, 96},
8456 {98, 100, 102, 105, 106, 108, 110, 113, 114, 116, 118, 120, 122, 124, 126, 0xaa},
8457 {},
8458 {},
8459 {},
8460 {}},
8461 {{0x0604, 0x0a09, 0x0e0c, 0x1211, 0x1614, 0x1a18, 0x1e1c, 0x2220},
8462 {0x2624, 0x2a29, 0x2e2c, 0x3231, 0x3634, 0x3a38, 0x3e3c, 0x4240},
8463 {0x4644, 0x4a49, 0x4e4c, 0x5251, 0x5654, 0x5a58, 0x5e5c, 0x6260},
8464 {0x6664, 0x6a69, 0x6e6c, 0x7271, 0x7674, 0x7a78, 0x7e7c, 0xaaaa},
8465 {},
8466 {},
8467 {},
8468 {}},
8469 {{0x0e0c'0a09, 0x1614'1211, 0x1e1c'1a18, 0x2624'2220},
8470 {0x2e2c'2a29, 0x3634'3231, 0x3e3c'3a38, 0x4644'4240},
8471 {0x4e4c'4a49, 0x5654'5251, 0x5e5c'5a58, 0x6664'6260},
8472 {0x6e6c'6a69, 0x7674'7271, 0x7e7c'7a78, 0xaaaa'aaaa},
8473 {},
8474 {},
8475 {},
8476 {}},
8477 {{0x1e1c'1a18'1614'1211, 0x2e2c'2a29'2624'2220},
8478 {0x3e3c'3a38'3634'3231, 0x4e4c'4a49'4644'4240},
8479 {0x5e5c'5a58'5654'5251, 0x6e6c'6a69'6664'6260},
8480 {0x7e7c'7a78'7674'7271, 0xaaaa'aaaa'aaaa'aaaa},
8481 {},
8482 {},
8483 {},
8484 {}},
8485 kVectorCalculationsSourceLegacy,
8486 /*vlmul=*/2,
8487 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8488 /*skip=*/0,
8489 /*ignore_vma_for_last=*/true,
8490 /*last_elem_is_x1=*/true);
8491
8492 // VLMUL = 3
8493 TestVectorPermutationInstruction(
8494 0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8495 {{2, 4, 6, 9, 10, 12, 14, 17, 18, 20, 22, 24, 26, 28, 30, 32},
8496 {34, 36, 38, 41, 42, 44, 46, 49, 50, 52, 54, 56, 58, 60, 62, 64},
8497 {66, 68, 70, 73, 74, 76, 78, 81, 82, 84, 86, 88, 90, 92, 94, 96},
8498 {98, 100, 102, 105, 106, 108, 110, 113, 114, 116, 118, 120, 122, 124, 126, 128},
8499 {130, 132, 134, 137, 138, 140, 142, 145, 146, 148, 150, 152, 154, 156, 158, 160},
8500 {162, 164, 166, 169, 170, 172, 174, 177, 178, 180, 182, 184, 186, 188, 190, 192},
8501 {194, 196, 198, 201, 202, 204, 206, 209, 210, 212, 214, 216, 218, 220, 222, 224},
8502 {226, 228, 230, 233, 234, 236, 238, 241, 242, 244, 246, 248, 250, 252, 254, 0xaa}},
8503 {{0x0604, 0x0a09, 0x0e0c, 0x1211, 0x1614, 0x1a18, 0x1e1c, 0x2220},
8504 {0x2624, 0x2a29, 0x2e2c, 0x3231, 0x3634, 0x3a38, 0x3e3c, 0x4240},
8505 {0x4644, 0x4a49, 0x4e4c, 0x5251, 0x5654, 0x5a58, 0x5e5c, 0x6260},
8506 {0x6664, 0x6a69, 0x6e6c, 0x7271, 0x7674, 0x7a78, 0x7e7c, 0x8280},
8507 {0x8684, 0x8a89, 0x8e8c, 0x9291, 0x9694, 0x9a98, 0x9e9c, 0xa2a0},
8508 {0xa6a4, 0xaaa9, 0xaeac, 0xb2b1, 0xb6b4, 0xbab8, 0xbebc, 0xc2c0},
8509 {0xc6c4, 0xcac9, 0xcecc, 0xd2d1, 0xd6d4, 0xdad8, 0xdedc, 0xe2e0},
8510 {0xe6e4, 0xeae9, 0xeeec, 0xf2f1, 0xf6f4, 0xfaf8, 0xfefc, 0xaaaa}},
8511 {{0x0e0c'0a09, 0x1614'1211, 0x1e1c'1a18, 0x2624'2220},
8512 {0x2e2c'2a29, 0x3634'3231, 0x3e3c'3a38, 0x4644'4240},
8513 {0x4e4c'4a49, 0x5654'5251, 0x5e5c'5a58, 0x6664'6260},
8514 {0x6e6c'6a69, 0x7674'7271, 0x7e7c'7a78, 0x8684'8280},
8515 {0x8e8c'8a89, 0x9694'9291, 0x9e9c'9a98, 0xa6a4'a2a0},
8516 {0xaeac'aaa9, 0xb6b4'b2b1, 0xbebc'bab8, 0xc6c4'c2c0},
8517 {0xcecc'cac9, 0xd6d4'd2d1, 0xdedc'dad8, 0xe6e4'e2e0},
8518 {0xeeec'eae9, 0xf6f4'f2f1, 0xfefc'faf8, 0xaaaa'aaaa}},
8519 {{0x1e1c'1a18'1614'1211, 0x2e2c'2a29'2624'2220},
8520 {0x3e3c'3a38'3634'3231, 0x4e4c'4a49'4644'4240},
8521 {0x5e5c'5a58'5654'5251, 0x6e6c'6a69'6664'6260},
8522 {0x7e7c'7a78'7674'7271, 0x8e8c'8a89'8684'8280},
8523 {0x9e9c'9a98'9694'9291, 0xaeac'aaa9'a6a4'a2a0},
8524 {0xbebc'bab8'b6b4'b2b1, 0xcecc'cac9'c6c4'c2c0},
8525 {0xdedc'dad8'd6d4'd2d1, 0xeeec'eae9'e6e4'e2e0},
8526 {0xfefc'faf8'f6f4'f2f1, 0xaaaa'aaaa'aaaa'aaaa}},
8527 kVectorCalculationsSourceLegacy,
8528 /*vlmul=*/3,
8529 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8530 /*skip=*/0,
8531 /*ignore_vma_for_last=*/true,
8532 /*last_elem_is_x1=*/true);
8533
8534 // VLMUL = 4
8535 TestVectorPermutationInstruction(0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8536 {{}, {}, {}, {}, {}, {}, {}, {}},
8537 {{}, {}, {}, {}, {}, {}, {}, {}},
8538 {{}, {}, {}, {}, {}, {}, {}, {}},
8539 {{}, {}, {}, {}, {}, {}, {}, {}},
8540 kVectorCalculationsSourceLegacy,
8541 /*vlmul=*/4,
8542 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8543 /*skip=*/0,
8544 /*ignore_vma_for_last=*/true,
8545 /*last_elem_is_x1=*/true);
8546
8547 // VLMUL = 5
8548 TestVectorPermutationInstruction(0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8549 {{2, 0xaa}, {}, {}, {}, {}, {}, {}, {}},
8550 {{0xaaaa}, {}, {}, {}, {}, {}, {}, {}},
8551 {{}, {}, {}, {}, {}, {}, {}, {}},
8552 {{}, {}, {}, {}, {}, {}, {}, {}},
8553 kVectorCalculationsSourceLegacy,
8554 /*vlmul=*/5,
8555 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8556 /*skip=*/0,
8557 /*ignore_vma_for_last=*/true,
8558 /*last_elem_is_x1=*/true);
8559
8560 // VLMUL = 6
8561 TestVectorPermutationInstruction(0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8562 {{2, 4, 6, 0xaa}, {}, {}, {}, {}, {}, {}, {}},
8563 {{0x0604, 0xaaaa}, {}, {}, {}, {}, {}, {}, {}},
8564 {{0xaaaa'aaaa}, {}, {}, {}, {}, {}, {}, {}},
8565 {{}, {}, {}, {}, {}, {}, {}, {}},
8566 kVectorCalculationsSourceLegacy,
8567 /*vlmul=*/6,
8568 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8569 /*skip=*/0,
8570 /*ignore_vma_for_last=*/true,
8571 /*last_elem_is_x1=*/true);
8572
8573 // VLMUL = 7
8574 TestVectorPermutationInstruction(0x3d80e457, // vslide1down.vx v8, v24, x1, v0.t
8575 {{2, 4, 6, 9, 10, 12, 14, 0xaa}, {}, {}, {}, {}, {}, {}, {}},
8576 {{0x0604, 0x0a09, 0x0e0c, 0xaaaa}, {}, {}, {}, {}, {}, {}, {}},
8577 {{0x0e0c'0a09, 0xaaaa'aaaa}, {}, {}, {}, {}, {}, {}, {}},
8578 {{0xaaaa'aaaa'aaaa'aaaa}, {}, {}, {}, {}, {}, {}, {}},
8579 kVectorCalculationsSourceLegacy,
8580 /*vlmul=*/7,
8581 /*regx1=*/0xaaaa'aaaa'aaaa'aaaa,
8582 /*skip=*/0,
8583 /*ignore_vma_for_last=*/true,
8584 /*last_elem_is_x1=*/true);
8585 }
8586
TEST_F(Riscv64InterpreterTest,TestVfslide1up)8587 TEST_F(Riscv64InterpreterTest, TestVfslide1up) {
8588 TestVectorFloatInstruction(0x3980d457, // vfslide1up.vf v8, v24, f1, v0.t
8589 {{0x40b4'0000, 0x9604'9200, 0x9e0c'9a09, 0x8614'8211},
8590 {0x8e1c'8a18, 0xb624'b220, 0xbe2c'ba29, 0xa634'a231},
8591 {0xae3c'aa38, 0xd644'd240, 0xde4c'da49, 0xc654'c251},
8592 {0xce5c'ca58, 0xf664'f260, 0xfe6c'fa69, 0xe674'e271},
8593 {0xee7c'ea78, 0x1684'1280, 0x1e8c'1a89, 0x0694'0291},
8594 {0x0e9c'0a98, 0x36a4'32a0, 0x3eac'3aa9, 0x26b4'22b1},
8595 {0x2ebc'2ab8, 0x56c4'52c0, 0x5ecc'5ac9, 0x46d4'42d1},
8596 {0x4edc'4ad8, 0x76e4'72e0, 0x7eec'7ae9, 0x66f4'62f1}},
8597 {{0x4016'8000'0000'0000, 0x9e0c'9a09'9604'9200},
8598 {0x8e1c'8a18'8614'8211, 0xbe2c'ba29'b624'b220},
8599 {0xae3c'aa38'a634'a231, 0xde4c'da49'd644'd240},
8600 {0xce5c'ca58'c654'c251, 0xfe6c'fa69'f664'f260},
8601 {0xee7c'ea78'e674'e271, 0x1e8c'1a89'1684'1280},
8602 {0x0e9c'0a98'0694'0291, 0x3eac'3aa9'36a4'32a0},
8603 {0x2ebc'2ab8'26b4'22b1, 0x5ecc'5ac9'56c4'52c0},
8604 {0x4edc'4ad8'46d4'42d1, 0x7eec'7ae9'76e4'72e0}},
8605 kVectorCalculationsSource);
8606 }
8607
TEST_F(Riscv64InterpreterTest,TestVfslide1down)8608 TEST_F(Riscv64InterpreterTest, TestVfslide1down) {
8609 // Where the element at the top gets inserted will depend on VLMUL so we use
8610 // TestVectorFloatPermutationInstruction instead of TestVectorFloatInstruction.
8611
8612 // VLMUL = 0
8613 TestVectorFloatPermutationInstruction(
8614 0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8615 {{0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18, 0x40b4'0000}, {}, {}, {}, {}, {}, {}, {}},
8616 {{0x8e1c'8a18'8614'8211, 0x4016'8000'0000'0000}, {}, {}, {}, {}, {}, {}, {}},
8617 kVectorCalculationsSource,
8618 /*vlmul=*/0,
8619 /*skip=*/0,
8620 /*ignore_vma_for_last=*/true,
8621 /*last_elem_is_f1=*/true);
8622
8623 // VLMUL = 1
8624 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8625 {{0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18, 0xb624'b220},
8626 {0xbe2c'ba29, 0xa634'a231, 0xae3c'aa38, 0x40b4'0000},
8627 {},
8628 {},
8629 {},
8630 {},
8631 {},
8632 {}},
8633 {{0x8e1c'8a18'8614'8211, 0xbe2c'ba29'b624'b220},
8634 {0xae3c'aa38'a634'a231, 0x4016'8000'0000'0000},
8635 {},
8636 {},
8637 {},
8638 {},
8639 {},
8640 {}},
8641 kVectorCalculationsSource,
8642 /*vlmul=*/1,
8643 /*skip=*/0,
8644 /*ignore_vma_for_last=*/true,
8645 /*last_elem_is_f1=*/true);
8646
8647 // VLMUL = 2
8648 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8649 {{0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18, 0xb624'b220},
8650 {0xbe2c'ba29, 0xa634'a231, 0xae3c'aa38, 0xd644'd240},
8651 {0xde4c'da49, 0xc654'c251, 0xce5c'ca58, 0xf664'f260},
8652 {0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78, 0x40b4'0000},
8653 {},
8654 {},
8655 {},
8656 {}},
8657 {{0x8e1c'8a18'8614'8211, 0xbe2c'ba29'b624'b220},
8658 {0xae3c'aa38'a634'a231, 0xde4c'da49'd644'd240},
8659 {0xce5c'ca58'c654'c251, 0xfe6c'fa69'f664'f260},
8660 {0xee7c'ea78'e674'e271, 0x4016'8000'0000'0000},
8661 {},
8662 {},
8663 {},
8664 {}},
8665 kVectorCalculationsSource,
8666 /*vlmul=*/2,
8667 /*skip=*/0,
8668 /*ignore_vma_for_last=*/true,
8669 /*last_elem_is_f1=*/true);
8670
8671 // VLMUL = 3
8672 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8673 {{0x9e0c'9a09, 0x8614'8211, 0x8e1c'8a18, 0xb624'b220},
8674 {0xbe2c'ba29, 0xa634'a231, 0xae3c'aa38, 0xd644'd240},
8675 {0xde4c'da49, 0xc654'c251, 0xce5c'ca58, 0xf664'f260},
8676 {0xfe6c'fa69, 0xe674'e271, 0xee7c'ea78, 0x1684'1280},
8677 {0x1e8c'1a89, 0x0694'0291, 0x0e9c'0a98, 0x36a4'32a0},
8678 {0x3eac'3aa9, 0x26b4'22b1, 0x2ebc'2ab8, 0x56c4'52c0},
8679 {0x5ecc'5ac9, 0x46d4'42d1, 0x4edc'4ad8, 0x76e4'72e0},
8680 {0x7eec'7ae9, 0x66f4'62f1, 0x6efc'6af8, 0x40b4'0000}},
8681 {{0x8e1c'8a18'8614'8211, 0xbe2c'ba29'b624'b220},
8682 {0xae3c'aa38'a634'a231, 0xde4c'da49'd644'd240},
8683 {0xce5c'ca58'c654'c251, 0xfe6c'fa69'f664'f260},
8684 {0xee7c'ea78'e674'e271, 0x1e8c'1a89'1684'1280},
8685 {0x0e9c'0a98'0694'0291, 0x3eac'3aa9'36a4'32a0},
8686 {0x2ebc'2ab8'26b4'22b1, 0x5ecc'5ac9'56c4'52c0},
8687 {0x4edc'4ad8'46d4'42d1, 0x7eec'7ae9'76e4'72e0},
8688 {0x6efc'6af8'66f4'62f1, 0x4016'8000'0000'0000}},
8689 kVectorCalculationsSource,
8690 /*vlmul=*/3,
8691 /*skip=*/0,
8692 /*ignore_vma_for_last=*/true,
8693 /*last_elem_is_f1=*/true);
8694
8695 // VLMUL = 4
8696 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8697 {{}, {}, {}, {}, {}, {}, {}, {}},
8698 {{}, {}, {}, {}, {}, {}, {}, {}},
8699 kVectorCalculationsSource,
8700 /*vlmul=*/4,
8701 /*skip=*/0,
8702 /*ignore_vma_for_last=*/true,
8703 /*last_elem_is_f1=*/true);
8704
8705 // VLMUL = 5
8706 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8707 {{}, {}, {}, {}, {}, {}, {}, {}},
8708 {{}, {}, {}, {}, {}, {}, {}, {}},
8709 kVectorCalculationsSource,
8710 /*vlmul=*/5,
8711 /*skip=*/0,
8712 /*ignore_vma_for_last=*/true,
8713 /*last_elem_is_f1=*/true);
8714
8715 // VLMUL = 6
8716 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8717 {{0x40b4'0000}, {}, {}, {}, {}, {}, {}, {}},
8718 {{}, {}, {}, {}, {}, {}, {}, {}},
8719 kVectorCalculationsSource,
8720 /*vlmul=*/6,
8721 /*skip=*/0,
8722 /*ignore_vma_for_last=*/true,
8723 /*last_elem_is_f1=*/true);
8724
8725 // VLMUL = 7
8726 TestVectorFloatPermutationInstruction(0x3d80d457, // vfslide1down.vf v8, v24, f1, v0.t
8727 {{0x9e0c'9a09, 0x40b4'0000}, {}, {}, {}, {}, {}, {}, {}},
8728 {{0x4016'8000'0000'0000}, {}, {}, {}, {}, {}, {}, {}},
8729 kVectorCalculationsSource,
8730 /*vlmul=*/7,
8731 /*skip=*/0,
8732 /*ignore_vma_for_last=*/true,
8733 /*last_elem_is_f1=*/true);
8734 }
8735
TEST_F(Riscv64InterpreterTest,TestVseXX)8736 TEST_F(Riscv64InterpreterTest, TestVseXX) {
8737 TestVseXX(0x8427, // vse8.v v8, (x1), v0.t
8738 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
8739 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159},
8740 {32, 161, 34, 163, 36, 165, 38, 167, 40, 169, 42, 171, 44, 173, 46, 175},
8741 {48, 177, 50, 179, 52, 181, 54, 183, 56, 185, 58, 187, 60, 189, 62, 191},
8742 {64, 193, 66, 195, 68, 197, 70, 199, 72, 201, 74, 203, 76, 205, 78, 207},
8743 {80, 209, 82, 211, 84, 213, 86, 215, 88, 217, 90, 219, 92, 221, 94, 223},
8744 {96, 225, 98, 227, 100, 229, 102, 231, 104, 233, 106, 235, 108, 237, 110, 239},
8745 {112, 241, 114, 243, 116, 245, 118, 247, 120, 249, 122, 251, 124, 253, 126, 255}},
8746 {},
8747 {},
8748 {},
8749 0,
8750 kVectorCalculationsSourceLegacy);
8751 TestVseXX(0xd427, // vse16.v v8, (x1), v0.t
8752 {},
8753 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
8754 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e},
8755 {0xa120, 0xa322, 0xa524, 0xa726, 0xa928, 0xab2a, 0xad2c, 0xaf2e},
8756 {0xb130, 0xb332, 0xb534, 0xb736, 0xb938, 0xbb3a, 0xbd3c, 0xbf3e},
8757 {0xc140, 0xc342, 0xc544, 0xc746, 0xc948, 0xcb4a, 0xcd4c, 0xcf4e},
8758 {0xd150, 0xd352, 0xd554, 0xd756, 0xd958, 0xdb5a, 0xdd5c, 0xdf5e},
8759 {0xe160, 0xe362, 0xe564, 0xe766, 0xe968, 0xeb6a, 0xed6c, 0xef6e},
8760 {0xf170, 0xf372, 0xf574, 0xf776, 0xf978, 0xfb7a, 0xfd7c, 0xff7e}},
8761 {},
8762 {},
8763 1,
8764 kVectorCalculationsSourceLegacy);
8765 TestVseXX(0xe427, // vse32.v v8, (x1), v0.t
8766 {},
8767 {},
8768 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
8769 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
8770 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
8771 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
8772 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
8773 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
8774 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
8775 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
8776 {},
8777 2,
8778 kVectorCalculationsSourceLegacy);
8779 TestVseXX(0xf427, // vse64.v v8, (x1), v0.t
8780 {},
8781 {},
8782 {},
8783 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
8784 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
8785 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
8786 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
8787 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
8788 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
8789 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
8790 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
8791 3,
8792 kVectorCalculationsSourceLegacy);
8793 }
8794
TEST_F(Riscv64InterpreterTest,TestVleXX)8795 TEST_F(Riscv64InterpreterTest, TestVleXX) {
8796 TestVleXX(0x8407, // vle8.v v8, (x1), v0.t
8797 {{0, 129, 2, 131, 4, 133, 6, 135, 8, 137, 10, 139, 12, 141, 14, 143},
8798 {16, 145, 18, 147, 20, 149, 22, 151, 24, 153, 26, 155, 28, 157, 30, 159},
8799 {32, 161, 34, 163, 36, 165, 38, 167, 40, 169, 42, 171, 44, 173, 46, 175},
8800 {48, 177, 50, 179, 52, 181, 54, 183, 56, 185, 58, 187, 60, 189, 62, 191},
8801 {64, 193, 66, 195, 68, 197, 70, 199, 72, 201, 74, 203, 76, 205, 78, 207},
8802 {80, 209, 82, 211, 84, 213, 86, 215, 88, 217, 90, 219, 92, 221, 94, 223},
8803 {96, 225, 98, 227, 100, 229, 102, 231, 104, 233, 106, 235, 108, 237, 110, 239},
8804 {112, 241, 114, 243, 116, 245, 118, 247, 120, 249, 122, 251, 124, 253, 126, 255}},
8805 {},
8806 {},
8807 {},
8808 0,
8809 kVectorCalculationsSourceLegacy);
8810 TestVleXX(0xd407, // vle16.v v8, (x1), v0.t
8811 {},
8812 {{0x8100, 0x8302, 0x8504, 0x8706, 0x8908, 0x8b0a, 0x8d0c, 0x8f0e},
8813 {0x9110, 0x9312, 0x9514, 0x9716, 0x9918, 0x9b1a, 0x9d1c, 0x9f1e},
8814 {0xa120, 0xa322, 0xa524, 0xa726, 0xa928, 0xab2a, 0xad2c, 0xaf2e},
8815 {0xb130, 0xb332, 0xb534, 0xb736, 0xb938, 0xbb3a, 0xbd3c, 0xbf3e},
8816 {0xc140, 0xc342, 0xc544, 0xc746, 0xc948, 0xcb4a, 0xcd4c, 0xcf4e},
8817 {0xd150, 0xd352, 0xd554, 0xd756, 0xd958, 0xdb5a, 0xdd5c, 0xdf5e},
8818 {0xe160, 0xe362, 0xe564, 0xe766, 0xe968, 0xeb6a, 0xed6c, 0xef6e},
8819 {0xf170, 0xf372, 0xf574, 0xf776, 0xf978, 0xfb7a, 0xfd7c, 0xff7e}},
8820 {},
8821 {},
8822 1,
8823 kVectorCalculationsSourceLegacy);
8824 TestVleXX(0xe407, // vle32.v v8, (x1), v0.t
8825 {},
8826 {},
8827 {{0x8302'8100, 0x8706'8504, 0x8b0a'8908, 0x8f0e'8d0c},
8828 {0x9312'9110, 0x9716'9514, 0x9b1a'9918, 0x9f1e'9d1c},
8829 {0xa322'a120, 0xa726'a524, 0xab2a'a928, 0xaf2e'ad2c},
8830 {0xb332'b130, 0xb736'b534, 0xbb3a'b938, 0xbf3e'bd3c},
8831 {0xc342'c140, 0xc746'c544, 0xcb4a'c948, 0xcf4e'cd4c},
8832 {0xd352'd150, 0xd756'd554, 0xdb5a'd958, 0xdf5e'dd5c},
8833 {0xe362'e160, 0xe766'e564, 0xeb6a'e968, 0xef6e'ed6c},
8834 {0xf372'f170, 0xf776'f574, 0xfb7a'f978, 0xff7e'fd7c}},
8835 {},
8836 2,
8837 kVectorCalculationsSourceLegacy);
8838 TestVleXX(0xf407, // vle64.v v8, (x1), v0.t
8839 {},
8840 {},
8841 {},
8842 {{0x8706'8504'8302'8100, 0x8f0e'8d0c'8b0a'8908},
8843 {0x9716'9514'9312'9110, 0x9f1e'9d1c'9b1a'9918},
8844 {0xa726'a524'a322'a120, 0xaf2e'ad2c'ab2a'a928},
8845 {0xb736'b534'b332'b130, 0xbf3e'bd3c'bb3a'b938},
8846 {0xc746'c544'c342'c140, 0xcf4e'cd4c'cb4a'c948},
8847 {0xd756'd554'd352'd150, 0xdf5e'dd5c'db5a'd958},
8848 {0xe766'e564'e362'e160, 0xef6e'ed6c'eb6a'e968},
8849 {0xf776'f574'f372'f170, 0xff7e'fd7c'fb7a'f978}},
8850 3,
8851 kVectorCalculationsSourceLegacy);
8852 }
8853
TEST_F(Riscv64InterpreterTest,TestVleXXff)8854 TEST_F(Riscv64InterpreterTest, TestVleXXff) {
8855 TestVleXXff(0x1008407, 6, 0, 6); // vle8ff.v v8, (x1), v0.t
8856 TestVleXXff(0x1008407, 8, 0, 8);
8857 TestVleXXff(0x1008407, 16, 0, 16);
8858 TestVleXXff(0x1008407, 32, 0, 32);
8859 TestVleXXff(0x1008407, 255, 0, 128); // All 128 bytes accessible.
8860
8861 TestVleXXff(0x100d407, 6, 1, 3); // vle16ff.v v8, (x1), v0.t
8862 TestVleXXff(0x100d407, 8, 1, 4);
8863 TestVleXXff(0x100d407, 16, 1, 8);
8864 TestVleXXff(0x100d407, 32, 1, 16);
8865
8866 TestVleXXff(0x100e407, 6, 2, 1); // vle32ff.v v8, (x1), v0.t
8867 TestVleXXff(0x100e407, 8, 2, 2);
8868 TestVleXXff(0x100e407, 16, 2, 4);
8869 TestVleXXff(0x100e407, 32, 2, 8);
8870 TestVleXXff(0x100e407, 64, 2, 16);
8871
8872 TestVleXXff(0x100f407, 8, 3, 1); // vle64ff.v v8, (x1), v0.t
8873 TestVleXXff(0x100f407, 16, 3, 2);
8874 TestVleXXff(0x100f407, 32, 3, 4);
8875 TestVleXXff(0x100f407, 64, 3, 8);
8876
8877 TestVleXXff(0x100f407, 6, 3, 16, true); // Should raise exception and not change VL
8878 }
8879
TEST_F(Riscv64InterpreterTest,TestVcpopm)8880 TEST_F(Riscv64InterpreterTest, TestVcpopm) {
8881 TestVXmXXsInstruction(
8882 0x410820d7, // vcpop.m x1, v16, v0.t
8883 { 0, /* default value when vl=0 */
8884 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2,
8885 2, 3, 3, 3, 3, 3, 3, 3, 4, 5, 5, 5, 5, 5, 5, 6,
8886 6, 6, 7, 7, 7, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 10,
8887 10, 11, 12, 12, 12, 12, 12, 12, 13, 14, 15, 15, 15, 15, 15, 16,
8888 16, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 19, 19, 19, 19, 20,
8889 20, 21, 21, 22, 22, 22, 22, 22, 23, 24, 24, 25, 25, 25, 25, 26,
8890 26, 26, 27, 28, 28, 28, 28, 28, 29, 29, 30, 31, 31, 31, 31, 32,
8891 32, 33, 34, 35, 35, 35, 35, 35, 36, 37, 38, 39, 39, 39, 39, 40},
8892 { 0, /* default value when vl=0 */
8893 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2,
8894 2, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 5,
8895 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 8,
8896 8, 8, 9, 9, 9, 9, 9, 9, 10, 10, 11, 11, 11, 11, 11, 12,
8897 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13, 14, 14, 14, 14, 14,
8898 14, 14, 14, 15, 15, 15, 15, 15, 15, 16, 16, 17, 17, 17, 17, 18,
8899 18, 18, 18, 19, 19, 19, 19, 19, 20, 20, 21, 21, 21, 21, 21, 21,
8900 21, 22, 23, 23, 23, 23, 23, 23, 23, 24, 24, 25, 25, 25, 25, 25},
8901 kVectorCalculationsSourceLegacy[0]);
8902 }
8903
TEST_F(Riscv64InterpreterTest,TestVfirstm)8904 TEST_F(Riscv64InterpreterTest, TestVfirstm) {
8905 TestVXmXXsInstruction(
8906 0x4108a0d7, // vfirst.m x1, v16, v0.t
8907 { [0 ... 8] = ~0ULL,
8908 [9 ... 128] = 8 },
8909 { [0 ... 8] = ~0ULL,
8910 [9 ... 128] = 8 },
8911 kVectorCalculationsSourceLegacy[0]);
8912 }
8913
8914 // For Vrgather the expectations for different VLMULs are very different, i.e. different vlmax
8915 // values produce different results for the same src. So we have to call each of them explicitly.
8916 // To produce none-all-zero expected_results, all registers index vectors(v24) have first half
8917 // masked to have valid indexes (< vlmax); x1 is masked to be < vlmax; uimm is accordingly to be 0,
8918 // 1 or 3.
TEST_F(Riscv64InterpreterTest,TestVrgather)8919 TEST_F(Riscv64InterpreterTest, TestVrgather) {
8920 // VLMUL = 0
8921 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
8922 {{0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8923 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8924 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8925 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8926 {0, 2, 4, 6, 137, 10, 12, 14, 0, 2, 0, 6, 0, 10, 0, 14},
8927 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8928 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0},
8929 {0, 2, 4, 6, 137, 10, 12, 14, 0, 0, 0, 0, 0, 0, 0, 0}},
8930 {{0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8931 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8932 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8933 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8934 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8935 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8936 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000},
8937 {0x8100, 0x8908, 0x8302, 0x8908, 0x0000, 0x0000, 0x0000, 0x0000}},
8938 {{0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8939 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8940 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8941 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8942 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8943 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8944 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
8945 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000}},
8946 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8947 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8948 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8949 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8950 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8951 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8952 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
8953 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
8954 /*vlmul=*/0,
8955 kVectorCalculationsSource);
8956
8957 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
8958 {{10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8959 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8960 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8961 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8962 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8963 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8964 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
8965 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}},
8966 {{0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8967 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8968 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8969 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8970 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8971 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8972 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
8973 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504}},
8974 {{0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8975 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8976 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8977 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8978 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8979 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8980 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
8981 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908}},
8982 {{0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8983 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8984 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8985 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8986 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8987 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8988 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
8989 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100}},
8990 /*vlmul=*/0,
8991 kVectorCalculationsSource);
8992 TestVectorRegisterGather(
8993 0x3100b457, // vrgather.vi v8,v16,1,v0.t
8994 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8995 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8996 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8997 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8998 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
8999 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9000 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9001 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
9002 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9003 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9004 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9005 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9006 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9007 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9008 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9009 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
9010 {{0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9011 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9012 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9013 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9014 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9015 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9016 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9017 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504}},
9018 {{0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9019 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9020 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9021 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9022 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9023 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9024 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9025 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908}},
9026 /*vlmul=*/0,
9027 kVectorCalculationsSource);
9028
9029 // VLMUL = 1
9030 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
9031 {{0, 18, 4, 22, 137, 26, 12, 30, 145, 0, 20, 0, 24, 0, 28, 0},
9032 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
9033 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
9034 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
9035 {0, 18, 4, 22, 137, 26, 12, 30, 0, 2, 0, 6, 0, 10, 0, 14},
9036 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
9037 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
9038 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0}},
9039 {{0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9040 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9041 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9042 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9043 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9044 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9045 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9046 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000}},
9047 {{0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9048 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9049 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9050 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9051 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9052 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9053 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9054 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000}},
9055 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9056 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9057 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9058 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9059 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9060 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9061 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9062 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
9063 /*vlmul=*/1,
9064 kVectorCalculationsSource);
9065 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
9066 {{10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
9067 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
9068 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
9069 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
9070 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
9071 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
9072 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10},
9073 {10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}},
9074 {{0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9075 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9076 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9077 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9078 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9079 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9080 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9081 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514}},
9082 {{0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
9083 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
9084 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
9085 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
9086 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
9087 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
9088 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908},
9089 {0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908, 0x8b0a'8908}},
9090 {{0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9091 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9092 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9093 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9094 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9095 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9096 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9097 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110}},
9098 /*vlmul=*/1,
9099 kVectorCalculationsSource);
9100 TestVectorRegisterGather(
9101 0x3100b457, // vrgather.vi v8,v16,1,v0.t
9102 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9103 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9104 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9105 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9106 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9107 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9108 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9109 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
9110 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9111 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9112 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9113 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9114 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9115 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9116 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9117 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
9118 {{0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9119 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9120 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9121 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9122 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9123 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9124 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9125 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504}},
9126 {{0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9127 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9128 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9129 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9130 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9131 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9132 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9133 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908}},
9134 /*vlmul=*/1,
9135 kVectorCalculationsSource);
9136
9137 // VLMUL = 2
9138 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
9139 {{0, 18, 4, 22, 137, 26, 12, 30, 145, 0, 20, 0, 24, 0, 28, 0},
9140 {32, 50, 36, 54, 169, 58, 44, 62, 177, 0, 52, 0, 56, 0, 60, 0},
9141 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
9142 {32, 50, 36, 54, 169, 58, 44, 62, 0, 0, 0, 0, 0, 0, 0, 0},
9143 {0, 18, 4, 22, 137, 26, 12, 30, 0, 2, 0, 6, 0, 10, 0, 14},
9144 {32, 50, 36, 54, 169, 58, 44, 62, 0, 34, 0, 38, 0, 42, 0, 46},
9145 {0, 18, 4, 22, 137, 26, 12, 30, 0, 0, 0, 0, 0, 0, 0, 0},
9146 {32, 50, 36, 54, 169, 58, 44, 62, 0, 0, 0, 0, 0, 0, 0, 0}},
9147 {{0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9148 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9149 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9150 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9151 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9152 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9153 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9154 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000}},
9155 {{0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9156 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9157 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9158 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9159 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9160 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9161 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9162 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000}},
9163 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9164 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9165 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9166 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9167 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9168 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9169 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9170 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
9171 /*vlmul=*/2,
9172 kVectorCalculationsSource);
9173 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
9174 {{42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9175 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9176 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9177 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9178 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9179 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9180 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9181 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42}},
9182 {{0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9183 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9184 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9185 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9186 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9187 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9188 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514},
9189 {0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514, 0x9514}},
9190 {{0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9191 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9192 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9193 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9194 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9195 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9196 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9197 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928}},
9198 {{0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9199 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9200 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9201 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9202 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9203 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9204 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110},
9205 {0x9716'9514'9312'9110, 0x9716'9514'9312'9110}},
9206 /*vlmul=*/2,
9207 kVectorCalculationsSource);
9208 TestVectorRegisterGather(
9209 0x3100b457, // vrgather.vi v8,v16,1,v0.t
9210 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9211 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9212 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9213 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9214 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9215 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9216 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9217 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
9218 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9219 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9220 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9221 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9222 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9223 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9224 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9225 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
9226 {{0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9227 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9228 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9229 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9230 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9231 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9232 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9233 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504}},
9234 {{0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9235 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9236 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9237 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9238 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9239 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9240 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908},
9241 {0x8f0e'8d0c'8b0a'8908, 0x8f0e'8d0c'8b0a'8908}},
9242 /*vlmul=*/2,
9243 kVectorCalculationsSource);
9244
9245 // VLMUL = 3
9246 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
9247 {{0, 18, 4, 22, 137, 26, 12, 30, 145, 0, 20, 0, 24, 0, 28, 0},
9248 {32, 50, 36, 54, 169, 58, 44, 62, 177, 0, 52, 0, 56, 0, 60, 0},
9249 {64, 82, 68, 86, 201, 90, 76, 94, 209, 0, 84, 0, 88, 0, 92, 0},
9250 {96, 114, 100, 118, 233, 122, 108, 126, 241, 0, 116, 0, 120, 0, 124, 0},
9251 {0, 18, 4, 22, 137, 26, 12, 30, 0, 2, 0, 6, 0, 10, 0, 14},
9252 {32, 50, 36, 54, 169, 58, 44, 62, 0, 34, 0, 38, 0, 42, 0, 46},
9253 {64, 82, 68, 86, 201, 90, 76, 94, 0, 66, 0, 70, 0, 74, 0, 78},
9254 {96, 114, 100, 118, 233, 122, 108, 126, 0, 98, 0, 102, 0, 106, 0, 110}},
9255 {{0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9256 {0xc140, 0xc948, 0xd352, 0xd958, 0x0000, 0x0000, 0x0000, 0x0000},
9257 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9258 {0xc140, 0xc948, 0xd352, 0xd958, 0x0000, 0x0000, 0x0000, 0x0000},
9259 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9260 {0xc140, 0xc948, 0xd352, 0xd958, 0x0000, 0x0000, 0x0000, 0x0000},
9261 {0x8100, 0x8908, 0x9312, 0x9918, 0x0000, 0x0000, 0x0000, 0x0000},
9262 {0xc140, 0xc948, 0xd352, 0xd958, 0x0000, 0x0000, 0x0000, 0x0000}},
9263 {{0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9264 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9265 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9266 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9267 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9268 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9269 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000},
9270 {0x8302'8100, 0xa726'a524, 0x0000'0000, 0x0000'0000}},
9271 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9272 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9273 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9274 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9275 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9276 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9277 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9278 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
9279 /*vlmul=*/3,
9280 kVectorCalculationsSource);
9281 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
9282 {{42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9283 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9284 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9285 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9286 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9287 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9288 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42},
9289 {42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42}},
9290 {{0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
9291 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
9292 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
9293 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
9294 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
9295 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
9296 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554},
9297 {0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554, 0xd554}},
9298 {{0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9299 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9300 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9301 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9302 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9303 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9304 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928},
9305 {0xab2a'a928, 0xab2a'a928, 0xab2a'a928, 0xab2a'a928}},
9306 {{0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
9307 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
9308 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
9309 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
9310 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
9311 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
9312 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150},
9313 {0xd756'd554'd352'd150, 0xd756'd554'd352'd150}},
9314 /*vlmul=*/3,
9315 kVectorCalculationsSource);
9316 TestVectorRegisterGather(
9317 0x3101b457, // vrgather.vi v8,v16,3,v0.t
9318 {{131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
9319 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
9320 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
9321 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
9322 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
9323 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
9324 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131},
9325 {131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, 131}},
9326 {{0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
9327 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
9328 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
9329 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
9330 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
9331 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
9332 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706},
9333 {0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706, 0x8706}},
9334 {{0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
9335 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
9336 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
9337 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
9338 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
9339 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
9340 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c},
9341 {0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c, 0x8f0e'8d0c}},
9342 {{0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
9343 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
9344 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
9345 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
9346 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
9347 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
9348 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918},
9349 {0x9f1e'9d1c'9b1a'9918, 0x9f1e'9d1c'9b1a'9918}},
9350 /*vlmul=*/3,
9351 kVectorCalculationsSource);
9352
9353 // VLMUL = 5
9354 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
9355 {{0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9356 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9357 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9358 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9359 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9360 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9361 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9362 {0, 0, 0, 0, 129, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
9363 {{0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9364 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9365 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9366 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9367 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9368 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9369 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9370 {0x8100, 0x8100, 0x8100, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000}},
9371 {},
9372 {},
9373 /*vlmul=*/5,
9374 kVectorCalculationsSource);
9375 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
9376 {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9377 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9378 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9379 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9380 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9381 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9382 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
9383 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
9384 {{0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9385 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9386 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9387 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9388 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9389 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9390 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9391 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100}},
9392 {},
9393 {},
9394 /*vlmul=*/5,
9395 kVectorCalculationsSource);
9396 TestVectorRegisterGather(
9397 0x3100b457, // vrgather.vi v8,v16,1,v0.t
9398 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9399 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9400 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9401 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9402 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9403 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9404 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9405 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
9406 {{0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
9407 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
9408 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
9409 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
9410 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
9411 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
9412 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
9413 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}},
9414 {},
9415 {},
9416 /*vlmul=*/5,
9417 kVectorCalculationsSource);
9418
9419 // VLMUL = 6
9420 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
9421 {{0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
9422 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
9423 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
9424 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
9425 {0, 2, 0, 2, 129, 2, 0, 2, 0, 2, 0, 0, 0, 0, 0, 0},
9426 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
9427 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0},
9428 {0, 2, 0, 2, 129, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0}},
9429 {{0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9430 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9431 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9432 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9433 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9434 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9435 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9436 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000}},
9437 {{0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
9438 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
9439 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
9440 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
9441 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
9442 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
9443 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000},
9444 {0x8302'8100, 0x8302'8100, 0x0000'0000, 0x0000'0000}},
9445 {},
9446 /*vlmul=*/6,
9447 kVectorCalculationsSource);
9448 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
9449 {{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9450 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9451 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9452 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9453 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9454 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9455 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9456 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}},
9457 {{0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9458 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9459 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9460 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9461 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9462 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9463 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100},
9464 {0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100, 0x8100}},
9465 {{0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9466 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9467 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9468 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9469 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9470 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9471 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9472 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100}},
9473 {},
9474 /*vlmul=*/6,
9475 kVectorCalculationsSource);
9476 TestVectorRegisterGather(
9477 0x3100b457, // vrgather.vi v8,v16,1,v0.t
9478 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9479 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9480 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9481 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9482 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9483 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9484 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9485 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
9486 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9487 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9488 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9489 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9490 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9491 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9492 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9493 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
9494 {{0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
9495 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
9496 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
9497 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
9498 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
9499 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
9500 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000},
9501 {0x0000'0000, 0x0000'0000, 0x0000'0000, 0x0000'0000}},
9502 {},
9503 /*vlmul=*/6,
9504 kVectorCalculationsSource);
9505
9506 // VLMUL = 7
9507 TestVectorRegisterGather(0x310c0457, // vrgather.vv v8,v16,v24,v0.t
9508 {{0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
9509 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
9510 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
9511 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
9512 {0, 2, 4, 6, 129, 2, 4, 6, 0, 2, 0, 6, 0, 0, 0, 0},
9513 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
9514 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0},
9515 {0, 2, 4, 6, 129, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0}},
9516 {{0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9517 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9518 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9519 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9520 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9521 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9522 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000},
9523 {0x8100, 0x8100, 0x8302, 0x8100, 0x0000, 0x0000, 0x0000, 0x0000}},
9524 {{0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9525 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9526 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9527 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9528 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9529 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9530 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000},
9531 {0x8302'8100, 0x8706'8504, 0x0000'0000, 0x0000'0000}},
9532 {{0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9533 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9534 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9535 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9536 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9537 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9538 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000},
9539 {0x8706'8504'8302'8100, 0x0000'0000'0000'0000}},
9540 /*vlmul=*/7,
9541 kVectorCalculationsSource);
9542 TestVectorRegisterGather(0x3100c457, // vrgather.vx v8,v16,x1,v0.t
9543 {{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9544 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9545 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9546 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9547 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9548 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9549 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
9550 {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}},
9551 {{0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9552 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9553 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9554 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9555 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9556 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9557 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504},
9558 {0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504, 0x8504}},
9559 {{0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9560 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9561 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9562 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9563 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9564 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9565 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100},
9566 {0x8302'8100, 0x8302'8100, 0x8302'8100, 0x8302'8100}},
9567 {{0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9568 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9569 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9570 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9571 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9572 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9573 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100},
9574 {0x8706'8504'8302'8100, 0x8706'8504'8302'8100}},
9575 /*vlmul=*/7,
9576 kVectorCalculationsSource);
9577 TestVectorRegisterGather(
9578 0x3100b457, // vrgather.vi v8,v16,1,v0.t
9579 {{129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9580 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9581 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9582 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9583 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9584 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9585 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129},
9586 {129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, 129}},
9587 {{0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9588 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9589 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9590 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9591 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9592 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9593 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302},
9594 {0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302, 0x8302}},
9595 {{0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9596 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9597 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9598 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9599 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9600 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9601 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504},
9602 {0x8706'8504, 0x8706'8504, 0x8706'8504, 0x8706'8504}},
9603 {{0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9604 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9605 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9606 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9607 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9608 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9609 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000},
9610 {0x0000'0000'0000'0000, 0x0000'0000'0000'0000}},
9611 /*vlmul=*/7,
9612 kVectorCalculationsSource);
9613 }
9614
9615 } // namespace
9616
9617 } // namespace berberis
9618