1 /****************************************************************************** 2 * 3 * Copyright 2010-2018, 2021-2022 NXP 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ******************************************************************************/ 18 /* 19 * OSAL header files related to memory, debug, random, semaphore and mutex 20 * functions. 21 */ 22 23 #ifndef PHNFCCOMMON_H 24 #define PHNFCCOMMON_H 25 26 /* 27 ************************* Include Files **************************************** 28 */ 29 30 #include <phDal4Nfc_messageQueueLib.h> 31 #include <phNfcCompId.h> 32 #include <phNfcStatus.h> 33 #include <phOsalNfc_Timer.h> 34 #include <pthread.h> 35 #include <semaphore.h> 36 37 #define FW_DLL_ROOT_DIR "/system/vendor/" 38 #define FW_DLL_EXTENSION ".so" 39 40 /* Actual FW library name*/ 41 /* Restore Corrupted PLL Settings/etc */ 42 #define PLATFORM_LIB_PATH \ 43 FW_DLL_ROOT_DIR "libsn100u_fw_platform" FW_DLL_EXTENSION 44 /* Upgrade the public Key */ 45 #define PKU_LIB_PATH FW_DLL_ROOT_DIR "libsn100u_fw_pku" FW_DLL_EXTENSION 46 47 /* HAL Version number (Updated as per release) */ 48 #define NXP_MW_VERSION_MAJ (0x03) 49 #define NXP_MW_VERSION_MIN (0x02) 50 51 #define GET_EEPROM_DATA (1U) 52 #define SET_EEPROM_DATA (2U) 53 54 #define BITWISE (1U) 55 #define BYTEWISE (2U) 56 57 #define GET_FW_DWNLD_FLAG (1U) 58 #define RESET_FW_DWNLD_FLAG (2U) 59 60 #define FLASH_UPPER_VERSION (1) 61 #define FLASH_DIFFERENT_VERSION (2) 62 #define FLASH_ALWAYS (3) 63 /* 64 ***************************************************************** 65 *********** System clock source selection configuration ******** 66 ***************************************************************** 67 */ 68 69 #define CLK_SRC_UNDEF 0 70 #define CLK_SRC_XTAL 1 71 #define CLK_SRC_PLL 2 72 #define CLK_SRC_PADDIRECT 3 73 #define CLK_CFG_XTAL 8 74 75 /*Extern crystal clock source*/ 76 /* Use one of CLK_SRC_<value> */ 77 #define NXP_SYS_CLK_SRC_SEL CLK_SRC_PLL 78 /*Direct clock*/ 79 80 /* 81 ***************************************************************** 82 *********** System clock frequency selection configuration **************** 83 * If Clk_Src is set to PLL, make sure to set the Clk_Freq also* 84 ***************************************************************** 85 */ 86 #define CLK_FREQ_UNDEF 0 87 #define CLK_FREQ_13MHZ 1 88 #define CLK_FREQ_19_2MHZ 2 89 #define CLK_FREQ_24MHZ 3 90 #define CLK_FREQ_26MHZ 4 91 #define CLK_FREQ_38_4MHZ 5 92 #define CLK_FREQ_52MHZ 6 93 #define CLK_FREQ_32MHZ 7 94 #define CLK_FREQ_48MHZ 8 95 96 static const uint8_t PN557_SET_CONFIG_CMD_PLL_13MHZ[] = { 97 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x20, 0x08, 0x08, 98 0x52, 0xA2, 0x02, 0x30, 0x01, 0xE1, 0x02}; 99 100 static const uint8_t PN557_SET_CONFIG_CMD_DPLL_13MHZ[] = { 101 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x26, 0x08, 0x40, 102 0x42, 0xA3, 0x02, 0x88, 0x01, 0xE2, 0x02}; 103 104 static const uint8_t PN557_SET_CONFIG_CMD_PLL_19_2MHZ[] = { 105 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x20, 0x08, 0x88, 106 0x51, 0xE3, 0x02, 0xB8, 0x21, 0xE1, 0x02}; 107 108 static const uint8_t PN557_SET_CONFIG_CMD_DPLL_19_2MHZ[] = { 109 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x26, 0x08, 0x88, 110 0x01, 0xE2, 0x02, 0xF0, 0x00, 0xA2, 0x01}; 111 112 static const uint8_t PN557_SET_CONFIG_CMD_PLL_24MHZ[] = { 113 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x20, 0x08, 0x28, 114 0xC2, 0xA2, 0x83, 0x88, 0x11, 0xE1, 0x02}; 115 116 static const uint8_t PN557_SET_CONFIG_CMD_DPLL_24MHZ[] = { 117 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x26, 0x08, 0x38, 118 0x41, 0xD3, 0x02, 0x88, 0x01, 0xE2, 0x02}; 119 120 static const uint8_t PN557_SET_CONFIG_CMD_PLL_26MHZ[] = { 121 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x20, 0x08, 0x08, 122 0x52, 0xA2, 0x82, 0x30, 0x01, 0xE1, 0x02}; 123 124 static const uint8_t PN557_SET_CONFIG_CMD_DPLL_26MHZ[] = { 125 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x26, 0x08, 0x20, 126 0x41, 0xA3, 0x01, 0x88, 0x01, 0xE2, 0x02}; 127 128 static const uint8_t PN557_SET_CONFIG_CMD_PLL_32MHZ[] = { 129 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x20, 0x08, 0xB8, 130 0x51, 0xA3, 0x82, 0x88, 0xF1, 0xF0, 0x02}; 131 132 static const uint8_t PN557_SET_CONFIG_CMD_DPLL_32MHZ[] = { 133 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x26, 0x08, 0xB0, 134 0x01, 0xA3, 0x82, 0x88, 0x01, 0xE2, 0x02}; 135 136 static const uint8_t PN557_SET_CONFIG_CMD_PLL_38_4MHZ[] = { 137 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x20, 0x08, 0x88, 138 0x51, 0xE3, 0x82, 0xB8, 0x21, 0xE1, 0x02}; 139 140 static const uint8_t PN557_SET_CONFIG_CMD_DPLL_38_4MHZ[] = { 141 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x26, 0x08, 0x88, 142 0x01, 0xE2, 0x82, 0xF0, 0x00, 0xA2, 0x01}; 143 144 static const uint8_t PN557_SET_CONFIG_CMD_PLL_48MHZ[] = { 145 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x20, 0x08, 0x38, 146 0x51, 0xD3, 0x82, 0x58, 0xE1, 0xE0, 0x02}; 147 148 static const uint8_t PN557_SET_CONFIG_CMD_DPLL_48MHZ[] = { 149 0x20, 0x02, 0x0C, 0x01, 0xA0, 0x26, 0x08, 0x38, 150 0x41, 0xD3, 0x82, 0x88, 0x01, 0xE2, 0x02}; 151 /* Set to one of CLK_FREQ_<value> */ 152 #define NXP_SYS_CLK_FREQ_SEL CLK_FREQ_19_2MHZ 153 154 #define CLK_TO_CFG_DEF 1 155 #define CLK_TO_CFG_MAX 6 156 157 #define CLK_REQ_DELAY_MIN 1 158 #define CLK_REQ_DELAY_MAX 31 159 #define CLK_REQ_DELAY_DEF 22 160 #define CLK_REQ_DELAY_MASK 0x1F 161 #define CLK_REQ_DELAY_PLL_OFFSET 13 162 #define CLK_REQ_DELAY_XTAL_OFFSET 14 163 /* 164 * information to configure OSAL 165 */ 166 typedef struct phOsalNfc_Config { 167 uint8_t* pLogFile; /* Log File Name*/ 168 uintptr_t dwCallbackThreadId; /* Client ID to which message is posted */ 169 } phOsalNfc_Config_t, *pphOsalNfc_Config_t /* Pointer to #phOsalNfc_Config_t */; 170 171 /* 172 * Deferred call declaration. 173 * This type of API is called from ClientApplication (main thread) to notify 174 * specific callback. 175 */ 176 typedef void (*pphOsalNfc_DeferFuncPointer_t)(void*); 177 178 /* 179 * Deferred message specific info declaration. 180 */ 181 typedef struct phOsalNfc_DeferedCallInfo { 182 pphOsalNfc_DeferFuncPointer_t pDeferedCall; /* pointer to Deferred callback */ 183 void* pParam; /* contains timer message specific details*/ 184 } phOsalNfc_DeferedCallInfo_t; 185 186 /* 187 * States in which a OSAL timer exist. 188 */ 189 typedef enum { 190 eTimerIdle = 0, /* Indicates Initial state of timer */ 191 eTimerRunning = 1, /* Indicate timer state when started */ 192 eTimerStopped = 2 /* Indicates timer state when stopped */ 193 } phOsalNfc_TimerStates_t; /* Variable representing State of timer */ 194 195 /* 196 **Timer Handle structure containing details of a timer. 197 */ 198 typedef struct phOsalNfc_TimerHandle { 199 uint32_t TimerId; /* ID of the timer */ 200 timer_t hTimerHandle; /* Handle of the timer */ 201 /* Timer callback function to be invoked */ 202 pphOsalNfc_TimerCallbck_t Application_callback; 203 void* pContext; /* Parameter to be passed to the callback function */ 204 phOsalNfc_TimerStates_t eState; /* Timer states */ 205 /* Osal Timer message posted on User Thread */ 206 phLibNfc_Message_t tOsalMessage; 207 /* Deferred Call structure to Invoke Callback function */ 208 phOsalNfc_DeferedCallInfo_t tDeferedCallInfo; 209 /* Variables for Structure Instance and Structure Ptr */ 210 } phOsalNfc_TimerHandle_t, *pphOsalNfc_TimerHandle_t; 211 212 #endif /* PHOSALNFC_H */ 213