1 /* 2 * Copyright (c) 2012 Travis Geiselbrecht 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files 6 * (the "Software"), to deal in the Software without restriction, 7 * including without limitation the rights to use, copy, modify, merge, 8 * publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, 10 * subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __PLATFORM_VEXPRESS_A15_H 24 #define __PLATFORM_VEXPRESS_A15_H 25 26 #define REGISTER_BANK_0_PADDR (0x1c000000) 27 #define REGISTER_BANK_1_PADDR (0x1c100000) 28 #define REGISTER_BANK_2_PADDR (0x2c000000) 29 30 #define REGISTER_BANK_0_VADDR (0x1c000000) /* use identry map for now */ 31 #define REGISTER_BANK_1_VADDR (0x1c100000) 32 #define REGISTER_BANK_2_VADDR (0x2c000000) 33 34 /* hardware base addresses */ 35 #define SECONDARY_BOOT_ADDR (REGISTER_BANK_0_VADDR + 0x10030) 36 37 #define UART0 (REGISTER_BANK_0_VADDR + 0x90000) 38 #define UART1 (REGISTER_BANK_0_VADDR + 0xa0000) 39 #define UART2 (REGISTER_BANK_0_VADDR + 0xb0000) 40 #define UART3 (REGISTER_BANK_0_VADDR + 0xc0000) 41 42 #define TIMER0 (REGISTER_BANK_1_VADDR + 0x10000) 43 #define TIMER1 (REGISTER_BANK_1_VADDR + 0x10020) 44 #define TIMER2 (REGISTER_BANK_1_VADDR + 0x20000) 45 #define TIMER3 (REGISTER_BANK_1_VADDR + 0x20020) 46 47 #define GIC0 (REGISTER_BANK_2_VADDR + 0x00000) 48 #define GIC1 (REGISTER_BANK_2_VADDR + 0x10000) 49 #define GIC2 (REGISTER_BANK_2_VADDR + 0x20000) 50 #define GIC3 (REGISTER_BANK_2_VADDR + 0x30000) 51 #define GICBASE(n) (GIC0 + (n)*0x10000) 52 53 /* interrupts */ 54 #define ARM_GENERIC_TIMER_INT 29 55 #define TIMER01_INT 34 56 #define TIMER23_INT 35 57 #define UART0_INT 37 58 #define UART1_INT 38 59 #define UART2_INT 39 60 #define UART3_INT 40 61 62 #define MAX_INT 96 63 64 #endif 65