1 /*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "assembler_x86.h"
18
19 #include "base/casts.h"
20 #include "base/memory_region.h"
21 #include "entrypoints/quick/quick_entrypoints.h"
22 #include "thread.h"
23
24 namespace art HIDDEN {
25 namespace x86 {
26
operator <<(std::ostream & os,const XmmRegister & reg)27 std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29 }
30
operator <<(std::ostream & os,const X87Register & reg)31 std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33 }
34
operator <<(std::ostream & os,const Address & addr)35 std::ostream& operator<<(std::ostream& os, const Address& addr) {
36 switch (addr.mod()) {
37 case 0:
38 if (addr.rm() != ESP || addr.index() == ESP) {
39 return os << "(%" << addr.rm() << ")";
40 } else if (addr.base() == EBP) {
41 return os << static_cast<int>(addr.disp32()) << "(,%" << addr.index()
42 << "," << (1 << addr.scale()) << ")";
43 }
44 return os << "(%" << addr.base() << ",%" << addr.index() << "," << (1 << addr.scale()) << ")";
45 case 1:
46 if (addr.rm() != ESP || addr.index() == ESP) {
47 return os << static_cast<int>(addr.disp8()) << "(%" << addr.rm() << ")";
48 }
49 return os << static_cast<int>(addr.disp8()) << "(%" << addr.base() << ",%"
50 << addr.index() << "," << (1 << addr.scale()) << ")";
51 case 2:
52 if (addr.rm() != ESP || addr.index() == ESP) {
53 return os << static_cast<int>(addr.disp32()) << "(%" << addr.rm() << ")";
54 }
55 return os << static_cast<int>(addr.disp32()) << "(%" << addr.base() << ",%"
56 << addr.index() << "," << (1 << addr.scale()) << ")";
57 default:
58 return os << "<address?>";
59 }
60 }
61
CpuHasAVXorAVX2FeatureFlag()62 bool X86Assembler::CpuHasAVXorAVX2FeatureFlag() {
63 if (has_AVX_ || has_AVX2_) {
64 return true;
65 }
66 return false;
67 }
68
call(Register reg)69 void X86Assembler::call(Register reg) {
70 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
71 EmitUint8(0xFF);
72 EmitRegisterOperand(2, reg);
73 }
74
75
call(const Address & address)76 void X86Assembler::call(const Address& address) {
77 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
78 EmitUint8(0xFF);
79 EmitOperand(2, address);
80 }
81
82
call(Label * label)83 void X86Assembler::call(Label* label) {
84 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
85 EmitUint8(0xE8);
86 static const int kSize = 5;
87 // Offset by one because we already have emitted the opcode.
88 EmitLabel(label, kSize - 1);
89 }
90
91
call(const ExternalLabel & label)92 void X86Assembler::call(const ExternalLabel& label) {
93 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
94 intptr_t call_start = buffer_.GetPosition();
95 EmitUint8(0xE8);
96 EmitInt32(label.address());
97 static const intptr_t kCallExternalLabelSize = 5;
98 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
99 }
100
101
pushl(Register reg)102 void X86Assembler::pushl(Register reg) {
103 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
104 EmitUint8(0x50 + reg);
105 }
106
107
pushl(const Address & address)108 void X86Assembler::pushl(const Address& address) {
109 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
110 EmitUint8(0xFF);
111 EmitOperand(6, address);
112 }
113
114
pushl(const Immediate & imm)115 void X86Assembler::pushl(const Immediate& imm) {
116 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
117 if (imm.is_int8()) {
118 EmitUint8(0x6A);
119 EmitUint8(imm.value() & 0xFF);
120 } else {
121 EmitUint8(0x68);
122 EmitImmediate(imm);
123 }
124 }
125
126
popl(Register reg)127 void X86Assembler::popl(Register reg) {
128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129 EmitUint8(0x58 + reg);
130 }
131
132
popl(const Address & address)133 void X86Assembler::popl(const Address& address) {
134 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
135 EmitUint8(0x8F);
136 EmitOperand(0, address);
137 }
138
139
movl(Register dst,const Immediate & imm)140 void X86Assembler::movl(Register dst, const Immediate& imm) {
141 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
142 EmitUint8(0xB8 + dst);
143 EmitImmediate(imm);
144 }
145
146
movl(Register dst,Register src)147 void X86Assembler::movl(Register dst, Register src) {
148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
149 EmitUint8(0x89);
150 EmitRegisterOperand(src, dst);
151 }
152
153
movl(Register dst,const Address & src)154 void X86Assembler::movl(Register dst, const Address& src) {
155 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
156 EmitUint8(0x8B);
157 EmitOperand(dst, src);
158 }
159
160
movl(const Address & dst,Register src)161 void X86Assembler::movl(const Address& dst, Register src) {
162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0x89);
164 EmitOperand(src, dst);
165 }
166
167
movl(const Address & dst,const Immediate & imm)168 void X86Assembler::movl(const Address& dst, const Immediate& imm) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0xC7);
171 EmitOperand(0, dst);
172 EmitImmediate(imm);
173 }
174
movl(const Address & dst,Label * lbl)175 void X86Assembler::movl(const Address& dst, Label* lbl) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0xC7);
178 EmitOperand(0, dst);
179 EmitLabel(lbl, dst.length_ + 5);
180 }
181
movntl(const Address & dst,Register src)182 void X86Assembler::movntl(const Address& dst, Register src) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xC3);
186 EmitOperand(src, dst);
187 }
188
blsi(Register dst,Register src)189 void X86Assembler::blsi(Register dst, Register src) {
190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191 uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
192 uint8_t byte_one = EmitVexPrefixByteOne(false, false, false, SET_VEX_M_0F_38);
193 uint8_t byte_two = EmitVexPrefixByteTwo(false,
194 X86ManagedRegister::FromCpuRegister(dst),
195 SET_VEX_L_128, SET_VEX_PP_NONE);
196 EmitUint8(byte_zero);
197 EmitUint8(byte_one);
198 EmitUint8(byte_two);
199 EmitUint8(0xF3);
200 EmitRegisterOperand(3, src);
201 }
202
blsmsk(Register dst,Register src)203 void X86Assembler::blsmsk(Register dst, Register src) {
204 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
205 uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
206 uint8_t byte_one = EmitVexPrefixByteOne(false, false, false, SET_VEX_M_0F_38);
207 uint8_t byte_two = EmitVexPrefixByteTwo(false,
208 X86ManagedRegister::FromCpuRegister(dst),
209 SET_VEX_L_128, SET_VEX_PP_NONE);
210 EmitUint8(byte_zero);
211 EmitUint8(byte_one);
212 EmitUint8(byte_two);
213 EmitUint8(0xF3);
214 EmitRegisterOperand(2, src);
215 }
216
blsr(Register dst,Register src)217 void X86Assembler::blsr(Register dst, Register src) {
218 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
219 uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
220 uint8_t byte_one = EmitVexPrefixByteOne(false, false, false, SET_VEX_M_0F_38);
221 uint8_t byte_two = EmitVexPrefixByteTwo(false,
222 X86ManagedRegister::FromCpuRegister(dst),
223 SET_VEX_L_128, SET_VEX_PP_NONE);
224 EmitUint8(byte_zero);
225 EmitUint8(byte_one);
226 EmitUint8(byte_two);
227 EmitUint8(0xF3);
228 EmitRegisterOperand(1, src);
229 }
230
bswapl(Register dst)231 void X86Assembler::bswapl(Register dst) {
232 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
233 EmitUint8(0x0F);
234 EmitUint8(0xC8 + dst);
235 }
236
bsfl(Register dst,Register src)237 void X86Assembler::bsfl(Register dst, Register src) {
238 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
239 EmitUint8(0x0F);
240 EmitUint8(0xBC);
241 EmitRegisterOperand(dst, src);
242 }
243
bsfl(Register dst,const Address & src)244 void X86Assembler::bsfl(Register dst, const Address& src) {
245 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
246 EmitUint8(0x0F);
247 EmitUint8(0xBC);
248 EmitOperand(dst, src);
249 }
250
bsrl(Register dst,Register src)251 void X86Assembler::bsrl(Register dst, Register src) {
252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
253 EmitUint8(0x0F);
254 EmitUint8(0xBD);
255 EmitRegisterOperand(dst, src);
256 }
257
bsrl(Register dst,const Address & src)258 void X86Assembler::bsrl(Register dst, const Address& src) {
259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260 EmitUint8(0x0F);
261 EmitUint8(0xBD);
262 EmitOperand(dst, src);
263 }
264
popcntl(Register dst,Register src)265 void X86Assembler::popcntl(Register dst, Register src) {
266 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
267 EmitUint8(0xF3);
268 EmitUint8(0x0F);
269 EmitUint8(0xB8);
270 EmitRegisterOperand(dst, src);
271 }
272
popcntl(Register dst,const Address & src)273 void X86Assembler::popcntl(Register dst, const Address& src) {
274 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
275 EmitUint8(0xF3);
276 EmitUint8(0x0F);
277 EmitUint8(0xB8);
278 EmitOperand(dst, src);
279 }
280
movzxb(Register dst,ByteRegister src)281 void X86Assembler::movzxb(Register dst, ByteRegister src) {
282 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
283 EmitUint8(0x0F);
284 EmitUint8(0xB6);
285 EmitRegisterOperand(dst, src);
286 }
287
288
movzxb(Register dst,const Address & src)289 void X86Assembler::movzxb(Register dst, const Address& src) {
290 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
291 EmitUint8(0x0F);
292 EmitUint8(0xB6);
293 EmitOperand(dst, src);
294 }
295
296
movsxb(Register dst,ByteRegister src)297 void X86Assembler::movsxb(Register dst, ByteRegister src) {
298 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
299 EmitUint8(0x0F);
300 EmitUint8(0xBE);
301 EmitRegisterOperand(dst, src);
302 }
303
304
movsxb(Register dst,const Address & src)305 void X86Assembler::movsxb(Register dst, const Address& src) {
306 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
307 EmitUint8(0x0F);
308 EmitUint8(0xBE);
309 EmitOperand(dst, src);
310 }
311
312
movb(Register,const Address &)313 void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
314 LOG(FATAL) << "Use movzxb or movsxb instead.";
315 }
316
317
movb(const Address & dst,ByteRegister src)318 void X86Assembler::movb(const Address& dst, ByteRegister src) {
319 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
320 EmitUint8(0x88);
321 EmitOperand(src, dst);
322 }
323
324
movb(const Address & dst,const Immediate & imm)325 void X86Assembler::movb(const Address& dst, const Immediate& imm) {
326 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
327 EmitUint8(0xC6);
328 EmitOperand(EAX, dst);
329 CHECK(imm.is_int8());
330 EmitUint8(imm.value() & 0xFF);
331 }
332
333
movzxw(Register dst,Register src)334 void X86Assembler::movzxw(Register dst, Register src) {
335 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
336 EmitUint8(0x0F);
337 EmitUint8(0xB7);
338 EmitRegisterOperand(dst, src);
339 }
340
341
movzxw(Register dst,const Address & src)342 void X86Assembler::movzxw(Register dst, const Address& src) {
343 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
344 EmitUint8(0x0F);
345 EmitUint8(0xB7);
346 EmitOperand(dst, src);
347 }
348
349
movsxw(Register dst,Register src)350 void X86Assembler::movsxw(Register dst, Register src) {
351 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
352 EmitUint8(0x0F);
353 EmitUint8(0xBF);
354 EmitRegisterOperand(dst, src);
355 }
356
357
movsxw(Register dst,const Address & src)358 void X86Assembler::movsxw(Register dst, const Address& src) {
359 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
360 EmitUint8(0x0F);
361 EmitUint8(0xBF);
362 EmitOperand(dst, src);
363 }
364
365
movw(Register,const Address &)366 void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
367 LOG(FATAL) << "Use movzxw or movsxw instead.";
368 }
369
370
movw(const Address & dst,Register src)371 void X86Assembler::movw(const Address& dst, Register src) {
372 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
373 EmitOperandSizeOverride();
374 EmitUint8(0x89);
375 EmitOperand(src, dst);
376 }
377
378
movw(const Address & dst,const Immediate & imm)379 void X86Assembler::movw(const Address& dst, const Immediate& imm) {
380 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
381 EmitOperandSizeOverride();
382 EmitUint8(0xC7);
383 EmitOperand(0, dst);
384 CHECK(imm.is_uint16() || imm.is_int16());
385 EmitUint8(imm.value() & 0xFF);
386 EmitUint8(imm.value() >> 8);
387 }
388
389
leal(Register dst,const Address & src)390 void X86Assembler::leal(Register dst, const Address& src) {
391 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
392 EmitUint8(0x8D);
393 EmitOperand(dst, src);
394 }
395
396
cmovl(Condition condition,Register dst,Register src)397 void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
398 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
399 EmitUint8(0x0F);
400 EmitUint8(0x40 + condition);
401 EmitRegisterOperand(dst, src);
402 }
403
404
cmovl(Condition condition,Register dst,const Address & src)405 void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
406 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
407 EmitUint8(0x0F);
408 EmitUint8(0x40 + condition);
409 EmitOperand(dst, src);
410 }
411
412
setb(Condition condition,Register dst)413 void X86Assembler::setb(Condition condition, Register dst) {
414 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
415 EmitUint8(0x0F);
416 EmitUint8(0x90 + condition);
417 EmitOperand(0, Operand(dst));
418 }
419
420
movaps(XmmRegister dst,XmmRegister src)421 void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
422 if (CpuHasAVXorAVX2FeatureFlag()) {
423 vmovaps(dst, src);
424 return;
425 }
426 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
427 EmitUint8(0x0F);
428 EmitUint8(0x28);
429 EmitXmmRegisterOperand(dst, src);
430 }
431
432 /**VEX.128.0F.WIG 28 /r VMOVAPS xmm1, xmm2*/
vmovaps(XmmRegister dst,XmmRegister src)433 void X86Assembler::vmovaps(XmmRegister dst, XmmRegister src) {
434 DCHECK(CpuHasAVXorAVX2FeatureFlag());
435 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
436 /**Instruction VEX Prefix*/
437 uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
438 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
439 /**a REX prefix is necessary only if an instruction references one of the
440 extended registers or uses a 64-bit operand.*/
441 uint8_t byte_one = EmitVexPrefixByteOne(/*R=*/ false,
442 vvvv_reg,
443 SET_VEX_L_128,
444 SET_VEX_PP_NONE);
445 EmitUint8(byte_zero);
446 EmitUint8(byte_one);
447 /**Instruction Opcode*/
448 EmitUint8(0x28);
449 /**Instruction Operands*/
450 EmitXmmRegisterOperand(dst, src);
451 }
452
movaps(XmmRegister dst,const Address & src)453 void X86Assembler::movaps(XmmRegister dst, const Address& src) {
454 if (CpuHasAVXorAVX2FeatureFlag()) {
455 vmovaps(dst, src);
456 return;
457 }
458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0x0F);
460 EmitUint8(0x28);
461 EmitOperand(dst, src);
462 }
463
464 /**VEX.128.0F.WIG 28 /r VMOVAPS xmm1, m128*/
vmovaps(XmmRegister dst,const Address & src)465 void X86Assembler::vmovaps(XmmRegister dst, const Address& src) {
466 DCHECK(CpuHasAVXorAVX2FeatureFlag());
467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 /**Instruction VEX Prefix*/
469 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
470 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
471 /**a REX prefix is necessary only if an instruction references one of the
472 extended registers or uses a 64-bit operand.*/
473 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
474 vvvv_reg,
475 SET_VEX_L_128,
476 SET_VEX_PP_NONE);
477 EmitUint8(ByteZero);
478 EmitUint8(ByteOne);
479 /**Instruction Opcode*/
480 EmitUint8(0x28);
481 /**Instruction Operands*/
482 EmitOperand(dst, src);
483 }
484
movups(XmmRegister dst,const Address & src)485 void X86Assembler::movups(XmmRegister dst, const Address& src) {
486 if (CpuHasAVXorAVX2FeatureFlag()) {
487 vmovups(dst, src);
488 return;
489 }
490 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
491 EmitUint8(0x0F);
492 EmitUint8(0x10);
493 EmitOperand(dst, src);
494 }
495
496 /**VEX.128.0F.WIG 10 /r VMOVUPS xmm1, m128*/
vmovups(XmmRegister dst,const Address & src)497 void X86Assembler::vmovups(XmmRegister dst, const Address& src) {
498 DCHECK(CpuHasAVXorAVX2FeatureFlag());
499 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
500 /**Instruction VEX Prefix*/
501 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
502 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
503 /**a REX prefix is necessary only if an instruction references one of the
504 extended registers or uses a 64-bit operand.*/
505 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
506 vvvv_reg,
507 SET_VEX_L_128,
508 SET_VEX_PP_NONE);
509 EmitUint8(ByteZero);
510 EmitUint8(ByteOne);
511 /*Instruction Opcode*/
512 EmitUint8(0x10);
513 /*Instruction Operands*/
514 EmitOperand(dst, src);
515 }
516
movaps(const Address & dst,XmmRegister src)517 void X86Assembler::movaps(const Address& dst, XmmRegister src) {
518 if (CpuHasAVXorAVX2FeatureFlag()) {
519 vmovaps(dst, src);
520 return;
521 }
522 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
523 EmitUint8(0x0F);
524 EmitUint8(0x29);
525 EmitOperand(src, dst);
526 }
527
528 /**VEX.128.0F.WIG 29 /r VMOVAPS m128, xmm1*/
vmovaps(const Address & dst,XmmRegister src)529 void X86Assembler::vmovaps(const Address& dst, XmmRegister src) {
530 DCHECK(CpuHasAVXorAVX2FeatureFlag());
531 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
532 /**Instruction VEX Prefix*/
533 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
534 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
535 /**a REX prefix is necessary only if an instruction references one of the
536 extended registers or uses a 64-bit operand.*/
537 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
538 vvvv_reg,
539 SET_VEX_L_128,
540 SET_VEX_PP_NONE);
541 EmitUint8(ByteZero);
542 EmitUint8(ByteOne);
543 /**Instruction Opcode*/
544 EmitUint8(0x29);
545 /**Instruction Operands*/
546 EmitOperand(src, dst);
547 }
548
movups(const Address & dst,XmmRegister src)549 void X86Assembler::movups(const Address& dst, XmmRegister src) {
550 if (CpuHasAVXorAVX2FeatureFlag()) {
551 vmovups(dst, src);
552 return;
553 }
554 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
555 EmitUint8(0x0F);
556 EmitUint8(0x11);
557 EmitOperand(src, dst);
558 }
559
560 /**VEX.128.0F.WIG 11 /r VMOVUPS m128, xmm1*/
vmovups(const Address & dst,XmmRegister src)561 void X86Assembler::vmovups(const Address& dst, XmmRegister src) {
562 DCHECK(CpuHasAVXorAVX2FeatureFlag());
563 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
564 /**Instruction VEX Prefix*/
565 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
566 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
567 /**a REX prefix is necessary only if an instruction references one of the
568 extended registers or uses a 64-bit operand.*/
569 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
570 vvvv_reg,
571 SET_VEX_L_128,
572 SET_VEX_PP_NONE);
573 EmitUint8(ByteZero);
574 EmitUint8(ByteOne);
575 // Instruction Opcode
576 EmitUint8(0x11);
577 // Instruction Operands
578 EmitOperand(src, dst);
579 }
580
581
movss(XmmRegister dst,const Address & src)582 void X86Assembler::movss(XmmRegister dst, const Address& src) {
583 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
584 EmitUint8(0xF3);
585 EmitUint8(0x0F);
586 EmitUint8(0x10);
587 EmitOperand(dst, src);
588 }
589
590
movss(const Address & dst,XmmRegister src)591 void X86Assembler::movss(const Address& dst, XmmRegister src) {
592 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
593 EmitUint8(0xF3);
594 EmitUint8(0x0F);
595 EmitUint8(0x11);
596 EmitOperand(src, dst);
597 }
598
599
movss(XmmRegister dst,XmmRegister src)600 void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
602 EmitUint8(0xF3);
603 EmitUint8(0x0F);
604 EmitUint8(0x11);
605 EmitXmmRegisterOperand(src, dst);
606 }
607
608
movd(XmmRegister dst,Register src)609 void X86Assembler::movd(XmmRegister dst, Register src) {
610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
611 EmitUint8(0x66);
612 EmitUint8(0x0F);
613 EmitUint8(0x6E);
614 EmitOperand(dst, Operand(src));
615 }
616
617
movd(Register dst,XmmRegister src)618 void X86Assembler::movd(Register dst, XmmRegister src) {
619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
620 EmitUint8(0x66);
621 EmitUint8(0x0F);
622 EmitUint8(0x7E);
623 EmitOperand(src, Operand(dst));
624 }
625
626
addss(XmmRegister dst,XmmRegister src)627 void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0xF3);
630 EmitUint8(0x0F);
631 EmitUint8(0x58);
632 EmitXmmRegisterOperand(dst, src);
633 }
634
635
addss(XmmRegister dst,const Address & src)636 void X86Assembler::addss(XmmRegister dst, const Address& src) {
637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0xF3);
639 EmitUint8(0x0F);
640 EmitUint8(0x58);
641 EmitOperand(dst, src);
642 }
643
644
subss(XmmRegister dst,XmmRegister src)645 void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
646 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
647 EmitUint8(0xF3);
648 EmitUint8(0x0F);
649 EmitUint8(0x5C);
650 EmitXmmRegisterOperand(dst, src);
651 }
652
653
subss(XmmRegister dst,const Address & src)654 void X86Assembler::subss(XmmRegister dst, const Address& src) {
655 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
656 EmitUint8(0xF3);
657 EmitUint8(0x0F);
658 EmitUint8(0x5C);
659 EmitOperand(dst, src);
660 }
661
662
mulss(XmmRegister dst,XmmRegister src)663 void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
664 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
665 EmitUint8(0xF3);
666 EmitUint8(0x0F);
667 EmitUint8(0x59);
668 EmitXmmRegisterOperand(dst, src);
669 }
670
671
mulss(XmmRegister dst,const Address & src)672 void X86Assembler::mulss(XmmRegister dst, const Address& src) {
673 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
674 EmitUint8(0xF3);
675 EmitUint8(0x0F);
676 EmitUint8(0x59);
677 EmitOperand(dst, src);
678 }
679
680
divss(XmmRegister dst,XmmRegister src)681 void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
682 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
683 EmitUint8(0xF3);
684 EmitUint8(0x0F);
685 EmitUint8(0x5E);
686 EmitXmmRegisterOperand(dst, src);
687 }
688
689
divss(XmmRegister dst,const Address & src)690 void X86Assembler::divss(XmmRegister dst, const Address& src) {
691 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
692 EmitUint8(0xF3);
693 EmitUint8(0x0F);
694 EmitUint8(0x5E);
695 EmitOperand(dst, src);
696 }
697
698
addps(XmmRegister dst,XmmRegister src)699 void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
700 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
701 EmitUint8(0x0F);
702 EmitUint8(0x58);
703 EmitXmmRegisterOperand(dst, src);
704 }
705
vaddps(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)706 void X86Assembler::vaddps(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
707 DCHECK(CpuHasAVXorAVX2FeatureFlag());
708 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
709 uint8_t ByteZero = 0x00, ByteOne = 0x00;
710 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
711 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
712 X86ManagedRegister::FromXmmRegister(add_left),
713 SET_VEX_L_128,
714 SET_VEX_PP_NONE);
715 EmitUint8(ByteZero);
716 EmitUint8(ByteOne);
717 EmitUint8(0x58);
718 EmitXmmRegisterOperand(dst, add_right);
719 }
720
subps(XmmRegister dst,XmmRegister src)721 void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
722 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
723 EmitUint8(0x0F);
724 EmitUint8(0x5C);
725 EmitXmmRegisterOperand(dst, src);
726 }
727
vsubps(XmmRegister dst,XmmRegister src1,XmmRegister src2)728 void X86Assembler::vsubps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
729 DCHECK(CpuHasAVXorAVX2FeatureFlag());
730 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
731 uint8_t byte_zero = 0x00, byte_one = 0x00;
732 byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
733 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(src1);
734 byte_one = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_NONE);
735 EmitUint8(byte_zero);
736 EmitUint8(byte_one);
737 EmitUint8(0x5C);
738 EmitXmmRegisterOperand(dst, src2);
739 }
740
mulps(XmmRegister dst,XmmRegister src)741 void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
742 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
743 EmitUint8(0x0F);
744 EmitUint8(0x59);
745 EmitXmmRegisterOperand(dst, src);
746 }
747
vmulps(XmmRegister dst,XmmRegister src1,XmmRegister src2)748 void X86Assembler::vmulps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
749 DCHECK(CpuHasAVXorAVX2FeatureFlag());
750 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
751 uint8_t ByteZero = 0x00, ByteOne = 0x00;
752 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
753 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
754 X86ManagedRegister::FromXmmRegister(src1),
755 SET_VEX_L_128,
756 SET_VEX_PP_NONE);
757 EmitUint8(ByteZero);
758 EmitUint8(ByteOne);
759 EmitUint8(0x59);
760 EmitXmmRegisterOperand(dst, src2);
761 }
762
divps(XmmRegister dst,XmmRegister src)763 void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
764 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
765 EmitUint8(0x0F);
766 EmitUint8(0x5E);
767 EmitXmmRegisterOperand(dst, src);
768 }
769
770
vdivps(XmmRegister dst,XmmRegister src1,XmmRegister src2)771 void X86Assembler::vdivps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
772 DCHECK(CpuHasAVXorAVX2FeatureFlag());
773 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
774 uint8_t ByteZero = 0x00, ByteOne = 0x00;
775 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
776 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
777 X86ManagedRegister::FromXmmRegister(src1),
778 SET_VEX_L_128,
779 SET_VEX_PP_NONE);
780 EmitUint8(ByteZero);
781 EmitUint8(ByteOne);
782 EmitUint8(0x5E);
783 EmitXmmRegisterOperand(dst, src2);
784 }
785
vfmadd213ss(XmmRegister acc,XmmRegister left,XmmRegister right)786 void X86Assembler::vfmadd213ss(XmmRegister acc, XmmRegister left, XmmRegister right) {
787 DCHECK(CpuHasAVXorAVX2FeatureFlag());
788 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
789 uint8_t ByteZero = 0x00, ByteOne = 0x00, ByteTwo = 0x00;
790 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
791 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(left);
792 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
793 /*X=*/ false,
794 /*B=*/ false,
795 SET_VEX_M_0F_38);
796 ByteTwo = EmitVexPrefixByteTwo(/*W=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
797
798 EmitUint8(ByteZero);
799 EmitUint8(ByteOne);
800 EmitUint8(ByteTwo);
801 EmitUint8(0xA9);
802 EmitXmmRegisterOperand(acc, right);
803 }
804
vfmadd213sd(XmmRegister acc,XmmRegister left,XmmRegister right)805 void X86Assembler::vfmadd213sd(XmmRegister acc, XmmRegister left, XmmRegister right) {
806 DCHECK(CpuHasAVXorAVX2FeatureFlag());
807 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
808 uint8_t ByteZero = 0x00, ByteOne = 0x00, ByteTwo = 0x00;
809 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
810 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(left);
811 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
812 /*X=*/ false,
813 /*B=*/ false,
814 SET_VEX_M_0F_38);
815 ByteTwo = EmitVexPrefixByteTwo(/*W=*/ true, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
816
817 EmitUint8(ByteZero);
818 EmitUint8(ByteOne);
819 EmitUint8(ByteTwo);
820 EmitUint8(0xA9);
821 EmitXmmRegisterOperand(acc, right);
822 }
823
movapd(XmmRegister dst,XmmRegister src)824 void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
825 if (CpuHasAVXorAVX2FeatureFlag()) {
826 vmovapd(dst, src);
827 return;
828 }
829 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
830 EmitUint8(0x66);
831 EmitUint8(0x0F);
832 EmitUint8(0x28);
833 EmitXmmRegisterOperand(dst, src);
834 }
835
836 /**VEX.128.66.0F.WIG 28 /r VMOVAPD xmm1, xmm2*/
vmovapd(XmmRegister dst,XmmRegister src)837 void X86Assembler::vmovapd(XmmRegister dst, XmmRegister src) {
838 DCHECK(CpuHasAVXorAVX2FeatureFlag());
839 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
840 /**Instruction VEX Prefix*/
841 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
842 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
843 /**a REX prefix is necessary only if an instruction references one of the
844 extended registers or uses a 64-bit operand.*/
845 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
846 vvvv_reg ,
847 SET_VEX_L_128,
848 SET_VEX_PP_66);
849 EmitUint8(ByteZero);
850 EmitUint8(ByteOne);
851 // Instruction Opcode
852 EmitUint8(0x28);
853 // Instruction Operands
854 EmitXmmRegisterOperand(dst, src);
855 }
856
movapd(XmmRegister dst,const Address & src)857 void X86Assembler::movapd(XmmRegister dst, const Address& src) {
858 if (CpuHasAVXorAVX2FeatureFlag()) {
859 vmovapd(dst, src);
860 return;
861 }
862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
863 EmitUint8(0x66);
864 EmitUint8(0x0F);
865 EmitUint8(0x28);
866 EmitOperand(dst, src);
867 }
868
869 /**VEX.128.66.0F.WIG 28 /r VMOVAPD xmm1, m128*/
vmovapd(XmmRegister dst,const Address & src)870 void X86Assembler::vmovapd(XmmRegister dst, const Address& src) {
871 DCHECK(CpuHasAVXorAVX2FeatureFlag());
872 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
873 /**Instruction VEX Prefix*/
874 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
875 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
876 /**a REX prefix is necessary only if an instruction references one of the
877 extended registers or uses a 64-bit operand.*/
878 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
879 vvvv_reg,
880 SET_VEX_L_128,
881 SET_VEX_PP_66);
882 EmitUint8(ByteZero);
883 EmitUint8(ByteOne);
884 // Instruction Opcode
885 EmitUint8(0x28);
886 // Instruction Operands
887 EmitOperand(dst, src);
888 }
889
movupd(XmmRegister dst,const Address & src)890 void X86Assembler::movupd(XmmRegister dst, const Address& src) {
891 if (CpuHasAVXorAVX2FeatureFlag()) {
892 vmovupd(dst, src);
893 return;
894 }
895 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
896 EmitUint8(0x66);
897 EmitUint8(0x0F);
898 EmitUint8(0x10);
899 EmitOperand(dst, src);
900 }
901
902 /**VEX.128.66.0F.WIG 10 /r VMOVUPD xmm1, m128*/
vmovupd(XmmRegister dst,const Address & src)903 void X86Assembler::vmovupd(XmmRegister dst, const Address& src) {
904 DCHECK(CpuHasAVXorAVX2FeatureFlag());
905 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
906 /**Instruction VEX Prefix*/
907 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
908 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
909 /**a REX prefix is necessary only if an instruction references one of the
910 extended registers or uses a 64-bit operand.*/
911 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
912 vvvv_reg,
913 SET_VEX_L_128,
914 SET_VEX_PP_66);
915 EmitUint8(ByteZero);
916 EmitUint8(ByteOne);
917 // Instruction Opcode
918 EmitUint8(0x10);
919 // Instruction Operands
920 EmitOperand(dst, src);
921 }
922
923
movapd(const Address & dst,XmmRegister src)924 void X86Assembler::movapd(const Address& dst, XmmRegister src) {
925 if (CpuHasAVXorAVX2FeatureFlag()) {
926 vmovapd(dst, src);
927 return;
928 }
929 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
930 EmitUint8(0x66);
931 EmitUint8(0x0F);
932 EmitUint8(0x29);
933 EmitOperand(src, dst);
934 }
935
936 /**VEX.128.66.0F.WIG 29 /r VMOVAPD m128, xmm1 */
vmovapd(const Address & dst,XmmRegister src)937 void X86Assembler::vmovapd(const Address& dst, XmmRegister src) {
938 DCHECK(CpuHasAVXorAVX2FeatureFlag());
939 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
940 /**Instruction VEX Prefix */
941 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
942 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
943 /**a REX prefix is necessary only if an instruction references one of the
944 extended registers or uses a 64-bit operand.*/
945 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
946 vvvv_reg,
947 SET_VEX_L_128,
948 SET_VEX_PP_66);
949 EmitUint8(ByteZero);
950 EmitUint8(ByteOne);
951 // Instruction Opcode
952 EmitUint8(0x29);
953 // Instruction Operands
954 EmitOperand(src, dst);
955 }
956
movupd(const Address & dst,XmmRegister src)957 void X86Assembler::movupd(const Address& dst, XmmRegister src) {
958 if (CpuHasAVXorAVX2FeatureFlag()) {
959 vmovupd(dst, src);
960 return;
961 }
962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
963 EmitUint8(0x66);
964 EmitUint8(0x0F);
965 EmitUint8(0x11);
966 EmitOperand(src, dst);
967 }
968
969 /**VEX.128.66.0F.WIG 11 /r VMOVUPD m128, xmm1 */
vmovupd(const Address & dst,XmmRegister src)970 void X86Assembler::vmovupd(const Address& dst, XmmRegister src) {
971 DCHECK(CpuHasAVXorAVX2FeatureFlag());
972 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
973 /**Instruction VEX Prefix */
974 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
975 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
976 /**a REX prefix is necessary only if an instruction references one of the
977 extended registers or uses a 64-bit operand.**/
978 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
979 vvvv_reg,
980 SET_VEX_L_128,
981 SET_VEX_PP_66);
982 EmitUint8(ByteZero);
983 EmitUint8(ByteOne);
984 // Instruction Opcode
985 EmitUint8(0x11);
986 // Instruction Operands
987 EmitOperand(src, dst);
988 }
989
flds(const Address & src)990 void X86Assembler::flds(const Address& src) {
991 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
992 EmitUint8(0xD9);
993 EmitOperand(0, src);
994 }
995
996
fsts(const Address & dst)997 void X86Assembler::fsts(const Address& dst) {
998 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
999 EmitUint8(0xD9);
1000 EmitOperand(2, dst);
1001 }
1002
1003
fstps(const Address & dst)1004 void X86Assembler::fstps(const Address& dst) {
1005 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1006 EmitUint8(0xD9);
1007 EmitOperand(3, dst);
1008 }
1009
1010
movsd(XmmRegister dst,const Address & src)1011 void X86Assembler::movsd(XmmRegister dst, const Address& src) {
1012 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1013 EmitUint8(0xF2);
1014 EmitUint8(0x0F);
1015 EmitUint8(0x10);
1016 EmitOperand(dst, src);
1017 }
1018
1019
movsd(const Address & dst,XmmRegister src)1020 void X86Assembler::movsd(const Address& dst, XmmRegister src) {
1021 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1022 EmitUint8(0xF2);
1023 EmitUint8(0x0F);
1024 EmitUint8(0x11);
1025 EmitOperand(src, dst);
1026 }
1027
1028
movsd(XmmRegister dst,XmmRegister src)1029 void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
1030 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1031 EmitUint8(0xF2);
1032 EmitUint8(0x0F);
1033 EmitUint8(0x11);
1034 EmitXmmRegisterOperand(src, dst);
1035 }
1036
1037
movhpd(XmmRegister dst,const Address & src)1038 void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
1039 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1040 EmitUint8(0x66);
1041 EmitUint8(0x0F);
1042 EmitUint8(0x16);
1043 EmitOperand(dst, src);
1044 }
1045
1046
movhpd(const Address & dst,XmmRegister src)1047 void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
1048 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1049 EmitUint8(0x66);
1050 EmitUint8(0x0F);
1051 EmitUint8(0x17);
1052 EmitOperand(src, dst);
1053 }
1054
1055
addsd(XmmRegister dst,XmmRegister src)1056 void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
1057 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1058 EmitUint8(0xF2);
1059 EmitUint8(0x0F);
1060 EmitUint8(0x58);
1061 EmitXmmRegisterOperand(dst, src);
1062 }
1063
1064
addsd(XmmRegister dst,const Address & src)1065 void X86Assembler::addsd(XmmRegister dst, const Address& src) {
1066 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1067 EmitUint8(0xF2);
1068 EmitUint8(0x0F);
1069 EmitUint8(0x58);
1070 EmitOperand(dst, src);
1071 }
1072
1073
subsd(XmmRegister dst,XmmRegister src)1074 void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
1075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1076 EmitUint8(0xF2);
1077 EmitUint8(0x0F);
1078 EmitUint8(0x5C);
1079 EmitXmmRegisterOperand(dst, src);
1080 }
1081
1082
subsd(XmmRegister dst,const Address & src)1083 void X86Assembler::subsd(XmmRegister dst, const Address& src) {
1084 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1085 EmitUint8(0xF2);
1086 EmitUint8(0x0F);
1087 EmitUint8(0x5C);
1088 EmitOperand(dst, src);
1089 }
1090
1091
mulsd(XmmRegister dst,XmmRegister src)1092 void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
1093 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1094 EmitUint8(0xF2);
1095 EmitUint8(0x0F);
1096 EmitUint8(0x59);
1097 EmitXmmRegisterOperand(dst, src);
1098 }
1099
1100
mulsd(XmmRegister dst,const Address & src)1101 void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
1102 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1103 EmitUint8(0xF2);
1104 EmitUint8(0x0F);
1105 EmitUint8(0x59);
1106 EmitOperand(dst, src);
1107 }
1108
1109
divsd(XmmRegister dst,XmmRegister src)1110 void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
1111 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1112 EmitUint8(0xF2);
1113 EmitUint8(0x0F);
1114 EmitUint8(0x5E);
1115 EmitXmmRegisterOperand(dst, src);
1116 }
1117
1118
divsd(XmmRegister dst,const Address & src)1119 void X86Assembler::divsd(XmmRegister dst, const Address& src) {
1120 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1121 EmitUint8(0xF2);
1122 EmitUint8(0x0F);
1123 EmitUint8(0x5E);
1124 EmitOperand(dst, src);
1125 }
1126
1127
addpd(XmmRegister dst,XmmRegister src)1128 void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
1129 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1130 EmitUint8(0x66);
1131 EmitUint8(0x0F);
1132 EmitUint8(0x58);
1133 EmitXmmRegisterOperand(dst, src);
1134 }
1135
1136
vaddpd(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1137 void X86Assembler::vaddpd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1138 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1139 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1140 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1141 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1142 X86ManagedRegister::FromXmmRegister(add_left),
1143 SET_VEX_L_128,
1144 SET_VEX_PP_66);
1145 EmitUint8(ByteZero);
1146 EmitUint8(ByteOne);
1147 EmitUint8(0x58);
1148 EmitXmmRegisterOperand(dst, add_right);
1149 }
1150
1151
subpd(XmmRegister dst,XmmRegister src)1152 void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
1153 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1154 EmitUint8(0x66);
1155 EmitUint8(0x0F);
1156 EmitUint8(0x5C);
1157 EmitXmmRegisterOperand(dst, src);
1158 }
1159
1160
vsubpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)1161 void X86Assembler::vsubpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1163 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1164 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form*/ true);
1165 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1166 X86ManagedRegister::FromXmmRegister(src1),
1167 SET_VEX_L_128,
1168 SET_VEX_PP_66);
1169 EmitUint8(ByteZero);
1170 EmitUint8(ByteOne);
1171 EmitUint8(0x5C);
1172 EmitXmmRegisterOperand(dst, src2);
1173 }
1174
mulpd(XmmRegister dst,XmmRegister src)1175 void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
1176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1177 EmitUint8(0x66);
1178 EmitUint8(0x0F);
1179 EmitUint8(0x59);
1180 EmitXmmRegisterOperand(dst, src);
1181 }
1182
vmulpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)1183 void X86Assembler::vmulpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1184 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1185 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1186 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1187 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1188 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1189 X86ManagedRegister::FromXmmRegister(src1),
1190 SET_VEX_L_128,
1191 SET_VEX_PP_66);
1192 EmitUint8(ByteZero);
1193 EmitUint8(ByteOne);
1194 EmitUint8(0x59);
1195 EmitXmmRegisterOperand(dst, src2);
1196 }
1197
divpd(XmmRegister dst,XmmRegister src)1198 void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
1199 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1200 EmitUint8(0x66);
1201 EmitUint8(0x0F);
1202 EmitUint8(0x5E);
1203 EmitXmmRegisterOperand(dst, src);
1204 }
1205
vdivpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)1206 void X86Assembler::vdivpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1207 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1208 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1209 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1210 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1211 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1212 X86ManagedRegister::FromXmmRegister(src1),
1213 SET_VEX_L_128,
1214 SET_VEX_PP_66);
1215 EmitUint8(ByteZero);
1216 EmitUint8(ByteOne);
1217 EmitUint8(0x5E);
1218 EmitXmmRegisterOperand(dst, src2);
1219 }
1220
movdqa(XmmRegister dst,XmmRegister src)1221 void X86Assembler::movdqa(XmmRegister dst, XmmRegister src) {
1222 if (CpuHasAVXorAVX2FeatureFlag()) {
1223 vmovdqa(dst, src);
1224 return;
1225 }
1226 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1227 EmitUint8(0x66);
1228 EmitUint8(0x0F);
1229 EmitUint8(0x6F);
1230 EmitXmmRegisterOperand(dst, src);
1231 }
1232
1233 /**VEX.128.66.0F.WIG 6F /r VMOVDQA xmm1, xmm2 */
vmovdqa(XmmRegister dst,XmmRegister src)1234 void X86Assembler::vmovdqa(XmmRegister dst, XmmRegister src) {
1235 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1236 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1237 /**Instruction VEX Prefix */
1238 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1239 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1240 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1241 vvvv_reg,
1242 SET_VEX_L_128,
1243 SET_VEX_PP_66);
1244 EmitUint8(ByteZero);
1245 EmitUint8(ByteOne);
1246 // Instruction Opcode
1247 EmitUint8(0x6F);
1248 // Instruction Operands
1249 EmitXmmRegisterOperand(dst, src);
1250 }
1251
movdqa(XmmRegister dst,const Address & src)1252 void X86Assembler::movdqa(XmmRegister dst, const Address& src) {
1253 if (CpuHasAVXorAVX2FeatureFlag()) {
1254 vmovdqa(dst, src);
1255 return;
1256 }
1257 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1258 EmitUint8(0x66);
1259 EmitUint8(0x0F);
1260 EmitUint8(0x6F);
1261 EmitOperand(dst, src);
1262 }
1263
1264 /**VEX.128.66.0F.WIG 6F /r VMOVDQA xmm1, m128 */
vmovdqa(XmmRegister dst,const Address & src)1265 void X86Assembler::vmovdqa(XmmRegister dst, const Address& src) {
1266 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1267 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1268 /**Instruction VEX Prefix */
1269 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1270 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1271 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1272 vvvv_reg,
1273 SET_VEX_L_128,
1274 SET_VEX_PP_66);
1275 EmitUint8(ByteZero);
1276 EmitUint8(ByteOne);
1277 // Instruction Opcode
1278 EmitUint8(0x6F);
1279 // Instruction Operands
1280 EmitOperand(dst, src);
1281 }
1282
movdqu(XmmRegister dst,const Address & src)1283 void X86Assembler::movdqu(XmmRegister dst, const Address& src) {
1284 if (CpuHasAVXorAVX2FeatureFlag()) {
1285 vmovdqu(dst, src);
1286 return;
1287 }
1288 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1289 EmitUint8(0xF3);
1290 EmitUint8(0x0F);
1291 EmitUint8(0x6F);
1292 EmitOperand(dst, src);
1293 }
1294
1295 /**VEX.128.F3.0F.WIG 6F /r VMOVDQU xmm1, m128 */
vmovdqu(XmmRegister dst,const Address & src)1296 void X86Assembler::vmovdqu(XmmRegister dst, const Address& src) {
1297 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1298 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1299 /**Instruction VEX Prefix */
1300 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1301 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1302 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1303 vvvv_reg,
1304 SET_VEX_L_128,
1305 SET_VEX_PP_F3);
1306 EmitUint8(ByteZero);
1307 EmitUint8(ByteOne);
1308 // Instruction Opcode
1309 EmitUint8(0x6F);
1310 // Instruction Operands
1311 EmitOperand(dst, src);
1312 }
1313
movdqa(const Address & dst,XmmRegister src)1314 void X86Assembler::movdqa(const Address& dst, XmmRegister src) {
1315 if (CpuHasAVXorAVX2FeatureFlag()) {
1316 vmovdqa(dst, src);
1317 return;
1318 }
1319 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1320 EmitUint8(0x66);
1321 EmitUint8(0x0F);
1322 EmitUint8(0x7F);
1323 EmitOperand(src, dst);
1324 }
1325
1326 /**VEX.128.66.0F.WIG 7F /r VMOVDQA m128, xmm1 */
vmovdqa(const Address & dst,XmmRegister src)1327 void X86Assembler::vmovdqa(const Address& dst, XmmRegister src) {
1328 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1329 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1330 /**Instruction VEX Prefix */
1331 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1332 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1333 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1334 vvvv_reg,
1335 SET_VEX_L_128,
1336 SET_VEX_PP_66);
1337 EmitUint8(ByteZero);
1338 EmitUint8(ByteOne);
1339 // Instruction Opcode
1340 EmitUint8(0x7F);
1341 // Instruction Operands
1342 EmitOperand(src, dst);
1343 }
1344
1345
movdqu(const Address & dst,XmmRegister src)1346 void X86Assembler::movdqu(const Address& dst, XmmRegister src) {
1347 if (CpuHasAVXorAVX2FeatureFlag()) {
1348 vmovdqu(dst, src);
1349 return;
1350 }
1351 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1352 EmitUint8(0xF3);
1353 EmitUint8(0x0F);
1354 EmitUint8(0x7F);
1355 EmitOperand(src, dst);
1356 }
1357
1358 /**VEX.128.F3.0F.WIG 7F /r VMOVDQU m128, xmm1 */
vmovdqu(const Address & dst,XmmRegister src)1359 void X86Assembler::vmovdqu(const Address& dst, XmmRegister src) {
1360 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1361 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1362 // Instruction VEX Prefix
1363 uint8_t ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1364 X86ManagedRegister vvvv_reg = ManagedRegister::NoRegister().AsX86();
1365 uint8_t ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1366 vvvv_reg,
1367 SET_VEX_L_128,
1368 SET_VEX_PP_F3);
1369 EmitUint8(ByteZero);
1370 EmitUint8(ByteOne);
1371 // Instruction Opcode
1372 EmitUint8(0x7F);
1373 // Instruction Operands
1374 EmitOperand(src, dst);
1375 }
1376
paddb(XmmRegister dst,XmmRegister src)1377 void X86Assembler::paddb(XmmRegister dst, XmmRegister src) {
1378 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1379 EmitUint8(0x66);
1380 EmitUint8(0x0F);
1381 EmitUint8(0xFC);
1382 EmitXmmRegisterOperand(dst, src);
1383 }
1384
vpaddb(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1385 void X86Assembler::vpaddb(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1386 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1387 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1388 uint8_t ByteOne = 0x00, ByteZero = 0x00;
1389 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1390 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1391 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1392 EmitUint8(ByteZero);
1393 EmitUint8(ByteOne);
1394 EmitUint8(0xFC);
1395 EmitXmmRegisterOperand(dst, add_right);
1396 }
1397
psubb(XmmRegister dst,XmmRegister src)1398 void X86Assembler::psubb(XmmRegister dst, XmmRegister src) {
1399 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1400 EmitUint8(0x66);
1401 EmitUint8(0x0F);
1402 EmitUint8(0xF8);
1403 EmitXmmRegisterOperand(dst, src);
1404 }
1405
vpsubb(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1406 void X86Assembler::vpsubb(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1407 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1408 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1409 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1410 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1411 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1412 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1413 EmitUint8(ByteZero);
1414 EmitUint8(ByteOne);
1415 EmitUint8(0xF8);
1416 EmitXmmRegisterOperand(dst, add_right);
1417 }
1418
paddw(XmmRegister dst,XmmRegister src)1419 void X86Assembler::paddw(XmmRegister dst, XmmRegister src) {
1420 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1421 EmitUint8(0x66);
1422 EmitUint8(0x0F);
1423 EmitUint8(0xFD);
1424 EmitXmmRegisterOperand(dst, src);
1425 }
1426
vpaddw(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1427 void X86Assembler::vpaddw(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1428 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1429 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1430 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1431 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1432 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1433 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1434 EmitUint8(ByteZero);
1435 EmitUint8(ByteOne);
1436 EmitUint8(0xFD);
1437 EmitXmmRegisterOperand(dst, add_right);
1438 }
1439
psubw(XmmRegister dst,XmmRegister src)1440 void X86Assembler::psubw(XmmRegister dst, XmmRegister src) {
1441 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1442 EmitUint8(0x66);
1443 EmitUint8(0x0F);
1444 EmitUint8(0xF9);
1445 EmitXmmRegisterOperand(dst, src);
1446 }
1447
vpsubw(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1448 void X86Assembler::vpsubw(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1449 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1450 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1451 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1452 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1453 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1454 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1455 EmitUint8(ByteZero);
1456 EmitUint8(ByteOne);
1457 EmitUint8(0xF9);
1458 EmitXmmRegisterOperand(dst, add_right);
1459 }
1460
pmullw(XmmRegister dst,XmmRegister src)1461 void X86Assembler::pmullw(XmmRegister dst, XmmRegister src) {
1462 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1463 EmitUint8(0x66);
1464 EmitUint8(0x0F);
1465 EmitUint8(0xD5);
1466 EmitXmmRegisterOperand(dst, src);
1467 }
1468
1469
paddd(XmmRegister dst,XmmRegister src)1470 void X86Assembler::paddd(XmmRegister dst, XmmRegister src) {
1471 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1472 EmitUint8(0x66);
1473 EmitUint8(0x0F);
1474 EmitUint8(0xFE);
1475 EmitXmmRegisterOperand(dst, src);
1476 }
1477
vpaddd(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1478 void X86Assembler::vpaddd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1479 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1480 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1481 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1482 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1483 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1484 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1485 EmitUint8(ByteZero);
1486 EmitUint8(ByteOne);
1487 EmitUint8(0xFE);
1488 EmitXmmRegisterOperand(dst, add_right);
1489 }
1490
psubd(XmmRegister dst,XmmRegister src)1491 void X86Assembler::psubd(XmmRegister dst, XmmRegister src) {
1492 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1493 EmitUint8(0x66);
1494 EmitUint8(0x0F);
1495 EmitUint8(0xFA);
1496 EmitXmmRegisterOperand(dst, src);
1497 }
1498
1499
vpsubd(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1500 void X86Assembler::vpsubd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1501 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1502 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1503 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1504 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1505 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1506 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1507 EmitUint8(ByteZero);
1508 EmitUint8(ByteOne);
1509 EmitUint8(0xFA);
1510 EmitXmmRegisterOperand(dst, add_right);
1511 }
1512
1513
pmulld(XmmRegister dst,XmmRegister src)1514 void X86Assembler::pmulld(XmmRegister dst, XmmRegister src) {
1515 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1516 EmitUint8(0x66);
1517 EmitUint8(0x0F);
1518 EmitUint8(0x38);
1519 EmitUint8(0x40);
1520 EmitXmmRegisterOperand(dst, src);
1521 }
1522
vpmulld(XmmRegister dst,XmmRegister src1,XmmRegister src2)1523 void X86Assembler::vpmulld(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1524 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1525 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1526 uint8_t ByteZero = 0x00, ByteOne = 0x00, ByteTwo = 0x00;
1527 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
1528 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1529 /*X=*/ false,
1530 /*B=*/ false,
1531 SET_VEX_M_0F_38);
1532 ByteTwo = EmitVexPrefixByteTwo(/*W=*/ false,
1533 X86ManagedRegister::FromXmmRegister(src1),
1534 SET_VEX_L_128,
1535 SET_VEX_PP_66);
1536 EmitUint8(ByteZero);
1537 EmitUint8(ByteOne);
1538 EmitUint8(ByteTwo);
1539 EmitUint8(0x40);
1540 EmitRegisterOperand(dst, src2);
1541 }
1542
vpmullw(XmmRegister dst,XmmRegister src1,XmmRegister src2)1543 void X86Assembler::vpmullw(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1544 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1545 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1546 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1547 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1548 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1549 X86ManagedRegister::FromXmmRegister(src1),
1550 SET_VEX_L_128,
1551 SET_VEX_PP_66);
1552 EmitUint8(ByteZero);
1553 EmitUint8(ByteOne);
1554 EmitUint8(0xD5);
1555 EmitRegisterOperand(dst, src2);
1556 }
1557
paddq(XmmRegister dst,XmmRegister src)1558 void X86Assembler::paddq(XmmRegister dst, XmmRegister src) {
1559 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1560 EmitUint8(0x66);
1561 EmitUint8(0x0F);
1562 EmitUint8(0xD4);
1563 EmitXmmRegisterOperand(dst, src);
1564 }
1565
vpaddq(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1566 void X86Assembler::vpaddq(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1567 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1568 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1569 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1570 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1571 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1572 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1573 EmitUint8(ByteZero);
1574 EmitUint8(ByteOne);
1575 EmitUint8(0xD4);
1576 EmitXmmRegisterOperand(dst, add_right);
1577 }
1578
1579
psubq(XmmRegister dst,XmmRegister src)1580 void X86Assembler::psubq(XmmRegister dst, XmmRegister src) {
1581 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1582 EmitUint8(0x66);
1583 EmitUint8(0x0F);
1584 EmitUint8(0xFB);
1585 EmitXmmRegisterOperand(dst, src);
1586 }
1587
vpsubq(XmmRegister dst,XmmRegister add_left,XmmRegister add_right)1588 void X86Assembler::vpsubq(XmmRegister dst, XmmRegister add_left, XmmRegister add_right) {
1589 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1590 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1591 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1592 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1593 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(add_left);
1594 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
1595 EmitUint8(ByteZero);
1596 EmitUint8(ByteOne);
1597 EmitUint8(0xFB);
1598 EmitXmmRegisterOperand(dst, add_right);
1599 }
1600
paddusb(XmmRegister dst,XmmRegister src)1601 void X86Assembler::paddusb(XmmRegister dst, XmmRegister src) {
1602 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1603 EmitUint8(0x66);
1604 EmitUint8(0x0F);
1605 EmitUint8(0xDC);
1606 EmitXmmRegisterOperand(dst, src);
1607 }
1608
1609
paddsb(XmmRegister dst,XmmRegister src)1610 void X86Assembler::paddsb(XmmRegister dst, XmmRegister src) {
1611 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1612 EmitUint8(0x66);
1613 EmitUint8(0x0F);
1614 EmitUint8(0xEC);
1615 EmitXmmRegisterOperand(dst, src);
1616 }
1617
1618
paddusw(XmmRegister dst,XmmRegister src)1619 void X86Assembler::paddusw(XmmRegister dst, XmmRegister src) {
1620 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1621 EmitUint8(0x66);
1622 EmitUint8(0x0F);
1623 EmitUint8(0xDD);
1624 EmitXmmRegisterOperand(dst, src);
1625 }
1626
1627
paddsw(XmmRegister dst,XmmRegister src)1628 void X86Assembler::paddsw(XmmRegister dst, XmmRegister src) {
1629 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1630 EmitUint8(0x66);
1631 EmitUint8(0x0F);
1632 EmitUint8(0xED);
1633 EmitXmmRegisterOperand(dst, src);
1634 }
1635
1636
psubusb(XmmRegister dst,XmmRegister src)1637 void X86Assembler::psubusb(XmmRegister dst, XmmRegister src) {
1638 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1639 EmitUint8(0x66);
1640 EmitUint8(0x0F);
1641 EmitUint8(0xD8);
1642 EmitXmmRegisterOperand(dst, src);
1643 }
1644
1645
psubsb(XmmRegister dst,XmmRegister src)1646 void X86Assembler::psubsb(XmmRegister dst, XmmRegister src) {
1647 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1648 EmitUint8(0x66);
1649 EmitUint8(0x0F);
1650 EmitUint8(0xE8);
1651 EmitXmmRegisterOperand(dst, src);
1652 }
1653
1654
psubusw(XmmRegister dst,XmmRegister src)1655 void X86Assembler::psubusw(XmmRegister dst, XmmRegister src) {
1656 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1657 EmitUint8(0x66);
1658 EmitUint8(0x0F);
1659 EmitUint8(0xD9);
1660 EmitXmmRegisterOperand(dst, src);
1661 }
1662
1663
psubsw(XmmRegister dst,XmmRegister src)1664 void X86Assembler::psubsw(XmmRegister dst, XmmRegister src) {
1665 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1666 EmitUint8(0x66);
1667 EmitUint8(0x0F);
1668 EmitUint8(0xE9);
1669 EmitXmmRegisterOperand(dst, src);
1670 }
1671
1672
cvtsi2ss(XmmRegister dst,Register src)1673 void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
1674 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1675 EmitUint8(0xF3);
1676 EmitUint8(0x0F);
1677 EmitUint8(0x2A);
1678 EmitOperand(dst, Operand(src));
1679 }
1680
1681
cvtsi2sd(XmmRegister dst,Register src)1682 void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
1683 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1684 EmitUint8(0xF2);
1685 EmitUint8(0x0F);
1686 EmitUint8(0x2A);
1687 EmitOperand(dst, Operand(src));
1688 }
1689
1690
cvtss2si(Register dst,XmmRegister src)1691 void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
1692 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1693 EmitUint8(0xF3);
1694 EmitUint8(0x0F);
1695 EmitUint8(0x2D);
1696 EmitXmmRegisterOperand(dst, src);
1697 }
1698
1699
cvtss2sd(XmmRegister dst,XmmRegister src)1700 void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
1701 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1702 EmitUint8(0xF3);
1703 EmitUint8(0x0F);
1704 EmitUint8(0x5A);
1705 EmitXmmRegisterOperand(dst, src);
1706 }
1707
1708
cvtsd2si(Register dst,XmmRegister src)1709 void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
1710 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1711 EmitUint8(0xF2);
1712 EmitUint8(0x0F);
1713 EmitUint8(0x2D);
1714 EmitXmmRegisterOperand(dst, src);
1715 }
1716
1717
cvttss2si(Register dst,XmmRegister src)1718 void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
1719 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1720 EmitUint8(0xF3);
1721 EmitUint8(0x0F);
1722 EmitUint8(0x2C);
1723 EmitXmmRegisterOperand(dst, src);
1724 }
1725
1726
cvttsd2si(Register dst,XmmRegister src)1727 void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
1728 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1729 EmitUint8(0xF2);
1730 EmitUint8(0x0F);
1731 EmitUint8(0x2C);
1732 EmitXmmRegisterOperand(dst, src);
1733 }
1734
1735
cvtsd2ss(XmmRegister dst,XmmRegister src)1736 void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
1737 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1738 EmitUint8(0xF2);
1739 EmitUint8(0x0F);
1740 EmitUint8(0x5A);
1741 EmitXmmRegisterOperand(dst, src);
1742 }
1743
1744
cvtdq2ps(XmmRegister dst,XmmRegister src)1745 void X86Assembler::cvtdq2ps(XmmRegister dst, XmmRegister src) {
1746 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1747 EmitUint8(0x0F);
1748 EmitUint8(0x5B);
1749 EmitXmmRegisterOperand(dst, src);
1750 }
1751
1752
cvtdq2pd(XmmRegister dst,XmmRegister src)1753 void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
1754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1755 EmitUint8(0xF3);
1756 EmitUint8(0x0F);
1757 EmitUint8(0xE6);
1758 EmitXmmRegisterOperand(dst, src);
1759 }
1760
1761
comiss(XmmRegister a,XmmRegister b)1762 void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
1763 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1764 EmitUint8(0x0F);
1765 EmitUint8(0x2F);
1766 EmitXmmRegisterOperand(a, b);
1767 }
1768
1769
comiss(XmmRegister a,const Address & b)1770 void X86Assembler::comiss(XmmRegister a, const Address& b) {
1771 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1772 EmitUint8(0x0F);
1773 EmitUint8(0x2F);
1774 EmitOperand(a, b);
1775 }
1776
1777
comisd(XmmRegister a,XmmRegister b)1778 void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
1779 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1780 EmitUint8(0x66);
1781 EmitUint8(0x0F);
1782 EmitUint8(0x2F);
1783 EmitXmmRegisterOperand(a, b);
1784 }
1785
1786
comisd(XmmRegister a,const Address & b)1787 void X86Assembler::comisd(XmmRegister a, const Address& b) {
1788 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1789 EmitUint8(0x66);
1790 EmitUint8(0x0F);
1791 EmitUint8(0x2F);
1792 EmitOperand(a, b);
1793 }
1794
1795
ucomiss(XmmRegister a,XmmRegister b)1796 void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
1797 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1798 EmitUint8(0x0F);
1799 EmitUint8(0x2E);
1800 EmitXmmRegisterOperand(a, b);
1801 }
1802
1803
ucomiss(XmmRegister a,const Address & b)1804 void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
1805 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1806 EmitUint8(0x0F);
1807 EmitUint8(0x2E);
1808 EmitOperand(a, b);
1809 }
1810
1811
ucomisd(XmmRegister a,XmmRegister b)1812 void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
1813 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1814 EmitUint8(0x66);
1815 EmitUint8(0x0F);
1816 EmitUint8(0x2E);
1817 EmitXmmRegisterOperand(a, b);
1818 }
1819
1820
ucomisd(XmmRegister a,const Address & b)1821 void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
1822 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1823 EmitUint8(0x66);
1824 EmitUint8(0x0F);
1825 EmitUint8(0x2E);
1826 EmitOperand(a, b);
1827 }
1828
1829
roundsd(XmmRegister dst,XmmRegister src,const Immediate & imm)1830 void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1831 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1832 EmitUint8(0x66);
1833 EmitUint8(0x0F);
1834 EmitUint8(0x3A);
1835 EmitUint8(0x0B);
1836 EmitXmmRegisterOperand(dst, src);
1837 EmitUint8(imm.value());
1838 }
1839
1840
roundss(XmmRegister dst,XmmRegister src,const Immediate & imm)1841 void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1842 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1843 EmitUint8(0x66);
1844 EmitUint8(0x0F);
1845 EmitUint8(0x3A);
1846 EmitUint8(0x0A);
1847 EmitXmmRegisterOperand(dst, src);
1848 EmitUint8(imm.value());
1849 }
1850
1851
sqrtsd(XmmRegister dst,XmmRegister src)1852 void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
1853 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1854 EmitUint8(0xF2);
1855 EmitUint8(0x0F);
1856 EmitUint8(0x51);
1857 EmitXmmRegisterOperand(dst, src);
1858 }
1859
1860
sqrtss(XmmRegister dst,XmmRegister src)1861 void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
1862 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1863 EmitUint8(0xF3);
1864 EmitUint8(0x0F);
1865 EmitUint8(0x51);
1866 EmitXmmRegisterOperand(dst, src);
1867 }
1868
1869
xorpd(XmmRegister dst,const Address & src)1870 void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
1871 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1872 EmitUint8(0x66);
1873 EmitUint8(0x0F);
1874 EmitUint8(0x57);
1875 EmitOperand(dst, src);
1876 }
1877
1878
xorpd(XmmRegister dst,XmmRegister src)1879 void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
1880 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1881 EmitUint8(0x66);
1882 EmitUint8(0x0F);
1883 EmitUint8(0x57);
1884 EmitXmmRegisterOperand(dst, src);
1885 }
1886
1887
xorps(XmmRegister dst,const Address & src)1888 void X86Assembler::xorps(XmmRegister dst, const Address& src) {
1889 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1890 EmitUint8(0x0F);
1891 EmitUint8(0x57);
1892 EmitOperand(dst, src);
1893 }
1894
1895
xorps(XmmRegister dst,XmmRegister src)1896 void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
1897 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1898 EmitUint8(0x0F);
1899 EmitUint8(0x57);
1900 EmitXmmRegisterOperand(dst, src);
1901 }
1902
1903
pxor(XmmRegister dst,XmmRegister src)1904 void X86Assembler::pxor(XmmRegister dst, XmmRegister src) {
1905 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1906 EmitUint8(0x66);
1907 EmitUint8(0x0F);
1908 EmitUint8(0xEF);
1909 EmitXmmRegisterOperand(dst, src);
1910 }
1911
1912 /* VEX.128.66.0F.WIG EF /r VPXOR xmm1, xmm2, xmm3/m128 */
vpxor(XmmRegister dst,XmmRegister src1,XmmRegister src2)1913 void X86Assembler::vpxor(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1914 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1915 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1916 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1917 /* Instruction VEX Prefix */
1918 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1919 /* REX prefix is necessary only if an instruction references one of extended
1920 registers or uses a 64-bit operand. */
1921 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1922 X86ManagedRegister::FromXmmRegister(src1),
1923 SET_VEX_L_128,
1924 SET_VEX_PP_66);
1925 EmitUint8(ByteZero);
1926 EmitUint8(ByteOne);
1927 // Instruction Opcode
1928 EmitUint8(0xEF);
1929 // Instruction Operands
1930 EmitXmmRegisterOperand(dst, src2);
1931 }
1932
1933 /* VEX.128.0F.WIG 57 /r VXORPS xmm1,xmm2, xmm3/m128 */
vxorps(XmmRegister dst,XmmRegister src1,XmmRegister src2)1934 void X86Assembler::vxorps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1935 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1936 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1937 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1938 /* Instruction VEX Prefix */
1939 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1940 /* REX prefix is necessary only if an instruction references one of extended
1941 registers or uses a 64-bit operand. */
1942 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1943 X86ManagedRegister::FromXmmRegister(src1),
1944 SET_VEX_L_128,
1945 SET_VEX_PP_NONE);
1946 EmitUint8(ByteZero);
1947 EmitUint8(ByteOne);
1948 // Instruction Opcode
1949 EmitUint8(0x57);
1950 // Instruction Operands
1951 EmitXmmRegisterOperand(dst, src2);
1952 }
1953
1954 /* VEX.128.66.0F.WIG 57 /r VXORPD xmm1,xmm2, xmm3/m128 */
vxorpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)1955 void X86Assembler::vxorpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
1956 DCHECK(CpuHasAVXorAVX2FeatureFlag());
1957 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1958 uint8_t ByteZero = 0x00, ByteOne = 0x00;
1959 /* Instruction VEX Prefix */
1960 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
1961 /* REX prefix is necessary only if an instruction references one of extended
1962 registers or uses a 64-bit operand. */
1963 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
1964 X86ManagedRegister::FromXmmRegister(src1),
1965 SET_VEX_L_128,
1966 SET_VEX_PP_66);
1967 EmitUint8(ByteZero);
1968 EmitUint8(ByteOne);
1969 // Instruction Opcode
1970 EmitUint8(0x57);
1971 // Instruction Operands
1972 EmitXmmRegisterOperand(dst, src2);
1973 }
1974
andpd(XmmRegister dst,XmmRegister src)1975 void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1976 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1977 EmitUint8(0x66);
1978 EmitUint8(0x0F);
1979 EmitUint8(0x54);
1980 EmitXmmRegisterOperand(dst, src);
1981 }
1982
1983
andpd(XmmRegister dst,const Address & src)1984 void X86Assembler::andpd(XmmRegister dst, const Address& src) {
1985 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1986 EmitUint8(0x66);
1987 EmitUint8(0x0F);
1988 EmitUint8(0x54);
1989 EmitOperand(dst, src);
1990 }
1991
1992
andps(XmmRegister dst,XmmRegister src)1993 void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
1994 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1995 EmitUint8(0x0F);
1996 EmitUint8(0x54);
1997 EmitXmmRegisterOperand(dst, src);
1998 }
1999
2000
andps(XmmRegister dst,const Address & src)2001 void X86Assembler::andps(XmmRegister dst, const Address& src) {
2002 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2003 EmitUint8(0x0F);
2004 EmitUint8(0x54);
2005 EmitOperand(dst, src);
2006 }
2007
2008
pand(XmmRegister dst,XmmRegister src)2009 void X86Assembler::pand(XmmRegister dst, XmmRegister src) {
2010 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2011 EmitUint8(0x66);
2012 EmitUint8(0x0F);
2013 EmitUint8(0xDB);
2014 EmitXmmRegisterOperand(dst, src);
2015 }
2016
2017 /* VEX.128.66.0F.WIG DB /r VPAND xmm1, xmm2, xmm3/m128 */
vpand(XmmRegister dst,XmmRegister src1,XmmRegister src2)2018 void X86Assembler::vpand(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2019 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2020 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2021 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2022 /* Instruction VEX Prefix */
2023 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2024 /* REX prefix is necessary only if an instruction references one of extended
2025 registers or uses a 64-bit operand. */
2026 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2027 X86ManagedRegister::FromXmmRegister(src1),
2028 SET_VEX_L_128,
2029 SET_VEX_PP_66);
2030 EmitUint8(ByteZero);
2031 EmitUint8(ByteOne);
2032 // Instruction Opcode
2033 EmitUint8(0xDB);
2034 // Instruction Operands
2035 EmitXmmRegisterOperand(dst, src2);
2036 }
2037
2038 /* VEX.128.0F 54 /r VANDPS xmm1,xmm2, xmm3/m128 */
vandps(XmmRegister dst,XmmRegister src1,XmmRegister src2)2039 void X86Assembler::vandps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2040 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2041 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2042 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2043 /* Instruction VEX Prefix */
2044 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2045 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2046 X86ManagedRegister::FromXmmRegister(src1),
2047 SET_VEX_L_128,
2048 SET_VEX_PP_NONE);
2049 EmitUint8(ByteZero);
2050 EmitUint8(ByteOne);
2051 // Instruction Opcode
2052 EmitUint8(0x54);
2053 // Instruction Operands
2054 EmitXmmRegisterOperand(dst, src2);
2055 }
2056
2057 /* VEX.128.66.0F 54 /r VANDPD xmm1, xmm2, xmm3/m128 */
vandpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)2058 void X86Assembler::vandpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2059 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2060 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2061 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2062 /* Instruction VEX Prefix */
2063 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2064 /* REX prefix is necessary only if an instruction references one of extended
2065 registers or uses a 64-bit operand. */
2066 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2067 X86ManagedRegister::FromXmmRegister(src1),
2068 SET_VEX_L_128,
2069 SET_VEX_PP_66);
2070 EmitUint8(ByteZero);
2071 EmitUint8(ByteOne);
2072 // Instruction Opcode
2073 EmitUint8(0x54);
2074 // Instruction Operands
2075 EmitXmmRegisterOperand(dst, src2);
2076 }
2077
andnpd(XmmRegister dst,XmmRegister src)2078 void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) {
2079 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2080 EmitUint8(0x66);
2081 EmitUint8(0x0F);
2082 EmitUint8(0x55);
2083 EmitXmmRegisterOperand(dst, src);
2084 }
2085
2086
andnps(XmmRegister dst,XmmRegister src)2087 void X86Assembler::andnps(XmmRegister dst, XmmRegister src) {
2088 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2089 EmitUint8(0x0F);
2090 EmitUint8(0x55);
2091 EmitXmmRegisterOperand(dst, src);
2092 }
2093
2094
pandn(XmmRegister dst,XmmRegister src)2095 void X86Assembler::pandn(XmmRegister dst, XmmRegister src) {
2096 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2097 EmitUint8(0x66);
2098 EmitUint8(0x0F);
2099 EmitUint8(0xDF);
2100 EmitXmmRegisterOperand(dst, src);
2101 }
2102
2103 /* VEX.128.66.0F.WIG DF /r VPANDN xmm1, xmm2, xmm3/m128 */
vpandn(XmmRegister dst,XmmRegister src1,XmmRegister src2)2104 void X86Assembler::vpandn(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2105 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2106 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2107 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2108 /* Instruction VEX Prefix */
2109 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2110 /* REX prefix is necessary only if an instruction references one of extended
2111 registers or uses a 64-bit operand. */
2112 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2113 X86ManagedRegister::FromXmmRegister(src1),
2114 SET_VEX_L_128,
2115 SET_VEX_PP_66);
2116 EmitUint8(ByteZero);
2117 EmitUint8(ByteOne);
2118 // Instruction Opcode
2119 EmitUint8(0xDF);
2120 // Instruction Operands
2121 EmitXmmRegisterOperand(dst, src2);
2122 }
2123
2124 /* VEX.128.0F 55 /r VANDNPS xmm1, xmm2, xmm3/m128 */
vandnps(XmmRegister dst,XmmRegister src1,XmmRegister src2)2125 void X86Assembler::vandnps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2126 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2127 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2128 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2129 /* Instruction VEX Prefix */
2130 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2131 /* REX prefix is necessary only if an instruction references one of extended
2132 registers or uses a 64-bit operand. */
2133 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2134 X86ManagedRegister::FromXmmRegister(src1),
2135 SET_VEX_L_128,
2136 SET_VEX_PP_NONE);
2137 EmitUint8(ByteZero);
2138 EmitUint8(ByteOne);
2139 // Instruction Opcode
2140 EmitUint8(0x55);
2141 // Instruction Operands
2142 EmitXmmRegisterOperand(dst, src2);
2143 }
2144
2145 /* VEX.128.66.0F 55 /r VANDNPD xmm1, xmm2, xmm3/m128 */
vandnpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)2146 void X86Assembler::vandnpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2147 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2148 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2149 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2150 /* Instruction VEX Prefix */
2151 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2152 /* REX prefix is necessary only if an instruction references one of extended
2153 registers or uses a 64-bit operand. */
2154 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2155 X86ManagedRegister::FromXmmRegister(src1),
2156 SET_VEX_L_128,
2157 SET_VEX_PP_66);
2158 EmitUint8(ByteZero);
2159 EmitUint8(ByteOne);
2160 // Instruction Opcode
2161 EmitUint8(0x55);
2162 // Instruction Operands
2163 EmitXmmRegisterOperand(dst, src2);
2164 }
2165
orpd(XmmRegister dst,XmmRegister src)2166 void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
2167 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2168 EmitUint8(0x66);
2169 EmitUint8(0x0F);
2170 EmitUint8(0x56);
2171 EmitXmmRegisterOperand(dst, src);
2172 }
2173
2174
orps(XmmRegister dst,XmmRegister src)2175 void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
2176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2177 EmitUint8(0x0F);
2178 EmitUint8(0x56);
2179 EmitXmmRegisterOperand(dst, src);
2180 }
2181
andn(Register dst,Register src1,Register src2)2182 void X86Assembler::andn(Register dst, Register src1, Register src2) {
2183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2184 uint8_t byte_zero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ false);
2185 uint8_t byte_one = EmitVexPrefixByteOne(/*R=*/ false,
2186 /*X=*/ false,
2187 /*B=*/ false,
2188 SET_VEX_M_0F_38);
2189 uint8_t byte_two = EmitVexPrefixByteTwo(/*W=*/ false,
2190 X86ManagedRegister::FromCpuRegister(src1),
2191 SET_VEX_L_128,
2192 SET_VEX_PP_NONE);
2193 EmitUint8(byte_zero);
2194 EmitUint8(byte_one);
2195 EmitUint8(byte_two);
2196 // Opcode field
2197 EmitUint8(0xF2);
2198 EmitRegisterOperand(dst, src2);
2199 }
2200
por(XmmRegister dst,XmmRegister src)2201 void X86Assembler::por(XmmRegister dst, XmmRegister src) {
2202 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2203 EmitUint8(0x66);
2204 EmitUint8(0x0F);
2205 EmitUint8(0xEB);
2206 EmitXmmRegisterOperand(dst, src);
2207 }
2208
2209 /* VEX.128.66.0F.WIG EB /r VPOR xmm1, xmm2, xmm3/m128 */
vpor(XmmRegister dst,XmmRegister src1,XmmRegister src2)2210 void X86Assembler::vpor(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2211 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2212 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2213 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2214 /* Instruction VEX Prefix */
2215 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2216 /* REX prefix is necessary only if an instruction references one of extended
2217 registers or uses a 64-bit operand. */
2218 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2219 X86ManagedRegister::FromXmmRegister(src1),
2220 SET_VEX_L_128,
2221 SET_VEX_PP_66);
2222 EmitUint8(ByteZero);
2223 EmitUint8(ByteOne);
2224 // Instruction Opcode
2225 EmitUint8(0xEB);
2226 // Instruction Operands
2227 EmitXmmRegisterOperand(dst, src2);
2228 }
2229
2230 /* VEX.128.0F 56 /r VORPS xmm1,xmm2, xmm3/m128 */
vorps(XmmRegister dst,XmmRegister src1,XmmRegister src2)2231 void X86Assembler::vorps(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2232 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2233 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2234 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2235 /* Instruction VEX Prefix */
2236 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2237 /* REX prefix is necessary only if an instruction references one of extended
2238 registers or uses a 64-bit operand. */
2239 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2240 X86ManagedRegister::FromXmmRegister(src1),
2241 SET_VEX_L_128,
2242 SET_VEX_PP_NONE);
2243 EmitUint8(ByteZero);
2244 EmitUint8(ByteOne);
2245 // Instruction Opcode
2246 EmitUint8(0x56);
2247 // Instruction Operands
2248 EmitXmmRegisterOperand(dst, src2);
2249 }
2250
2251 /* VEX.128.66.0F 56 /r VORPD xmm1,xmm2, xmm3/m128 */
vorpd(XmmRegister dst,XmmRegister src1,XmmRegister src2)2252 void X86Assembler::vorpd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2253 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2254 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2255 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2256 /* Instruction VEX Prefix */
2257 ByteZero = EmitVexPrefixByteZero(/*is_twobyte_form=*/ true);
2258 /* REX prefix is necessary only if an instruction references one of extended
2259 registers or uses a 64-bit operand. */
2260 ByteOne = EmitVexPrefixByteOne(/*R=*/ false,
2261 X86ManagedRegister::FromXmmRegister(src1),
2262 SET_VEX_L_128,
2263 SET_VEX_PP_66);
2264 EmitUint8(ByteZero);
2265 EmitUint8(ByteOne);
2266 // Instruction Opcode
2267 EmitUint8(0x56);
2268 // Instruction Operands
2269 EmitXmmRegisterOperand(dst, src2);
2270 }
2271
pavgb(XmmRegister dst,XmmRegister src)2272 void X86Assembler::pavgb(XmmRegister dst, XmmRegister src) {
2273 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2274 EmitUint8(0x66);
2275 EmitUint8(0x0F);
2276 EmitUint8(0xE0);
2277 EmitXmmRegisterOperand(dst, src);
2278 }
2279
2280
pavgw(XmmRegister dst,XmmRegister src)2281 void X86Assembler::pavgw(XmmRegister dst, XmmRegister src) {
2282 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2283 EmitUint8(0x66);
2284 EmitUint8(0x0F);
2285 EmitUint8(0xE3);
2286 EmitXmmRegisterOperand(dst, src);
2287 }
2288
2289
psadbw(XmmRegister dst,XmmRegister src)2290 void X86Assembler::psadbw(XmmRegister dst, XmmRegister src) {
2291 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2292 EmitUint8(0x66);
2293 EmitUint8(0x0F);
2294 EmitUint8(0xF6);
2295 EmitXmmRegisterOperand(dst, src);
2296 }
2297
2298
pmaddwd(XmmRegister dst,XmmRegister src)2299 void X86Assembler::pmaddwd(XmmRegister dst, XmmRegister src) {
2300 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2301 EmitUint8(0x66);
2302 EmitUint8(0x0F);
2303 EmitUint8(0xF5);
2304 EmitXmmRegisterOperand(dst, src);
2305 }
2306
2307
vpmaddwd(XmmRegister dst,XmmRegister src1,XmmRegister src2)2308 void X86Assembler::vpmaddwd(XmmRegister dst, XmmRegister src1, XmmRegister src2) {
2309 DCHECK(CpuHasAVXorAVX2FeatureFlag());
2310 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2311 uint8_t ByteZero = 0x00, ByteOne = 0x00;
2312 ByteZero = EmitVexPrefixByteZero(/* is_twobyte_form=*/ true);
2313 X86ManagedRegister vvvv_reg = X86ManagedRegister::FromXmmRegister(src1);
2314 ByteOne = EmitVexPrefixByteOne(/*R=*/ false, vvvv_reg, SET_VEX_L_128, SET_VEX_PP_66);
2315 EmitUint8(ByteZero);
2316 EmitUint8(ByteOne);
2317 EmitUint8(0xF5);
2318 EmitXmmRegisterOperand(dst, src2);
2319 }
2320
2321
phaddw(XmmRegister dst,XmmRegister src)2322 void X86Assembler::phaddw(XmmRegister dst, XmmRegister src) {
2323 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2324 EmitUint8(0x66);
2325 EmitUint8(0x0F);
2326 EmitUint8(0x38);
2327 EmitUint8(0x01);
2328 EmitXmmRegisterOperand(dst, src);
2329 }
2330
2331
phaddd(XmmRegister dst,XmmRegister src)2332 void X86Assembler::phaddd(XmmRegister dst, XmmRegister src) {
2333 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2334 EmitUint8(0x66);
2335 EmitUint8(0x0F);
2336 EmitUint8(0x38);
2337 EmitUint8(0x02);
2338 EmitXmmRegisterOperand(dst, src);
2339 }
2340
2341
haddps(XmmRegister dst,XmmRegister src)2342 void X86Assembler::haddps(XmmRegister dst, XmmRegister src) {
2343 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2344 EmitUint8(0xF2);
2345 EmitUint8(0x0F);
2346 EmitUint8(0x7C);
2347 EmitXmmRegisterOperand(dst, src);
2348 }
2349
2350
haddpd(XmmRegister dst,XmmRegister src)2351 void X86Assembler::haddpd(XmmRegister dst, XmmRegister src) {
2352 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2353 EmitUint8(0x66);
2354 EmitUint8(0x0F);
2355 EmitUint8(0x7C);
2356 EmitXmmRegisterOperand(dst, src);
2357 }
2358
2359
phsubw(XmmRegister dst,XmmRegister src)2360 void X86Assembler::phsubw(XmmRegister dst, XmmRegister src) {
2361 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2362 EmitUint8(0x66);
2363 EmitUint8(0x0F);
2364 EmitUint8(0x38);
2365 EmitUint8(0x05);
2366 EmitXmmRegisterOperand(dst, src);
2367 }
2368
2369
phsubd(XmmRegister dst,XmmRegister src)2370 void X86Assembler::phsubd(XmmRegister dst, XmmRegister src) {
2371 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2372 EmitUint8(0x66);
2373 EmitUint8(0x0F);
2374 EmitUint8(0x38);
2375 EmitUint8(0x06);
2376 EmitXmmRegisterOperand(dst, src);
2377 }
2378
2379
hsubps(XmmRegister dst,XmmRegister src)2380 void X86Assembler::hsubps(XmmRegister dst, XmmRegister src) {
2381 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2382 EmitUint8(0xF2);
2383 EmitUint8(0x0F);
2384 EmitUint8(0x7D);
2385 EmitXmmRegisterOperand(dst, src);
2386 }
2387
2388
hsubpd(XmmRegister dst,XmmRegister src)2389 void X86Assembler::hsubpd(XmmRegister dst, XmmRegister src) {
2390 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2391 EmitUint8(0x66);
2392 EmitUint8(0x0F);
2393 EmitUint8(0x7D);
2394 EmitXmmRegisterOperand(dst, src);
2395 }
2396
2397
pminsb(XmmRegister dst,XmmRegister src)2398 void X86Assembler::pminsb(XmmRegister dst, XmmRegister src) {
2399 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2400 EmitUint8(0x66);
2401 EmitUint8(0x0F);
2402 EmitUint8(0x38);
2403 EmitUint8(0x38);
2404 EmitXmmRegisterOperand(dst, src);
2405 }
2406
pmaxsb(XmmRegister dst,XmmRegister src)2407 void X86Assembler::pmaxsb(XmmRegister dst, XmmRegister src) {
2408 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2409 EmitUint8(0x66);
2410 EmitUint8(0x0F);
2411 EmitUint8(0x38);
2412 EmitUint8(0x3C);
2413 EmitXmmRegisterOperand(dst, src);
2414 }
2415
pminsw(XmmRegister dst,XmmRegister src)2416 void X86Assembler::pminsw(XmmRegister dst, XmmRegister src) {
2417 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2418 EmitUint8(0x66);
2419 EmitUint8(0x0F);
2420 EmitUint8(0xEA);
2421 EmitXmmRegisterOperand(dst, src);
2422 }
2423
pmaxsw(XmmRegister dst,XmmRegister src)2424 void X86Assembler::pmaxsw(XmmRegister dst, XmmRegister src) {
2425 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2426 EmitUint8(0x66);
2427 EmitUint8(0x0F);
2428 EmitUint8(0xEE);
2429 EmitXmmRegisterOperand(dst, src);
2430 }
2431
pminsd(XmmRegister dst,XmmRegister src)2432 void X86Assembler::pminsd(XmmRegister dst, XmmRegister src) {
2433 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2434 EmitUint8(0x66);
2435 EmitUint8(0x0F);
2436 EmitUint8(0x38);
2437 EmitUint8(0x39);
2438 EmitXmmRegisterOperand(dst, src);
2439 }
2440
pmaxsd(XmmRegister dst,XmmRegister src)2441 void X86Assembler::pmaxsd(XmmRegister dst, XmmRegister src) {
2442 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2443 EmitUint8(0x66);
2444 EmitUint8(0x0F);
2445 EmitUint8(0x38);
2446 EmitUint8(0x3D);
2447 EmitXmmRegisterOperand(dst, src);
2448 }
2449
pminub(XmmRegister dst,XmmRegister src)2450 void X86Assembler::pminub(XmmRegister dst, XmmRegister src) {
2451 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2452 EmitUint8(0x66);
2453 EmitUint8(0x0F);
2454 EmitUint8(0xDA);
2455 EmitXmmRegisterOperand(dst, src);
2456 }
2457
pmaxub(XmmRegister dst,XmmRegister src)2458 void X86Assembler::pmaxub(XmmRegister dst, XmmRegister src) {
2459 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2460 EmitUint8(0x66);
2461 EmitUint8(0x0F);
2462 EmitUint8(0xDE);
2463 EmitXmmRegisterOperand(dst, src);
2464 }
2465
pminuw(XmmRegister dst,XmmRegister src)2466 void X86Assembler::pminuw(XmmRegister dst, XmmRegister src) {
2467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2468 EmitUint8(0x66);
2469 EmitUint8(0x0F);
2470 EmitUint8(0x38);
2471 EmitUint8(0x3A);
2472 EmitXmmRegisterOperand(dst, src);
2473 }
2474
pmaxuw(XmmRegister dst,XmmRegister src)2475 void X86Assembler::pmaxuw(XmmRegister dst, XmmRegister src) {
2476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2477 EmitUint8(0x66);
2478 EmitUint8(0x0F);
2479 EmitUint8(0x38);
2480 EmitUint8(0x3E);
2481 EmitXmmRegisterOperand(dst, src);
2482 }
2483
pminud(XmmRegister dst,XmmRegister src)2484 void X86Assembler::pminud(XmmRegister dst, XmmRegister src) {
2485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2486 EmitUint8(0x66);
2487 EmitUint8(0x0F);
2488 EmitUint8(0x38);
2489 EmitUint8(0x3B);
2490 EmitXmmRegisterOperand(dst, src);
2491 }
2492
pmaxud(XmmRegister dst,XmmRegister src)2493 void X86Assembler::pmaxud(XmmRegister dst, XmmRegister src) {
2494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2495 EmitUint8(0x66);
2496 EmitUint8(0x0F);
2497 EmitUint8(0x38);
2498 EmitUint8(0x3F);
2499 EmitXmmRegisterOperand(dst, src);
2500 }
2501
minps(XmmRegister dst,XmmRegister src)2502 void X86Assembler::minps(XmmRegister dst, XmmRegister src) {
2503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2504 EmitUint8(0x0F);
2505 EmitUint8(0x5D);
2506 EmitXmmRegisterOperand(dst, src);
2507 }
2508
maxps(XmmRegister dst,XmmRegister src)2509 void X86Assembler::maxps(XmmRegister dst, XmmRegister src) {
2510 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2511 EmitUint8(0x0F);
2512 EmitUint8(0x5F);
2513 EmitXmmRegisterOperand(dst, src);
2514 }
2515
minpd(XmmRegister dst,XmmRegister src)2516 void X86Assembler::minpd(XmmRegister dst, XmmRegister src) {
2517 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2518 EmitUint8(0x66);
2519 EmitUint8(0x0F);
2520 EmitUint8(0x5D);
2521 EmitXmmRegisterOperand(dst, src);
2522 }
2523
maxpd(XmmRegister dst,XmmRegister src)2524 void X86Assembler::maxpd(XmmRegister dst, XmmRegister src) {
2525 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2526 EmitUint8(0x66);
2527 EmitUint8(0x0F);
2528 EmitUint8(0x5F);
2529 EmitXmmRegisterOperand(dst, src);
2530 }
2531
pcmpeqb(XmmRegister dst,XmmRegister src)2532 void X86Assembler::pcmpeqb(XmmRegister dst, XmmRegister src) {
2533 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2534 EmitUint8(0x66);
2535 EmitUint8(0x0F);
2536 EmitUint8(0x74);
2537 EmitXmmRegisterOperand(dst, src);
2538 }
2539
2540
pcmpeqw(XmmRegister dst,XmmRegister src)2541 void X86Assembler::pcmpeqw(XmmRegister dst, XmmRegister src) {
2542 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2543 EmitUint8(0x66);
2544 EmitUint8(0x0F);
2545 EmitUint8(0x75);
2546 EmitXmmRegisterOperand(dst, src);
2547 }
2548
2549
pcmpeqd(XmmRegister dst,XmmRegister src)2550 void X86Assembler::pcmpeqd(XmmRegister dst, XmmRegister src) {
2551 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2552 EmitUint8(0x66);
2553 EmitUint8(0x0F);
2554 EmitUint8(0x76);
2555 EmitXmmRegisterOperand(dst, src);
2556 }
2557
2558
pcmpeqq(XmmRegister dst,XmmRegister src)2559 void X86Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
2560 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2561 EmitUint8(0x66);
2562 EmitUint8(0x0F);
2563 EmitUint8(0x38);
2564 EmitUint8(0x29);
2565 EmitXmmRegisterOperand(dst, src);
2566 }
2567
2568
pcmpgtb(XmmRegister dst,XmmRegister src)2569 void X86Assembler::pcmpgtb(XmmRegister dst, XmmRegister src) {
2570 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2571 EmitUint8(0x66);
2572 EmitUint8(0x0F);
2573 EmitUint8(0x64);
2574 EmitXmmRegisterOperand(dst, src);
2575 }
2576
2577
pcmpgtw(XmmRegister dst,XmmRegister src)2578 void X86Assembler::pcmpgtw(XmmRegister dst, XmmRegister src) {
2579 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2580 EmitUint8(0x66);
2581 EmitUint8(0x0F);
2582 EmitUint8(0x65);
2583 EmitXmmRegisterOperand(dst, src);
2584 }
2585
2586
pcmpgtd(XmmRegister dst,XmmRegister src)2587 void X86Assembler::pcmpgtd(XmmRegister dst, XmmRegister src) {
2588 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2589 EmitUint8(0x66);
2590 EmitUint8(0x0F);
2591 EmitUint8(0x66);
2592 EmitXmmRegisterOperand(dst, src);
2593 }
2594
2595
pcmpgtq(XmmRegister dst,XmmRegister src)2596 void X86Assembler::pcmpgtq(XmmRegister dst, XmmRegister src) {
2597 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2598 EmitUint8(0x66);
2599 EmitUint8(0x0F);
2600 EmitUint8(0x38);
2601 EmitUint8(0x37);
2602 EmitXmmRegisterOperand(dst, src);
2603 }
2604
2605
shufpd(XmmRegister dst,XmmRegister src,const Immediate & imm)2606 void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
2607 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2608 EmitUint8(0x66);
2609 EmitUint8(0x0F);
2610 EmitUint8(0xC6);
2611 EmitXmmRegisterOperand(dst, src);
2612 EmitUint8(imm.value());
2613 }
2614
2615
shufps(XmmRegister dst,XmmRegister src,const Immediate & imm)2616 void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
2617 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2618 EmitUint8(0x0F);
2619 EmitUint8(0xC6);
2620 EmitXmmRegisterOperand(dst, src);
2621 EmitUint8(imm.value());
2622 }
2623
2624
pshufd(XmmRegister dst,XmmRegister src,const Immediate & imm)2625 void X86Assembler::pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
2626 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2627 EmitUint8(0x66);
2628 EmitUint8(0x0F);
2629 EmitUint8(0x70);
2630 EmitXmmRegisterOperand(dst, src);
2631 EmitUint8(imm.value());
2632 }
2633
2634
punpcklbw(XmmRegister dst,XmmRegister src)2635 void X86Assembler::punpcklbw(XmmRegister dst, XmmRegister src) {
2636 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2637 EmitUint8(0x66);
2638 EmitUint8(0x0F);
2639 EmitUint8(0x60);
2640 EmitXmmRegisterOperand(dst, src);
2641 }
2642
2643
punpcklwd(XmmRegister dst,XmmRegister src)2644 void X86Assembler::punpcklwd(XmmRegister dst, XmmRegister src) {
2645 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2646 EmitUint8(0x66);
2647 EmitUint8(0x0F);
2648 EmitUint8(0x61);
2649 EmitXmmRegisterOperand(dst, src);
2650 }
2651
2652
punpckldq(XmmRegister dst,XmmRegister src)2653 void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
2654 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2655 EmitUint8(0x66);
2656 EmitUint8(0x0F);
2657 EmitUint8(0x62);
2658 EmitXmmRegisterOperand(dst, src);
2659 }
2660
2661
punpcklqdq(XmmRegister dst,XmmRegister src)2662 void X86Assembler::punpcklqdq(XmmRegister dst, XmmRegister src) {
2663 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2664 EmitUint8(0x66);
2665 EmitUint8(0x0F);
2666 EmitUint8(0x6C);
2667 EmitXmmRegisterOperand(dst, src);
2668 }
2669
2670
punpckhbw(XmmRegister dst,XmmRegister src)2671 void X86Assembler::punpckhbw(XmmRegister dst, XmmRegister src) {
2672 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2673 EmitUint8(0x66);
2674 EmitUint8(0x0F);
2675 EmitUint8(0x68);
2676 EmitXmmRegisterOperand(dst, src);
2677 }
2678
2679
punpckhwd(XmmRegister dst,XmmRegister src)2680 void X86Assembler::punpckhwd(XmmRegister dst, XmmRegister src) {
2681 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2682 EmitUint8(0x66);
2683 EmitUint8(0x0F);
2684 EmitUint8(0x69);
2685 EmitXmmRegisterOperand(dst, src);
2686 }
2687
2688
punpckhdq(XmmRegister dst,XmmRegister src)2689 void X86Assembler::punpckhdq(XmmRegister dst, XmmRegister src) {
2690 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2691 EmitUint8(0x66);
2692 EmitUint8(0x0F);
2693 EmitUint8(0x6A);
2694 EmitXmmRegisterOperand(dst, src);
2695 }
2696
2697
punpckhqdq(XmmRegister dst,XmmRegister src)2698 void X86Assembler::punpckhqdq(XmmRegister dst, XmmRegister src) {
2699 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2700 EmitUint8(0x66);
2701 EmitUint8(0x0F);
2702 EmitUint8(0x6D);
2703 EmitXmmRegisterOperand(dst, src);
2704 }
2705
2706
psllw(XmmRegister reg,const Immediate & shift_count)2707 void X86Assembler::psllw(XmmRegister reg, const Immediate& shift_count) {
2708 DCHECK(shift_count.is_uint8());
2709 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2710 EmitUint8(0x66);
2711 EmitUint8(0x0F);
2712 EmitUint8(0x71);
2713 EmitXmmRegisterOperand(6, reg);
2714 EmitUint8(shift_count.value());
2715 }
2716
2717
pslld(XmmRegister reg,const Immediate & shift_count)2718 void X86Assembler::pslld(XmmRegister reg, const Immediate& shift_count) {
2719 DCHECK(shift_count.is_uint8());
2720 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2721 EmitUint8(0x66);
2722 EmitUint8(0x0F);
2723 EmitUint8(0x72);
2724 EmitXmmRegisterOperand(6, reg);
2725 EmitUint8(shift_count.value());
2726 }
2727
2728
psllq(XmmRegister reg,const Immediate & shift_count)2729 void X86Assembler::psllq(XmmRegister reg, const Immediate& shift_count) {
2730 DCHECK(shift_count.is_uint8());
2731 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2732 EmitUint8(0x66);
2733 EmitUint8(0x0F);
2734 EmitUint8(0x73);
2735 EmitXmmRegisterOperand(6, reg);
2736 EmitUint8(shift_count.value());
2737 }
2738
2739
psraw(XmmRegister reg,const Immediate & shift_count)2740 void X86Assembler::psraw(XmmRegister reg, const Immediate& shift_count) {
2741 DCHECK(shift_count.is_uint8());
2742 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2743 EmitUint8(0x66);
2744 EmitUint8(0x0F);
2745 EmitUint8(0x71);
2746 EmitXmmRegisterOperand(4, reg);
2747 EmitUint8(shift_count.value());
2748 }
2749
2750
psrad(XmmRegister reg,const Immediate & shift_count)2751 void X86Assembler::psrad(XmmRegister reg, const Immediate& shift_count) {
2752 DCHECK(shift_count.is_uint8());
2753 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2754 EmitUint8(0x66);
2755 EmitUint8(0x0F);
2756 EmitUint8(0x72);
2757 EmitXmmRegisterOperand(4, reg);
2758 EmitUint8(shift_count.value());
2759 }
2760
2761
psrlw(XmmRegister reg,const Immediate & shift_count)2762 void X86Assembler::psrlw(XmmRegister reg, const Immediate& shift_count) {
2763 DCHECK(shift_count.is_uint8());
2764 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2765 EmitUint8(0x66);
2766 EmitUint8(0x0F);
2767 EmitUint8(0x71);
2768 EmitXmmRegisterOperand(2, reg);
2769 EmitUint8(shift_count.value());
2770 }
2771
2772
psrld(XmmRegister reg,const Immediate & shift_count)2773 void X86Assembler::psrld(XmmRegister reg, const Immediate& shift_count) {
2774 DCHECK(shift_count.is_uint8());
2775 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2776 EmitUint8(0x66);
2777 EmitUint8(0x0F);
2778 EmitUint8(0x72);
2779 EmitXmmRegisterOperand(2, reg);
2780 EmitUint8(shift_count.value());
2781 }
2782
2783
psrlq(XmmRegister reg,const Immediate & shift_count)2784 void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
2785 DCHECK(shift_count.is_uint8());
2786 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2787 EmitUint8(0x66);
2788 EmitUint8(0x0F);
2789 EmitUint8(0x73);
2790 EmitXmmRegisterOperand(2, reg);
2791 EmitUint8(shift_count.value());
2792 }
2793
2794
psrldq(XmmRegister reg,const Immediate & shift_count)2795 void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
2796 DCHECK(shift_count.is_uint8());
2797 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2798 EmitUint8(0x66);
2799 EmitUint8(0x0F);
2800 EmitUint8(0x73);
2801 EmitXmmRegisterOperand(3, reg);
2802 EmitUint8(shift_count.value());
2803 }
2804
2805
fldl(const Address & src)2806 void X86Assembler::fldl(const Address& src) {
2807 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2808 EmitUint8(0xDD);
2809 EmitOperand(0, src);
2810 }
2811
2812
fstl(const Address & dst)2813 void X86Assembler::fstl(const Address& dst) {
2814 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2815 EmitUint8(0xDD);
2816 EmitOperand(2, dst);
2817 }
2818
2819
fstpl(const Address & dst)2820 void X86Assembler::fstpl(const Address& dst) {
2821 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2822 EmitUint8(0xDD);
2823 EmitOperand(3, dst);
2824 }
2825
2826
fstsw()2827 void X86Assembler::fstsw() {
2828 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2829 EmitUint8(0x9B);
2830 EmitUint8(0xDF);
2831 EmitUint8(0xE0);
2832 }
2833
2834
fnstcw(const Address & dst)2835 void X86Assembler::fnstcw(const Address& dst) {
2836 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2837 EmitUint8(0xD9);
2838 EmitOperand(7, dst);
2839 }
2840
2841
fldcw(const Address & src)2842 void X86Assembler::fldcw(const Address& src) {
2843 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2844 EmitUint8(0xD9);
2845 EmitOperand(5, src);
2846 }
2847
2848
fistpl(const Address & dst)2849 void X86Assembler::fistpl(const Address& dst) {
2850 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2851 EmitUint8(0xDF);
2852 EmitOperand(7, dst);
2853 }
2854
2855
fistps(const Address & dst)2856 void X86Assembler::fistps(const Address& dst) {
2857 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2858 EmitUint8(0xDB);
2859 EmitOperand(3, dst);
2860 }
2861
2862
fildl(const Address & src)2863 void X86Assembler::fildl(const Address& src) {
2864 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2865 EmitUint8(0xDF);
2866 EmitOperand(5, src);
2867 }
2868
2869
filds(const Address & src)2870 void X86Assembler::filds(const Address& src) {
2871 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2872 EmitUint8(0xDB);
2873 EmitOperand(0, src);
2874 }
2875
2876
fincstp()2877 void X86Assembler::fincstp() {
2878 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2879 EmitUint8(0xD9);
2880 EmitUint8(0xF7);
2881 }
2882
2883
ffree(const Immediate & index)2884 void X86Assembler::ffree(const Immediate& index) {
2885 CHECK_LT(index.value(), 7);
2886 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2887 EmitUint8(0xDD);
2888 EmitUint8(0xC0 + index.value());
2889 }
2890
2891
fsin()2892 void X86Assembler::fsin() {
2893 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2894 EmitUint8(0xD9);
2895 EmitUint8(0xFE);
2896 }
2897
2898
fcos()2899 void X86Assembler::fcos() {
2900 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2901 EmitUint8(0xD9);
2902 EmitUint8(0xFF);
2903 }
2904
2905
fptan()2906 void X86Assembler::fptan() {
2907 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2908 EmitUint8(0xD9);
2909 EmitUint8(0xF2);
2910 }
2911
2912
fucompp()2913 void X86Assembler::fucompp() {
2914 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2915 EmitUint8(0xDA);
2916 EmitUint8(0xE9);
2917 }
2918
2919
fprem()2920 void X86Assembler::fprem() {
2921 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2922 EmitUint8(0xD9);
2923 EmitUint8(0xF8);
2924 }
2925
2926
try_xchg_eax(Register dst,Register src)2927 bool X86Assembler::try_xchg_eax(Register dst, Register src) {
2928 if (src != EAX && dst != EAX) {
2929 return false;
2930 }
2931 if (dst == EAX) {
2932 std::swap(src, dst);
2933 }
2934 EmitUint8(0x90 + dst);
2935 return true;
2936 }
2937
2938
xchgb(ByteRegister dst,ByteRegister src)2939 void X86Assembler::xchgb(ByteRegister dst, ByteRegister src) {
2940 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2941 EmitUint8(0x86);
2942 EmitRegisterOperand(dst, src);
2943 }
2944
2945
xchgb(ByteRegister reg,const Address & address)2946 void X86Assembler::xchgb(ByteRegister reg, const Address& address) {
2947 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2948 EmitUint8(0x86);
2949 EmitOperand(reg, address);
2950 }
2951
2952
xchgb(Register dst,Register src)2953 void X86Assembler::xchgb(Register dst, Register src) {
2954 xchgb(static_cast<ByteRegister>(dst), static_cast<ByteRegister>(src));
2955 }
2956
2957
xchgb(Register reg,const Address & address)2958 void X86Assembler::xchgb(Register reg, const Address& address) {
2959 xchgb(static_cast<ByteRegister>(reg), address);
2960 }
2961
2962
xchgw(Register dst,Register src)2963 void X86Assembler::xchgw(Register dst, Register src) {
2964 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2965 EmitOperandSizeOverride();
2966 if (try_xchg_eax(dst, src)) {
2967 // A short version for AX.
2968 return;
2969 }
2970 // General case.
2971 EmitUint8(0x87);
2972 EmitRegisterOperand(dst, src);
2973 }
2974
2975
xchgw(Register reg,const Address & address)2976 void X86Assembler::xchgw(Register reg, const Address& address) {
2977 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2978 EmitOperandSizeOverride();
2979 EmitUint8(0x87);
2980 EmitOperand(reg, address);
2981 }
2982
2983
xchgl(Register dst,Register src)2984 void X86Assembler::xchgl(Register dst, Register src) {
2985 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2986 if (try_xchg_eax(dst, src)) {
2987 // A short version for EAX.
2988 return;
2989 }
2990 // General case.
2991 EmitUint8(0x87);
2992 EmitRegisterOperand(dst, src);
2993 }
2994
2995
xchgl(Register reg,const Address & address)2996 void X86Assembler::xchgl(Register reg, const Address& address) {
2997 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2998 EmitUint8(0x87);
2999 EmitOperand(reg, address);
3000 }
3001
3002
cmpb(const Address & address,const Immediate & imm)3003 void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
3004 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3005 EmitUint8(0x80);
3006 EmitOperand(7, address);
3007 EmitUint8(imm.value() & 0xFF);
3008 }
3009
3010
cmpw(const Address & address,const Immediate & imm)3011 void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
3012 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3013 EmitUint8(0x66);
3014 EmitComplex(7, address, imm, /* is_16_op= */ true);
3015 }
3016
3017
cmpl(Register reg,const Immediate & imm)3018 void X86Assembler::cmpl(Register reg, const Immediate& imm) {
3019 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3020 EmitComplex(7, Operand(reg), imm);
3021 }
3022
3023
cmpl(Register reg0,Register reg1)3024 void X86Assembler::cmpl(Register reg0, Register reg1) {
3025 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3026 EmitUint8(0x3B);
3027 EmitOperand(reg0, Operand(reg1));
3028 }
3029
3030
cmpl(Register reg,const Address & address)3031 void X86Assembler::cmpl(Register reg, const Address& address) {
3032 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3033 EmitUint8(0x3B);
3034 EmitOperand(reg, address);
3035 }
3036
3037
addl(Register dst,Register src)3038 void X86Assembler::addl(Register dst, Register src) {
3039 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3040 EmitUint8(0x03);
3041 EmitRegisterOperand(dst, src);
3042 }
3043
3044
addl(Register reg,const Address & address)3045 void X86Assembler::addl(Register reg, const Address& address) {
3046 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3047 EmitUint8(0x03);
3048 EmitOperand(reg, address);
3049 }
3050
3051
cmpl(const Address & address,Register reg)3052 void X86Assembler::cmpl(const Address& address, Register reg) {
3053 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3054 EmitUint8(0x39);
3055 EmitOperand(reg, address);
3056 }
3057
3058
cmpl(const Address & address,const Immediate & imm)3059 void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
3060 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3061 EmitComplex(7, address, imm);
3062 }
3063
3064
testl(Register reg1,Register reg2)3065 void X86Assembler::testl(Register reg1, Register reg2) {
3066 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3067 EmitUint8(0x85);
3068 EmitRegisterOperand(reg1, reg2);
3069 }
3070
3071
testl(Register reg,const Address & address)3072 void X86Assembler::testl(Register reg, const Address& address) {
3073 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3074 EmitUint8(0x85);
3075 EmitOperand(reg, address);
3076 }
3077
3078
testl(Register reg,const Immediate & immediate)3079 void X86Assembler::testl(Register reg, const Immediate& immediate) {
3080 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3081 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
3082 // we only test the byte register to keep the encoding short.
3083 if (immediate.is_uint8() && reg < 4) {
3084 // Use zero-extended 8-bit immediate.
3085 if (reg == EAX) {
3086 EmitUint8(0xA8);
3087 } else {
3088 EmitUint8(0xF6);
3089 EmitUint8(0xC0 + reg);
3090 }
3091 EmitUint8(immediate.value() & 0xFF);
3092 } else if (reg == EAX) {
3093 // Use short form if the destination is EAX.
3094 EmitUint8(0xA9);
3095 EmitImmediate(immediate);
3096 } else {
3097 EmitUint8(0xF7);
3098 EmitOperand(0, Operand(reg));
3099 EmitImmediate(immediate);
3100 }
3101 }
3102
3103
testb(const Address & dst,const Immediate & imm)3104 void X86Assembler::testb(const Address& dst, const Immediate& imm) {
3105 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3106 EmitUint8(0xF6);
3107 EmitOperand(EAX, dst);
3108 CHECK(imm.is_int8());
3109 EmitUint8(imm.value() & 0xFF);
3110 }
3111
3112
testl(const Address & dst,const Immediate & imm)3113 void X86Assembler::testl(const Address& dst, const Immediate& imm) {
3114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3115 EmitUint8(0xF7);
3116 EmitOperand(0, dst);
3117 EmitImmediate(imm);
3118 }
3119
3120
andl(Register dst,Register src)3121 void X86Assembler::andl(Register dst, Register src) {
3122 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3123 EmitUint8(0x23);
3124 EmitOperand(dst, Operand(src));
3125 }
3126
3127
andl(Register reg,const Address & address)3128 void X86Assembler::andl(Register reg, const Address& address) {
3129 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3130 EmitUint8(0x23);
3131 EmitOperand(reg, address);
3132 }
3133
3134
andl(Register dst,const Immediate & imm)3135 void X86Assembler::andl(Register dst, const Immediate& imm) {
3136 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3137 EmitComplex(4, Operand(dst), imm);
3138 }
3139
3140
andw(const Address & address,const Immediate & imm)3141 void X86Assembler::andw(const Address& address, const Immediate& imm) {
3142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3143 CHECK(imm.is_uint16() || imm.is_int16()) << imm.value();
3144 EmitOperandSizeOverride();
3145 EmitComplex(4, address, imm, /* is_16_op= */ true);
3146 }
3147
3148
orl(Register dst,Register src)3149 void X86Assembler::orl(Register dst, Register src) {
3150 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3151 EmitUint8(0x0B);
3152 EmitOperand(dst, Operand(src));
3153 }
3154
3155
orl(Register reg,const Address & address)3156 void X86Assembler::orl(Register reg, const Address& address) {
3157 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3158 EmitUint8(0x0B);
3159 EmitOperand(reg, address);
3160 }
3161
3162
orl(Register dst,const Immediate & imm)3163 void X86Assembler::orl(Register dst, const Immediate& imm) {
3164 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3165 EmitComplex(1, Operand(dst), imm);
3166 }
3167
3168
xorl(Register dst,Register src)3169 void X86Assembler::xorl(Register dst, Register src) {
3170 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3171 EmitUint8(0x33);
3172 EmitOperand(dst, Operand(src));
3173 }
3174
3175
xorl(Register reg,const Address & address)3176 void X86Assembler::xorl(Register reg, const Address& address) {
3177 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3178 EmitUint8(0x33);
3179 EmitOperand(reg, address);
3180 }
3181
3182
xorl(Register dst,const Immediate & imm)3183 void X86Assembler::xorl(Register dst, const Immediate& imm) {
3184 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3185 EmitComplex(6, Operand(dst), imm);
3186 }
3187
3188
addl(Register reg,const Immediate & imm)3189 void X86Assembler::addl(Register reg, const Immediate& imm) {
3190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3191 EmitComplex(0, Operand(reg), imm);
3192 }
3193
3194
addl(const Address & address,Register reg)3195 void X86Assembler::addl(const Address& address, Register reg) {
3196 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3197 EmitUint8(0x01);
3198 EmitOperand(reg, address);
3199 }
3200
3201
addl(const Address & address,const Immediate & imm)3202 void X86Assembler::addl(const Address& address, const Immediate& imm) {
3203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3204 EmitComplex(0, address, imm);
3205 }
3206
3207
addw(const Address & address,const Immediate & imm)3208 void X86Assembler::addw(const Address& address, const Immediate& imm) {
3209 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3210 CHECK(imm.is_uint16() || imm.is_int16()) << imm.value();
3211 EmitUint8(0x66);
3212 EmitComplex(0, address, imm, /* is_16_op= */ true);
3213 }
3214
3215
addw(Register reg,const Immediate & imm)3216 void X86Assembler::addw(Register reg, const Immediate& imm) {
3217 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3218 CHECK(imm.is_uint16() || imm.is_int16()) << imm.value();
3219 EmitUint8(0x66);
3220 EmitComplex(0, Operand(reg), imm, /* is_16_op= */ true);
3221 }
3222
3223
adcl(Register reg,const Immediate & imm)3224 void X86Assembler::adcl(Register reg, const Immediate& imm) {
3225 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3226 EmitComplex(2, Operand(reg), imm);
3227 }
3228
3229
adcl(Register dst,Register src)3230 void X86Assembler::adcl(Register dst, Register src) {
3231 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3232 EmitUint8(0x13);
3233 EmitOperand(dst, Operand(src));
3234 }
3235
3236
adcl(Register dst,const Address & address)3237 void X86Assembler::adcl(Register dst, const Address& address) {
3238 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3239 EmitUint8(0x13);
3240 EmitOperand(dst, address);
3241 }
3242
3243
subl(Register dst,Register src)3244 void X86Assembler::subl(Register dst, Register src) {
3245 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3246 EmitUint8(0x2B);
3247 EmitOperand(dst, Operand(src));
3248 }
3249
3250
subl(Register reg,const Immediate & imm)3251 void X86Assembler::subl(Register reg, const Immediate& imm) {
3252 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3253 EmitComplex(5, Operand(reg), imm);
3254 }
3255
3256
subl(Register reg,const Address & address)3257 void X86Assembler::subl(Register reg, const Address& address) {
3258 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3259 EmitUint8(0x2B);
3260 EmitOperand(reg, address);
3261 }
3262
3263
subl(const Address & address,Register reg)3264 void X86Assembler::subl(const Address& address, Register reg) {
3265 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3266 EmitUint8(0x29);
3267 EmitOperand(reg, address);
3268 }
3269
3270
cdq()3271 void X86Assembler::cdq() {
3272 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3273 EmitUint8(0x99);
3274 }
3275
3276
idivl(Register reg)3277 void X86Assembler::idivl(Register reg) {
3278 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3279 EmitUint8(0xF7);
3280 EmitUint8(0xF8 | reg);
3281 }
3282
3283
divl(Register reg)3284 void X86Assembler::divl(Register reg) {
3285 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3286 EmitUint8(0xF7);
3287 EmitUint8(0xF0 | reg);
3288 }
3289
3290
imull(Register dst,Register src)3291 void X86Assembler::imull(Register dst, Register src) {
3292 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3293 EmitUint8(0x0F);
3294 EmitUint8(0xAF);
3295 EmitOperand(dst, Operand(src));
3296 }
3297
3298
imull(Register dst,Register src,const Immediate & imm)3299 void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
3300 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3301 // See whether imm can be represented as a sign-extended 8bit value.
3302 int32_t v32 = static_cast<int32_t>(imm.value());
3303 if (IsInt<8>(v32)) {
3304 // Sign-extension works.
3305 EmitUint8(0x6B);
3306 EmitOperand(dst, Operand(src));
3307 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
3308 } else {
3309 // Not representable, use full immediate.
3310 EmitUint8(0x69);
3311 EmitOperand(dst, Operand(src));
3312 EmitImmediate(imm);
3313 }
3314 }
3315
3316
imull(Register reg,const Immediate & imm)3317 void X86Assembler::imull(Register reg, const Immediate& imm) {
3318 imull(reg, reg, imm);
3319 }
3320
3321
imull(Register reg,const Address & address)3322 void X86Assembler::imull(Register reg, const Address& address) {
3323 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3324 EmitUint8(0x0F);
3325 EmitUint8(0xAF);
3326 EmitOperand(reg, address);
3327 }
3328
3329
imull(Register reg)3330 void X86Assembler::imull(Register reg) {
3331 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3332 EmitUint8(0xF7);
3333 EmitOperand(5, Operand(reg));
3334 }
3335
3336
imull(const Address & address)3337 void X86Assembler::imull(const Address& address) {
3338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3339 EmitUint8(0xF7);
3340 EmitOperand(5, address);
3341 }
3342
3343
mull(Register reg)3344 void X86Assembler::mull(Register reg) {
3345 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3346 EmitUint8(0xF7);
3347 EmitOperand(4, Operand(reg));
3348 }
3349
3350
mull(const Address & address)3351 void X86Assembler::mull(const Address& address) {
3352 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3353 EmitUint8(0xF7);
3354 EmitOperand(4, address);
3355 }
3356
3357
sbbl(Register dst,Register src)3358 void X86Assembler::sbbl(Register dst, Register src) {
3359 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3360 EmitUint8(0x1B);
3361 EmitOperand(dst, Operand(src));
3362 }
3363
3364
sbbl(Register reg,const Immediate & imm)3365 void X86Assembler::sbbl(Register reg, const Immediate& imm) {
3366 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3367 EmitComplex(3, Operand(reg), imm);
3368 }
3369
3370
sbbl(Register dst,const Address & address)3371 void X86Assembler::sbbl(Register dst, const Address& address) {
3372 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3373 EmitUint8(0x1B);
3374 EmitOperand(dst, address);
3375 }
3376
3377
sbbl(const Address & address,Register src)3378 void X86Assembler::sbbl(const Address& address, Register src) {
3379 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3380 EmitUint8(0x19);
3381 EmitOperand(src, address);
3382 }
3383
3384
incl(Register reg)3385 void X86Assembler::incl(Register reg) {
3386 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3387 EmitUint8(0x40 + reg);
3388 }
3389
3390
incl(const Address & address)3391 void X86Assembler::incl(const Address& address) {
3392 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3393 EmitUint8(0xFF);
3394 EmitOperand(0, address);
3395 }
3396
3397
decl(Register reg)3398 void X86Assembler::decl(Register reg) {
3399 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3400 EmitUint8(0x48 + reg);
3401 }
3402
3403
decl(const Address & address)3404 void X86Assembler::decl(const Address& address) {
3405 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3406 EmitUint8(0xFF);
3407 EmitOperand(1, address);
3408 }
3409
3410
shll(Register reg,const Immediate & imm)3411 void X86Assembler::shll(Register reg, const Immediate& imm) {
3412 EmitGenericShift(4, Operand(reg), imm);
3413 }
3414
3415
shll(Register operand,Register shifter)3416 void X86Assembler::shll(Register operand, Register shifter) {
3417 EmitGenericShift(4, Operand(operand), shifter);
3418 }
3419
3420
shll(const Address & address,const Immediate & imm)3421 void X86Assembler::shll(const Address& address, const Immediate& imm) {
3422 EmitGenericShift(4, address, imm);
3423 }
3424
3425
shll(const Address & address,Register shifter)3426 void X86Assembler::shll(const Address& address, Register shifter) {
3427 EmitGenericShift(4, address, shifter);
3428 }
3429
3430
shrl(Register reg,const Immediate & imm)3431 void X86Assembler::shrl(Register reg, const Immediate& imm) {
3432 EmitGenericShift(5, Operand(reg), imm);
3433 }
3434
3435
shrl(Register operand,Register shifter)3436 void X86Assembler::shrl(Register operand, Register shifter) {
3437 EmitGenericShift(5, Operand(operand), shifter);
3438 }
3439
3440
shrl(const Address & address,const Immediate & imm)3441 void X86Assembler::shrl(const Address& address, const Immediate& imm) {
3442 EmitGenericShift(5, address, imm);
3443 }
3444
3445
shrl(const Address & address,Register shifter)3446 void X86Assembler::shrl(const Address& address, Register shifter) {
3447 EmitGenericShift(5, address, shifter);
3448 }
3449
3450
sarl(Register reg,const Immediate & imm)3451 void X86Assembler::sarl(Register reg, const Immediate& imm) {
3452 EmitGenericShift(7, Operand(reg), imm);
3453 }
3454
3455
sarl(Register operand,Register shifter)3456 void X86Assembler::sarl(Register operand, Register shifter) {
3457 EmitGenericShift(7, Operand(operand), shifter);
3458 }
3459
3460
sarl(const Address & address,const Immediate & imm)3461 void X86Assembler::sarl(const Address& address, const Immediate& imm) {
3462 EmitGenericShift(7, address, imm);
3463 }
3464
3465
sarl(const Address & address,Register shifter)3466 void X86Assembler::sarl(const Address& address, Register shifter) {
3467 EmitGenericShift(7, address, shifter);
3468 }
3469
3470
shld(Register dst,Register src,Register shifter)3471 void X86Assembler::shld(Register dst, Register src, Register shifter) {
3472 DCHECK_EQ(ECX, shifter);
3473 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3474 EmitUint8(0x0F);
3475 EmitUint8(0xA5);
3476 EmitRegisterOperand(src, dst);
3477 }
3478
3479
shld(Register dst,Register src,const Immediate & imm)3480 void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
3481 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3482 EmitUint8(0x0F);
3483 EmitUint8(0xA4);
3484 EmitRegisterOperand(src, dst);
3485 EmitUint8(imm.value() & 0xFF);
3486 }
3487
3488
shrd(Register dst,Register src,Register shifter)3489 void X86Assembler::shrd(Register dst, Register src, Register shifter) {
3490 DCHECK_EQ(ECX, shifter);
3491 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3492 EmitUint8(0x0F);
3493 EmitUint8(0xAD);
3494 EmitRegisterOperand(src, dst);
3495 }
3496
3497
shrd(Register dst,Register src,const Immediate & imm)3498 void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
3499 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3500 EmitUint8(0x0F);
3501 EmitUint8(0xAC);
3502 EmitRegisterOperand(src, dst);
3503 EmitUint8(imm.value() & 0xFF);
3504 }
3505
3506
roll(Register reg,const Immediate & imm)3507 void X86Assembler::roll(Register reg, const Immediate& imm) {
3508 EmitGenericShift(0, Operand(reg), imm);
3509 }
3510
3511
roll(Register operand,Register shifter)3512 void X86Assembler::roll(Register operand, Register shifter) {
3513 EmitGenericShift(0, Operand(operand), shifter);
3514 }
3515
3516
rorl(Register reg,const Immediate & imm)3517 void X86Assembler::rorl(Register reg, const Immediate& imm) {
3518 EmitGenericShift(1, Operand(reg), imm);
3519 }
3520
3521
rorl(Register operand,Register shifter)3522 void X86Assembler::rorl(Register operand, Register shifter) {
3523 EmitGenericShift(1, Operand(operand), shifter);
3524 }
3525
3526
negl(Register reg)3527 void X86Assembler::negl(Register reg) {
3528 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3529 EmitUint8(0xF7);
3530 EmitOperand(3, Operand(reg));
3531 }
3532
3533
notl(Register reg)3534 void X86Assembler::notl(Register reg) {
3535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3536 EmitUint8(0xF7);
3537 EmitUint8(0xD0 | reg);
3538 }
3539
3540
enter(const Immediate & imm)3541 void X86Assembler::enter(const Immediate& imm) {
3542 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3543 EmitUint8(0xC8);
3544 CHECK(imm.is_uint16());
3545 EmitUint8(imm.value() & 0xFF);
3546 EmitUint8((imm.value() >> 8) & 0xFF);
3547 EmitUint8(0x00);
3548 }
3549
3550
leave()3551 void X86Assembler::leave() {
3552 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3553 EmitUint8(0xC9);
3554 }
3555
3556
ret()3557 void X86Assembler::ret() {
3558 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3559 EmitUint8(0xC3);
3560 }
3561
3562
ret(const Immediate & imm)3563 void X86Assembler::ret(const Immediate& imm) {
3564 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3565 EmitUint8(0xC2);
3566 CHECK(imm.is_uint16());
3567 EmitUint8(imm.value() & 0xFF);
3568 EmitUint8((imm.value() >> 8) & 0xFF);
3569 }
3570
3571
3572
nop()3573 void X86Assembler::nop() {
3574 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3575 EmitUint8(0x90);
3576 }
3577
3578
int3()3579 void X86Assembler::int3() {
3580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3581 EmitUint8(0xCC);
3582 }
3583
3584
hlt()3585 void X86Assembler::hlt() {
3586 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3587 EmitUint8(0xF4);
3588 }
3589
3590
j(Condition condition,Label * label)3591 void X86Assembler::j(Condition condition, Label* label) {
3592 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3593 if (label->IsBound()) {
3594 static const int kShortSize = 2;
3595 static const int kLongSize = 6;
3596 int offset = label->Position() - buffer_.Size();
3597 CHECK_LE(offset, 0);
3598 if (IsInt<8>(offset - kShortSize)) {
3599 EmitUint8(0x70 + condition);
3600 EmitUint8((offset - kShortSize) & 0xFF);
3601 } else {
3602 EmitUint8(0x0F);
3603 EmitUint8(0x80 + condition);
3604 EmitInt32(offset - kLongSize);
3605 }
3606 } else {
3607 EmitUint8(0x0F);
3608 EmitUint8(0x80 + condition);
3609 EmitLabelLink(label);
3610 }
3611 }
3612
3613
j(Condition condition,NearLabel * label)3614 void X86Assembler::j(Condition condition, NearLabel* label) {
3615 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3616 if (label->IsBound()) {
3617 static const int kShortSize = 2;
3618 int offset = label->Position() - buffer_.Size();
3619 CHECK_LE(offset, 0);
3620 CHECK(IsInt<8>(offset - kShortSize));
3621 EmitUint8(0x70 + condition);
3622 EmitUint8((offset - kShortSize) & 0xFF);
3623 } else {
3624 EmitUint8(0x70 + condition);
3625 EmitLabelLink(label);
3626 }
3627 }
3628
3629
jecxz(NearLabel * label)3630 void X86Assembler::jecxz(NearLabel* label) {
3631 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3632 if (label->IsBound()) {
3633 static const int kShortSize = 2;
3634 int offset = label->Position() - buffer_.Size();
3635 CHECK_LE(offset, 0);
3636 CHECK(IsInt<8>(offset - kShortSize));
3637 EmitUint8(0xE3);
3638 EmitUint8((offset - kShortSize) & 0xFF);
3639 } else {
3640 EmitUint8(0xE3);
3641 EmitLabelLink(label);
3642 }
3643 }
3644
3645
jmp(Register reg)3646 void X86Assembler::jmp(Register reg) {
3647 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3648 EmitUint8(0xFF);
3649 EmitRegisterOperand(4, reg);
3650 }
3651
jmp(const Address & address)3652 void X86Assembler::jmp(const Address& address) {
3653 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3654 EmitUint8(0xFF);
3655 EmitOperand(4, address);
3656 }
3657
jmp(Label * label)3658 void X86Assembler::jmp(Label* label) {
3659 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3660 if (label->IsBound()) {
3661 static const int kShortSize = 2;
3662 static const int kLongSize = 5;
3663 int offset = label->Position() - buffer_.Size();
3664 CHECK_LE(offset, 0);
3665 if (IsInt<8>(offset - kShortSize)) {
3666 EmitUint8(0xEB);
3667 EmitUint8((offset - kShortSize) & 0xFF);
3668 } else {
3669 EmitUint8(0xE9);
3670 EmitInt32(offset - kLongSize);
3671 }
3672 } else {
3673 EmitUint8(0xE9);
3674 EmitLabelLink(label);
3675 }
3676 }
3677
3678
jmp(NearLabel * label)3679 void X86Assembler::jmp(NearLabel* label) {
3680 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3681 if (label->IsBound()) {
3682 static const int kShortSize = 2;
3683 int offset = label->Position() - buffer_.Size();
3684 CHECK_LE(offset, 0);
3685 CHECK(IsInt<8>(offset - kShortSize));
3686 EmitUint8(0xEB);
3687 EmitUint8((offset - kShortSize) & 0xFF);
3688 } else {
3689 EmitUint8(0xEB);
3690 EmitLabelLink(label);
3691 }
3692 }
3693
3694
repne_scasb()3695 void X86Assembler::repne_scasb() {
3696 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3697 EmitUint8(0xF2);
3698 EmitUint8(0xAE);
3699 }
3700
3701
repne_scasw()3702 void X86Assembler::repne_scasw() {
3703 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3704 EmitUint8(0x66);
3705 EmitUint8(0xF2);
3706 EmitUint8(0xAF);
3707 }
3708
3709
repe_cmpsb()3710 void X86Assembler::repe_cmpsb() {
3711 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3712 EmitUint8(0xF3);
3713 EmitUint8(0xA6);
3714 }
3715
3716
repe_cmpsw()3717 void X86Assembler::repe_cmpsw() {
3718 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3719 EmitUint8(0x66);
3720 EmitUint8(0xF3);
3721 EmitUint8(0xA7);
3722 }
3723
3724
repe_cmpsl()3725 void X86Assembler::repe_cmpsl() {
3726 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3727 EmitUint8(0xF3);
3728 EmitUint8(0xA7);
3729 }
3730
3731
rep_movsb()3732 void X86Assembler::rep_movsb() {
3733 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3734 EmitUint8(0xF3);
3735 EmitUint8(0xA4);
3736 }
3737
3738
rep_movsw()3739 void X86Assembler::rep_movsw() {
3740 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3741 EmitUint8(0x66);
3742 EmitUint8(0xF3);
3743 EmitUint8(0xA5);
3744 }
3745
rep_movsl()3746 void X86Assembler::rep_movsl() {
3747 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3748 EmitUint8(0xF3);
3749 EmitUint8(0xA5);
3750 }
3751
lock()3752 X86Assembler* X86Assembler::lock() {
3753 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3754 EmitUint8(0xF0);
3755 return this;
3756 }
3757
3758
cmpxchgb(const Address & address,ByteRegister reg)3759 void X86Assembler::cmpxchgb(const Address& address, ByteRegister reg) {
3760 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3761 EmitUint8(0x0F);
3762 EmitUint8(0xB0);
3763 EmitOperand(reg, address);
3764 }
3765
3766
cmpxchgw(const Address & address,Register reg)3767 void X86Assembler::cmpxchgw(const Address& address, Register reg) {
3768 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3769 EmitOperandSizeOverride();
3770 EmitUint8(0x0F);
3771 EmitUint8(0xB1);
3772 EmitOperand(reg, address);
3773 }
3774
3775
cmpxchgl(const Address & address,Register reg)3776 void X86Assembler::cmpxchgl(const Address& address, Register reg) {
3777 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3778 EmitUint8(0x0F);
3779 EmitUint8(0xB1);
3780 EmitOperand(reg, address);
3781 }
3782
3783
cmpxchg8b(const Address & address)3784 void X86Assembler::cmpxchg8b(const Address& address) {
3785 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3786 EmitUint8(0x0F);
3787 EmitUint8(0xC7);
3788 EmitOperand(1, address);
3789 }
3790
3791
xaddb(const Address & address,ByteRegister reg)3792 void X86Assembler::xaddb(const Address& address, ByteRegister reg) {
3793 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3794 EmitUint8(0x0F);
3795 EmitUint8(0xC0);
3796 EmitOperand(reg, address);
3797 }
3798
xaddw(const Address & address,Register reg)3799 void X86Assembler::xaddw(const Address& address, Register reg) {
3800 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3801 EmitOperandSizeOverride();
3802 EmitUint8(0x0F);
3803 EmitUint8(0xC1);
3804 EmitOperand(reg, address);
3805 }
3806
xaddl(const Address & address,Register reg)3807 void X86Assembler::xaddl(const Address& address, Register reg) {
3808 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3809 EmitUint8(0x0F);
3810 EmitUint8(0xC1);
3811 EmitOperand(reg, address);
3812 }
3813
3814
mfence()3815 void X86Assembler::mfence() {
3816 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3817 EmitUint8(0x0F);
3818 EmitUint8(0xAE);
3819 EmitUint8(0xF0);
3820 }
3821
fs()3822 X86Assembler* X86Assembler::fs() {
3823 // TODO: fs is a prefix and not an instruction
3824 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3825 EmitUint8(0x64);
3826 return this;
3827 }
3828
gs()3829 X86Assembler* X86Assembler::gs() {
3830 // TODO: fs is a prefix and not an instruction
3831 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3832 EmitUint8(0x65);
3833 return this;
3834 }
3835
AddImmediate(Register reg,const Immediate & imm)3836 void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
3837 int value = imm.value();
3838 if (value > 0) {
3839 if (value == 1) {
3840 incl(reg);
3841 } else if (value != 0) {
3842 addl(reg, imm);
3843 }
3844 } else if (value < 0) {
3845 value = -value;
3846 if (value == 1) {
3847 decl(reg);
3848 } else if (value != 0) {
3849 subl(reg, Immediate(value));
3850 }
3851 }
3852 }
3853
3854
LoadLongConstant(XmmRegister dst,int64_t value)3855 void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
3856 // TODO: Need to have a code constants table.
3857 pushl(Immediate(High32Bits(value)));
3858 pushl(Immediate(Low32Bits(value)));
3859 movsd(dst, Address(ESP, 0));
3860 addl(ESP, Immediate(2 * sizeof(int32_t)));
3861 }
3862
3863
LoadDoubleConstant(XmmRegister dst,double value)3864 void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
3865 // TODO: Need to have a code constants table.
3866 int64_t constant = bit_cast<int64_t, double>(value);
3867 LoadLongConstant(dst, constant);
3868 }
3869
3870
Align(int alignment,int offset)3871 void X86Assembler::Align(int alignment, int offset) {
3872 CHECK(IsPowerOfTwo(alignment));
3873 // Emit nop instruction until the real position is aligned.
3874 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
3875 nop();
3876 }
3877 }
3878
3879
Bind(Label * label)3880 void X86Assembler::Bind(Label* label) {
3881 int bound = buffer_.Size();
3882 CHECK(!label->IsBound()); // Labels can only be bound once.
3883 while (label->IsLinked()) {
3884 int position = label->LinkPosition();
3885 int next = buffer_.Load<int32_t>(position);
3886 buffer_.Store<int32_t>(position, bound - (position + 4));
3887 label->position_ = next;
3888 }
3889 label->BindTo(bound);
3890 }
3891
3892
Bind(NearLabel * label)3893 void X86Assembler::Bind(NearLabel* label) {
3894 int bound = buffer_.Size();
3895 CHECK(!label->IsBound()); // Labels can only be bound once.
3896 while (label->IsLinked()) {
3897 int position = label->LinkPosition();
3898 uint8_t delta = buffer_.Load<uint8_t>(position);
3899 int offset = bound - (position + 1);
3900 CHECK(IsInt<8>(offset));
3901 buffer_.Store<int8_t>(position, offset);
3902 label->position_ = delta != 0u ? label->position_ - delta : 0;
3903 }
3904 label->BindTo(bound);
3905 }
3906
3907
EmitOperand(int reg_or_opcode,const Operand & operand)3908 void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
3909 CHECK_GE(reg_or_opcode, 0);
3910 CHECK_LT(reg_or_opcode, 8);
3911 const int length = operand.length_;
3912 CHECK_GT(length, 0);
3913 // Emit the ModRM byte updated with the given reg value.
3914 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
3915 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
3916 // Emit the rest of the encoded operand.
3917 for (int i = 1; i < length; i++) {
3918 EmitUint8(operand.encoding_[i]);
3919 }
3920 AssemblerFixup* fixup = operand.GetFixup();
3921 if (fixup != nullptr) {
3922 EmitFixup(fixup);
3923 }
3924 }
3925
3926
EmitImmediate(const Immediate & imm,bool is_16_op)3927 void X86Assembler::EmitImmediate(const Immediate& imm, bool is_16_op) {
3928 if (is_16_op) {
3929 EmitUint8(imm.value() & 0xFF);
3930 EmitUint8(imm.value() >> 8);
3931 } else {
3932 EmitInt32(imm.value());
3933 }
3934 }
3935
3936
EmitComplex(int reg_or_opcode,const Operand & operand,const Immediate & immediate,bool is_16_op)3937 void X86Assembler::EmitComplex(int reg_or_opcode,
3938 const Operand& operand,
3939 const Immediate& immediate,
3940 bool is_16_op) {
3941 CHECK_GE(reg_or_opcode, 0);
3942 CHECK_LT(reg_or_opcode, 8);
3943 if (immediate.is_int8()) {
3944 // Use sign-extended 8-bit immediate.
3945 EmitUint8(0x83);
3946 EmitOperand(reg_or_opcode, operand);
3947 EmitUint8(immediate.value() & 0xFF);
3948 } else if (operand.IsRegister(EAX)) {
3949 // Use short form if the destination is eax.
3950 EmitUint8(0x05 + (reg_or_opcode << 3));
3951 EmitImmediate(immediate, is_16_op);
3952 } else {
3953 EmitUint8(0x81);
3954 EmitOperand(reg_or_opcode, operand);
3955 EmitImmediate(immediate, is_16_op);
3956 }
3957 }
3958
3959
EmitLabel(Label * label,int instruction_size)3960 void X86Assembler::EmitLabel(Label* label, int instruction_size) {
3961 if (label->IsBound()) {
3962 int offset = label->Position() - buffer_.Size();
3963 CHECK_LE(offset, 0);
3964 EmitInt32(offset - instruction_size);
3965 } else {
3966 EmitLabelLink(label);
3967 }
3968 }
3969
3970
EmitLabelLink(Label * label)3971 void X86Assembler::EmitLabelLink(Label* label) {
3972 CHECK(!label->IsBound());
3973 int position = buffer_.Size();
3974 EmitInt32(label->position_);
3975 label->LinkTo(position);
3976 }
3977
3978
EmitLabelLink(NearLabel * label)3979 void X86Assembler::EmitLabelLink(NearLabel* label) {
3980 CHECK(!label->IsBound());
3981 int position = buffer_.Size();
3982 if (label->IsLinked()) {
3983 // Save the delta in the byte that we have to play with.
3984 uint32_t delta = position - label->LinkPosition();
3985 CHECK(IsUint<8>(delta));
3986 EmitUint8(delta & 0xFF);
3987 } else {
3988 EmitUint8(0);
3989 }
3990 label->LinkTo(position);
3991 }
3992
3993
EmitGenericShift(int reg_or_opcode,const Operand & operand,const Immediate & imm)3994 void X86Assembler::EmitGenericShift(int reg_or_opcode,
3995 const Operand& operand,
3996 const Immediate& imm) {
3997 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
3998 CHECK(imm.is_int8());
3999 if (imm.value() == 1) {
4000 EmitUint8(0xD1);
4001 EmitOperand(reg_or_opcode, operand);
4002 } else {
4003 EmitUint8(0xC1);
4004 EmitOperand(reg_or_opcode, operand);
4005 EmitUint8(imm.value() & 0xFF);
4006 }
4007 }
4008
4009
EmitGenericShift(int reg_or_opcode,const Operand & operand,Register shifter)4010 void X86Assembler::EmitGenericShift(int reg_or_opcode,
4011 const Operand& operand,
4012 Register shifter) {
4013 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
4014 CHECK_EQ(shifter, ECX);
4015 EmitUint8(0xD3);
4016 EmitOperand(reg_or_opcode, operand);
4017 }
4018
AddConstantArea()4019 void X86Assembler::AddConstantArea() {
4020 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
4021 // Generate the data for the literal area.
4022 for (size_t i = 0, e = area.size(); i < e; i++) {
4023 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
4024 EmitInt32(area[i]);
4025 }
4026 }
4027
AppendInt32(int32_t v)4028 size_t ConstantArea::AppendInt32(int32_t v) {
4029 size_t result = buffer_.size() * elem_size_;
4030 buffer_.push_back(v);
4031 return result;
4032 }
4033
AddInt32(int32_t v)4034 size_t ConstantArea::AddInt32(int32_t v) {
4035 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
4036 if (v == buffer_[i]) {
4037 return i * elem_size_;
4038 }
4039 }
4040
4041 // Didn't match anything.
4042 return AppendInt32(v);
4043 }
4044
AddInt64(int64_t v)4045 size_t ConstantArea::AddInt64(int64_t v) {
4046 int32_t v_low = Low32Bits(v);
4047 int32_t v_high = High32Bits(v);
4048 if (buffer_.size() > 1) {
4049 // Ensure we don't pass the end of the buffer.
4050 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
4051 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
4052 return i * elem_size_;
4053 }
4054 }
4055 }
4056
4057 // Didn't match anything.
4058 size_t result = buffer_.size() * elem_size_;
4059 buffer_.push_back(v_low);
4060 buffer_.push_back(v_high);
4061 return result;
4062 }
4063
AddDouble(double v)4064 size_t ConstantArea::AddDouble(double v) {
4065 // Treat the value as a 64-bit integer value.
4066 return AddInt64(bit_cast<int64_t, double>(v));
4067 }
4068
AddFloat(float v)4069 size_t ConstantArea::AddFloat(float v) {
4070 // Treat the value as a 32-bit integer value.
4071 return AddInt32(bit_cast<int32_t, float>(v));
4072 }
4073
EmitVexPrefixByteZero(bool is_twobyte_form)4074 uint8_t X86Assembler::EmitVexPrefixByteZero(bool is_twobyte_form) {
4075 /**Vex Byte 0,
4076 Bits [7:0] must contain the value 11000101b (0xC5) for 2-byte Vex
4077 Bits [7:0] must contain the value 11000100b (0xC4) for 3-byte Vex */
4078 uint8_t vex_prefix = 0xC0;
4079 if (is_twobyte_form) {
4080 // 2-Byte Vex
4081 vex_prefix |= TWO_BYTE_VEX;
4082 } else {
4083 // 3-Byte Vex
4084 vex_prefix |= THREE_BYTE_VEX;
4085 }
4086 return vex_prefix;
4087 }
4088
EmitVexPrefixByteOne(bool R,bool X,bool B,int SET_VEX_M)4089 uint8_t X86Assembler::EmitVexPrefixByteOne(bool R,
4090 bool X,
4091 bool B,
4092 int SET_VEX_M) {
4093 /**Vex Byte 1, */
4094 uint8_t vex_prefix = VEX_INIT;
4095 /** Bit[7] This bit needs to be set to '1'
4096 otherwise the instruction is LES or LDS */
4097 if (!R) {
4098 // R .
4099 vex_prefix |= SET_VEX_R;
4100 }
4101 /** Bit[6] This bit needs to be set to '1'
4102 otherwise the instruction is LES or LDS */
4103 if (!X) {
4104 // X .
4105 vex_prefix |= SET_VEX_X;
4106 }
4107 /** Bit[5] This bit needs to be set to '1' */
4108 if (!B) {
4109 // B .
4110 vex_prefix |= SET_VEX_B;
4111 }
4112 /** Bits[4:0], */
4113 vex_prefix |= SET_VEX_M;
4114 return vex_prefix;
4115 }
4116
EmitVexPrefixByteOne(bool R,X86ManagedRegister operand,int SET_VEX_L,int SET_VEX_PP)4117 uint8_t X86Assembler::EmitVexPrefixByteOne(bool R,
4118 X86ManagedRegister operand,
4119 int SET_VEX_L,
4120 int SET_VEX_PP) {
4121 /**Vex Byte 1, */
4122 uint8_t vex_prefix = VEX_INIT;
4123 /** Bit[7] This bit needs to be set to '1'
4124 otherwise the instruction is LES or LDS */
4125 if (!R) {
4126 // R .
4127 vex_prefix |= SET_VEX_R;
4128 }
4129 /**Bits[6:3] - 'vvvv' the source or dest register specifier */
4130 if (operand.IsNoRegister()) {
4131 vex_prefix |= 0x78;
4132 } else if (operand.IsXmmRegister()) {
4133 XmmRegister vvvv = operand.AsXmmRegister();
4134 int inverted_reg = 15 - static_cast<int>(vvvv);
4135 uint8_t reg = static_cast<uint8_t>(inverted_reg);
4136 vex_prefix |= ((reg & 0x0F) << 3);
4137 } else if (operand.IsCpuRegister()) {
4138 Register vvvv = operand.AsCpuRegister();
4139 int inverted_reg = 15 - static_cast<int>(vvvv);
4140 uint8_t reg = static_cast<uint8_t>(inverted_reg);
4141 vex_prefix |= ((reg & 0x0F) << 3);
4142 }
4143 /** Bit[2] - "L" If VEX.L = 1 indicates 256-bit vector operation ,
4144 VEX.L = 0 indicates 128 bit vector operation */
4145 vex_prefix |= SET_VEX_L;
4146 /** Bits[1:0] - "pp" */
4147 vex_prefix |= SET_VEX_PP;
4148 return vex_prefix;
4149 }
4150
EmitVexPrefixByteTwo(bool W,X86ManagedRegister operand,int SET_VEX_L,int SET_VEX_PP)4151 uint8_t X86Assembler::EmitVexPrefixByteTwo(bool W,
4152 X86ManagedRegister operand,
4153 int SET_VEX_L,
4154 int SET_VEX_PP) {
4155 /** Vex Byte 2, */
4156 uint8_t vex_prefix = VEX_INIT;
4157 /** Bit[7] This bits needs to be set to '1' with default value.
4158 When using C4H form of VEX prefix, W value is ignored */
4159 if (W) {
4160 vex_prefix |= SET_VEX_W;
4161 }
4162 /** Bits[6:3] - 'vvvv' the source or dest register specifier */
4163 if (operand.IsXmmRegister()) {
4164 XmmRegister vvvv = operand.AsXmmRegister();
4165 int inverted_reg = 15 - static_cast<int>(vvvv);
4166 uint8_t reg = static_cast<uint8_t>(inverted_reg);
4167 vex_prefix |= ((reg & 0x0F) << 3);
4168 } else if (operand.IsCpuRegister()) {
4169 Register vvvv = operand.AsCpuRegister();
4170 int inverted_reg = 15 - static_cast<int>(vvvv);
4171 uint8_t reg = static_cast<uint8_t>(inverted_reg);
4172 vex_prefix |= ((reg & 0x0F) << 3);
4173 }
4174 /** Bit[2] - "L" If VEX.L = 1 indicates 256-bit vector operation ,
4175 VEX.L = 0 indicates 128 bit vector operation */
4176 vex_prefix |= SET_VEX_L;
4177 // Bits[1:0] - "pp"
4178 vex_prefix |= SET_VEX_PP;
4179 return vex_prefix;
4180 }
4181
EmitVexPrefixByteTwo(bool W,int SET_VEX_L,int SET_VEX_PP)4182 uint8_t X86Assembler::EmitVexPrefixByteTwo(bool W,
4183 int SET_VEX_L,
4184 int SET_VEX_PP) {
4185 /**Vex Byte 2, */
4186 uint8_t vex_prefix = VEX_INIT;
4187
4188 /** Bit[7] This bits needs to be set to '1' with default value.
4189 When using C4H form of VEX prefix, W value is ignored */
4190 if (W) {
4191 vex_prefix |= SET_VEX_W;
4192 }
4193 /** Bits[6:3] - 'vvvv' the source or dest register specifier,
4194 if unused set 1111 */
4195 vex_prefix |= (0x0F << 3);
4196
4197 /** Bit[2] - "L" If VEX.L = 1 indicates 256-bit vector operation ,
4198 VEX.L = 0 indicates 128 bit vector operation */
4199 vex_prefix |= SET_VEX_L;
4200
4201 /** Bits[1:0] - "pp" */
4202 if (SET_VEX_PP != SET_VEX_PP_NONE) {
4203 vex_prefix |= SET_VEX_PP;
4204 }
4205 return vex_prefix;
4206 }
4207
4208 } // namespace x86
4209 } // namespace art
4210