1 // Copyright 2021 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef MAGMA_INTEL_GEN_DEFS_H 6 #define MAGMA_INTEL_GEN_DEFS_H 7 8 #include "magma/magma_common_defs.h" 9 10 #define MAGMA_VENDOR_ID_INTEL 0x8086 11 #define MAGMA_VENDOR_VERSION_INTEL 1 12 13 enum MagmaIntelGenQuery { 14 // Returns chip details (simple result) 15 kMagmaIntelGenQuerySubsliceAndEuTotal = MAGMA_QUERY_VENDOR_PARAM_0, 16 // Returns the GTT size (simple result) 17 kMagmaIntelGenQueryGttSize = MAGMA_QUERY_VENDOR_PARAM_0 + 1, 18 // Returns the number of pages of padding used when assigning GPU addresses (simple result) 19 kMagmaIntelGenQueryExtraPageCount = MAGMA_QUERY_VENDOR_PARAM_0 + 2, 20 // Returns magma_intel_gen_timestamp_query (buffer result) 21 kMagmaIntelGenQueryTimestamp = MAGMA_QUERY_VENDOR_PARAM_0 + 3, 22 // Returns magma_intel_gen_topology (buffer result, see struct magma_intel_gen_topology) 23 kMagmaIntelGenQueryTopology = MAGMA_QUERY_VENDOR_PARAM_0 + 4, 24 // Returns boolean (simple result) 25 kMagmaIntelGenQueryHasContextIsolation = MAGMA_QUERY_VENDOR_PARAM_0 + 5, 26 // Returns timestamp frequency (simple result) 27 kMagmaIntelGenQueryTimestampFrequency = MAGMA_QUERY_VENDOR_PARAM_0 + 6, 28 }; 29 30 struct magma_intel_gen_timestamp_query { 31 uint64_t monotonic_raw_timestamp[2]; // start and end of sample interval 32 uint64_t monotonic_timestamp; 33 uint64_t device_timestamp; 34 } __attribute__((packed)); 35 36 enum MagmaIntelGenCommandBufferFlags { 37 kMagmaIntelGenCommandBufferForRender = MAGMA_COMMAND_BUFFER_VENDOR_FLAGS_0, 38 kMagmaIntelGenCommandBufferForVideo = MAGMA_COMMAND_BUFFER_VENDOR_FLAGS_0 << 1, 39 }; 40 41 struct magma_intel_gen_topology { 42 // The number of slices, subslices, and EUs, if none are disabled by masks. 43 uint32_t max_slice_count; 44 uint32_t max_subslice_count; 45 uint32_t max_eu_count; // executable units 46 uint32_t data_byte_count; // the number of data bytes immediately following this structure 47 48 // A variable amount of mask data follows this structure, starting with a slice enable mask, 49 // then for each enabled slice, there follows: a subslice enable mask and an EU enable mask for 50 // each enabled subslice. Each mask is contained within a multiple of 8 bits (little endian). 51 // Example: 2 slices, 3 subslices, 5 EUs 52 // 8 bits (2/2 slices enabled) = 0x3 53 // 8 bits (slice 0, 2/3 subslices enabled) = 0x6 54 // 8 bits (slice 0 subslice 1, 5/5 EUs enabled) = 0x1F 55 // 8 bits (slice 0 subslice 2, 4/5 EUs enabled) = 0x1D 56 // 8 bits (slice 1, 1/3 subslices enabled) = 0x2 57 // 8 bits (slice 1 subslice 1, 3/5 EUs enabled) = 0x1C 58 59 } __attribute__((packed)); 60 61 #endif // MSD_INTEL_GEN_QUERY_H 62