1 /* 2 * Copyright (C) 2016 Freescale Semiconductor, Inc. 3 * Copyright 2017 NXP 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef TZASC_H_ 30 #define TZASC_H_ 31 32 #include <imx-regs.h> 33 #include <reg.h> 34 #include <sys/types.h> 35 36 #define TZ_IRQ 140 37 38 #define TZ_REG(r) (*REG32(r)) 39 40 #define TZ_CONFIG (TZ_BASE_VIRT + 0x000) 41 #define TZ_ACTION (TZ_BASE_VIRT + 0x004) 42 #define TZ_INT_STATUS (TZ_BASE_VIRT + 0x010) 43 #define TZ_INT_CLEAR (TZ_BASE_VIRT + 0x014) 44 #define TZ_FAIL_ADDR_LOW (TZ_BASE_VIRT + 0x020) 45 #define TZ_FAIL_ADDR_HIGH (TZ_BASE_VIRT + 0x024) 46 #define TZ_FAIL_CONTROL (TZ_BASE_VIRT + 0x028) 47 #define TZ_FAIL_ID (TZ_BASE_VIRT + 0x02c) 48 #define TZ_SPECULATION_CTL (TZ_BASE_VIRT + 0x030) 49 #define TZ_SPECULATION_CTL_DISABLE_ALL (0x3) 50 51 #define TZ_REGION_BASE (TZ_BASE_VIRT + 0x100) 52 #define TZ_GET_REGION_ADDR(n) (TZ_REGION_BASE + (n * 0x10)) 53 54 #define TZ_SP_NS_W (0x1 << 0) 55 #define TZ_SP_NS_R (0x1 << 1) 56 #define TZ_SP_S_W (0x1 << 2) 57 #define TZ_SP_S_R (0x1 << 3) 58 59 #define TZ_SP_SHIFT 28 60 #define TZ_ATTR_SP_S_WR_ONLR (0x0 | ((TZ_SP_S_W | TZ_SP_S_R) << TZ_SP_SHIFT)) 61 #define TZ_ATTR_SP_ALL \ 62 (0x0 | ((TZ_SP_S_W | TZ_SP_S_R | TZ_SP_NS_R | TZ_SP_NS_W) << TZ_SP_SHIFT)) 63 64 #define TZ_REGION_SIZE_4M 0x15 65 #define TZ_REGION_SIZE_8M 0x16 66 #define TZ_REGION_SIZE_16M 0x17 67 #define TZ_REGION_SIZE_32M 0x18 68 #define TZ_REGION_SIZE_64M 0x19 69 #define TZ_REGION_SIZE_128M 0x1A 70 #define TZ_REGION_SIZE_256M 0x1B 71 #define TZ_REGION_SIZE_512M 0x1C 72 #define TZ_REGION_SIZE_1G 0x1D 73 #define TZ_REGION_SIZE_2G 0x1E 74 #define TZ_REGION_SIZE_4G 0x1F 75 76 #define TZ_REGION_SIZE_SHIFT 1 77 #define TZ_ATTR_REGION_SIZE(s) (0x0 | ((s) << TZ_REGION_SIZE_SHIFT)) 78 79 #define TZ_ATTR_DISABLE_REGION 0x0 80 81 #define TZ_REGION_ENABLE 0x1 82 #define TZ_REGION_DISABLE 0x0 83 #define TZ_ATTR(sp, sub_dis, size, en) (0x0 | (sp | sub_dis | size | en)) 84 85 typedef struct tzasc_region { 86 paddr_t addr_l; 87 paddr_t addr_h; 88 uint32_t attr; 89 } tzasc_region_t; 90 91 void initial_tzasc(const tzasc_region_t* r, uint num); 92 93 #endif 94