1 /*
2  * Copyright (C) 2014 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ART_COMPILER_OPTIMIZING_REGISTER_ALLOCATOR_LINEAR_SCAN_H_
18 #define ART_COMPILER_OPTIMIZING_REGISTER_ALLOCATOR_LINEAR_SCAN_H_
19 
20 #include "arch/instruction_set.h"
21 #include "base/macros.h"
22 #include "base/scoped_arena_containers.h"
23 #include "register_allocator.h"
24 
25 namespace art HIDDEN {
26 
27 class CodeGenerator;
28 class HBasicBlock;
29 class HGraph;
30 class HInstruction;
31 class HParallelMove;
32 class HPhi;
33 class LiveInterval;
34 class Location;
35 class SsaLivenessAnalysis;
36 
37 /**
38  * An implementation of a linear scan register allocator on an `HGraph` with SSA form.
39  */
40 class RegisterAllocatorLinearScan : public RegisterAllocator {
41  public:
42   RegisterAllocatorLinearScan(ScopedArenaAllocator* allocator,
43                               CodeGenerator* codegen,
44                               const SsaLivenessAnalysis& analysis);
45   ~RegisterAllocatorLinearScan() override;
46 
47   void AllocateRegisters() override;
48 
Validate(bool log_fatal_on_failure)49   bool Validate(bool log_fatal_on_failure) override {
50     current_register_type_ = RegisterType::kCoreRegister;
51     if (!ValidateInternal(log_fatal_on_failure)) {
52       return false;
53     }
54     current_register_type_ = RegisterType::kFpRegister;
55     return ValidateInternal(log_fatal_on_failure);
56   }
57 
GetNumberOfSpillSlots()58   size_t GetNumberOfSpillSlots() const {
59     return int_spill_slots_.size()
60         + long_spill_slots_.size()
61         + float_spill_slots_.size()
62         + double_spill_slots_.size()
63         + catch_phi_spill_slots_;
64   }
65 
66  private:
67   // Main methods of the allocator.
68   void LinearScan();
69   bool TryAllocateFreeReg(LiveInterval* interval);
70   bool AllocateBlockedReg(LiveInterval* interval);
71 
72   // Add `interval` in the given sorted list.
73   static void AddSorted(ScopedArenaVector<LiveInterval*>* array, LiveInterval* interval);
74 
75   // Returns whether `reg` is blocked by the code generator.
76   bool IsBlocked(int reg) const;
77 
78   // Update the interval for the register in `location` to cover [start, end).
79   void BlockRegister(Location location, size_t position, bool will_call);
80 
81   // Allocate a spill slot for the given interval. Should be called in linear
82   // order of interval starting positions.
83   void AllocateSpillSlotFor(LiveInterval* interval);
84 
85   // Allocate a spill slot for the given catch phi. Will allocate the same slot
86   // for phis which share the same vreg. Must be called in reverse linear order
87   // of lifetime positions and ascending vreg numbers for correctness.
88   void AllocateSpillSlotForCatchPhi(HPhi* phi);
89 
90   // Helper methods.
91   void AllocateRegistersInternal();
92   void ProcessInstruction(HInstruction* instruction);
93   bool ValidateInternal(bool log_fatal_on_failure) const;
94   void DumpInterval(std::ostream& stream, LiveInterval* interval) const;
95   void DumpAllIntervals(std::ostream& stream) const;
96   int FindAvailableRegisterPair(size_t* next_use, size_t starting_at) const;
97   int FindAvailableRegister(size_t* next_use, LiveInterval* current) const;
98   bool IsCallerSaveRegister(int reg) const;
99 
100   // If any inputs require specific registers, block those registers
101   // at the position of this instruction.
102   void CheckForFixedInputs(HInstruction* instruction, bool will_call);
103 
104   // If the output of an instruction requires a specific register, split
105   // the interval and assign the register to the first part.
106   void CheckForFixedOutput(HInstruction* instruction, bool will_call);
107 
108   // Add all applicable safepoints to a live interval.
109   // Currently depends on instruction processing order.
110   void AddSafepointsFor(HInstruction* instruction);
111 
112   // Collect all live intervals associated with the temporary locations
113   // needed by an instruction.
114   void CheckForTempLiveIntervals(HInstruction* instruction, bool will_call);
115 
116   // If a safe point is needed, add a synthesized interval to later record
117   // the number of live registers at this point.
118   void CheckForSafepoint(HInstruction* instruction);
119 
120   // Try to remove the SuspendCheck at function entry. Returns true if it was successful.
121   bool TryRemoveSuspendCheckEntry(HInstruction* instruction);
122 
123   // Try splitting an active non-pair or unaligned pair interval at the given `position`.
124   // Returns whether it was successful at finding such an interval.
125   bool TrySplitNonPairOrUnalignedPairIntervalAt(size_t position,
126                                                 size_t first_register_use,
127                                                 size_t* next_use);
128 
129   // List of intervals for core registers that must be processed, ordered by start
130   // position. Last entry is the interval that has the lowest start position.
131   // This list is initially populated before doing the linear scan.
132   ScopedArenaVector<LiveInterval*> unhandled_core_intervals_;
133 
134   // List of intervals for floating-point registers. Same comments as above.
135   ScopedArenaVector<LiveInterval*> unhandled_fp_intervals_;
136 
137   // Currently processed list of unhandled intervals. Either `unhandled_core_intervals_`
138   // or `unhandled_fp_intervals_`.
139   ScopedArenaVector<LiveInterval*>* unhandled_;
140 
141   // List of intervals that have been processed.
142   ScopedArenaVector<LiveInterval*> handled_;
143 
144   // List of intervals that are currently active when processing a new live interval.
145   // That is, they have a live range that spans the start of the new interval.
146   ScopedArenaVector<LiveInterval*> active_;
147 
148   // List of intervals that are currently inactive when processing a new live interval.
149   // That is, they have a lifetime hole that spans the start of the new interval.
150   ScopedArenaVector<LiveInterval*> inactive_;
151 
152   // Fixed intervals for physical registers. Such intervals cover the positions
153   // where an instruction requires a specific register.
154   ScopedArenaVector<LiveInterval*> physical_core_register_intervals_;
155   ScopedArenaVector<LiveInterval*> physical_fp_register_intervals_;
156   LiveInterval* block_registers_for_call_interval_;
157   LiveInterval* block_registers_special_interval_;  // For catch block or irreducible loop header.
158 
159   // Intervals for temporaries. Such intervals cover the positions
160   // where an instruction requires a temporary.
161   ScopedArenaVector<LiveInterval*> temp_intervals_;
162 
163   // The spill slots allocated for live intervals. We ensure spill slots
164   // are typed to avoid (1) doing moves and swaps between two different kinds
165   // of registers, and (2) swapping between a single stack slot and a double
166   // stack slot. This simplifies the parallel move resolver.
167   ScopedArenaVector<size_t> int_spill_slots_;
168   ScopedArenaVector<size_t> long_spill_slots_;
169   ScopedArenaVector<size_t> float_spill_slots_;
170   ScopedArenaVector<size_t> double_spill_slots_;
171 
172   // Spill slots allocated to catch phis. This category is special-cased because
173   // (1) slots are allocated prior to linear scan and in reverse linear order,
174   // (2) equivalent phis need to share slots despite having different types.
175   size_t catch_phi_spill_slots_;
176 
177   // Instructions that need a safepoint.
178   ScopedArenaVector<HInstruction*> safepoints_;
179 
180   // The register type we're currently processing.
181   RegisterType current_register_type_;
182 
183   // Number of registers for the current register kind (core or floating point).
184   size_t number_of_registers_;
185 
186   // Temporary array, allocated ahead of time for simplicity.
187   size_t* registers_array_;
188 
189   // Blocked registers, as decided by the code generator.
190   bool* const blocked_core_registers_;
191   bool* const blocked_fp_registers_;
192 
193   // Slots reserved for out arguments.
194   size_t reserved_out_slots_;
195 
196   ART_FRIEND_TEST(RegisterAllocatorTest, FreeUntil);
197   ART_FRIEND_TEST(RegisterAllocatorTest, SpillInactive);
198 
199   DISALLOW_COPY_AND_ASSIGN(RegisterAllocatorLinearScan);
200 };
201 
202 }  // namespace art
203 
204 #endif  // ART_COMPILER_OPTIMIZING_REGISTER_ALLOCATOR_LINEAR_SCAN_H_
205