Searched refs:Addiw (Results 1 – 5 of 5) sorted by relevance
| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 2625 TEST_F(AssemblerRISCV64Test, Addiw) { in TEST_F() argument
2626 …DriverStr(RepeatRRIb(&Riscv64Assembler::Addiw, /*imm_bits=*/-12, "addiw {reg1}, {reg2}, {imm}"), "… in TEST_F()
2631 DriverStr(RepeatRRIb(&Riscv64Assembler::Addiw, /*imm_bits=*/-12, "addiw {reg1}, {reg2}, {imm}"), in TEST_F()
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| D | assembler_riscv64.cc | 533 void Riscv64Assembler::Addiw(XRegister rd, XRegister rs1, int32_t imm12) { in Addiw() function in art::riscv64::Riscv64Assembler
6161 Addiw(rd, rs, 0); in SextW()
6420 auto addiw = [&](XRegister rd, XRegister rs1, int32_t value) { Addiw(rd, rs1, value); }; in AddConst32()
7641 auto addiw = [&](XRegister rd, XRegister rs, int32_t imm) { Addiw(rd, rs, imm); }; in LoadImmediate()
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| D | assembler_riscv64.h | 312 void Addiw(XRegister rd, XRegister rs1, int32_t imm12);
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 2185 __ Addiw(rd, rs1, instruction->IsSub() ? -imm : imm); in HandleBinaryOp() local
5327 __ Addiw(dst, src, 0); in VisitTypeConversion() local
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| D | intrinsics_riscv64.cc | 3001 __ Addiw(temp1, temp1, c_char_size); in VisitStringCompareTo() local
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