Searched refs:Blt (Results 1 – 5 of 5) sorted by relevance
| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 543 __ Blt(rs, rt, label, is_bare); in EmitBcondForAllConditions() local
2365 TEST_F(AssemblerRISCV64Test, Blt) { in TEST_F() argument
2368 &Riscv64Assembler::Blt, /*imm_bits=*/-12, /*shift=*/1, "blt {reg1}, {reg2}, {imm}\n"), in TEST_F()
8823 __ Blt(reg, reg, &label); in TEST_F() local
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| D | assembler_riscv64.cc | 144 void Riscv64Assembler::Blt(XRegister rs1, XRegister rs2, int32_t offset) { in Blt() function in art::riscv64::Riscv64Assembler
6236 Blt(rt, Zero, offset); in Bltz()
6240 Blt(Zero, rt, offset); in Bgtz()
6244 Blt(rt, rs, offset); in Bgt()
6461 Blt(rs, Zero, label, is_bare); in Bltz()
6484 void Riscv64Assembler::Blt(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Blt() function in art::riscv64::Riscv64Assembler
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| D | assembler_riscv64.h | 268 void Blt(XRegister rs1, XRegister rs2, int32_t offset);
1814 void Blt(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare = false);
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| /art/compiler/optimizing/ |
| D | intrinsics_riscv64.cc | 1485 __ Blt(rs1, temp, label); in EmitBlt32() local
1487 __ Blt(rs1, rs2.AsRegister<XRegister>(), label); in EmitBlt32() local
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| D | code_generator_riscv64.cc | 1722 __ Blt(left, right_reg, label); in GenerateIntLongCompareAndBranch() local
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