Searched refs:FA3 (Results 1 – 7 of 7) sorted by relevance
| /art/runtime/arch/riscv64/ |
| D | registers_riscv64.h | 93 FA3 = 13, // F13, argument 3 enumerator
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| D | callee_save_frame_riscv64.h | 62 (1 << art::riscv64::FA3) | (1 << art::riscv64::FA4) | (1 << art::riscv64::FA5) |
81 (1 << art::riscv64::FA3) | (1 << art::riscv64::FA4) | (1 << art::riscv64::FA5) |
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| D | context_riscv64.cc | 116 fprs_[FA3] = nullptr; in SmashCallerSaves()
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| /art/compiler/utils/riscv64/ |
| D | jni_macro_assembler_riscv64_test.cc | 457 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA3), kXlenInBytes), in TEST_F()
477 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA3), 2 * kVRegSize), in TEST_F()
535 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA3), kFloatSize), in TEST_F()
555 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA3), kVRegSize), in TEST_F()
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| D | assembler_riscv64_test.cc | 275 FA3, in GetFPRegisters()
313 FA3, in GetFPRegistersShort()
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| /art/compiler/jni/quick/riscv64/ |
| D | calling_convention_riscv64.cc | 41 FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.h | 37 static constexpr FRegister kParameterFpuRegisters[] = {FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7};
46 FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
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