Searched refs:FLoadd (Results 1 – 5 of 5) sorted by relevance
| /art/compiler/utils/riscv64/ |
| D | jni_macro_assembler_riscv64.cc | 107 __ FLoadd(enum_cast<FRegister>(reg), SP, offset); in RemoveFrame() local
232 __ FLoadd(dest.AsFRegister(), base.AsXRegister(), offs.Int32Value()); in Load() local
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| D | assembler_riscv64_test.cc | 1019 __ FLoadd(freg, wide_literal); in TestLoadLiteral() local
9105 TEST_F(AssemblerRISCV64Test, FLoadd) { in TEST_F() argument
9107 TestFPLoadStoreArbitraryOffset("FLoadd", "fld", &Riscv64Assembler::FLoadd); in TEST_F()
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| D | assembler_riscv64.h | 1791 void FLoadd(FRegister rd, XRegister rs1, int32_t offset);
1829 void FLoadd(FRegister rd, Literal* literal);
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| D | assembler_riscv64.cc | 6359 void Riscv64Assembler::FLoadd(FRegister rd, XRegister rs1, int32_t offset) { in FLoadd() function in art::riscv64::Riscv64Assembler
6540 void Riscv64Assembler::FLoadd(FRegister rd, Literal* literal) { in FLoadd() function in art::riscv64::Riscv64Assembler
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 920 __ FLoadd(out.AsFpuRegister<FRegister>(), rs1, offset); in Load() local
6085 __ FLoadd(reg, SP, offset); in GenerateFrameExit() local
6143 __ FLoadd(destination.AsFpuRegister<FRegister>(), SP, source.GetStackIndex()); in MoveLocation() local
6339 __ FLoadd(FRegister(reg_id), SP, stack_index); in RestoreFloatingPointRegister() local
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