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Searched refs:Operand (Results 1 – 15 of 15) sorted by relevance

/art/compiler/optimizing/
Dcommon_arm64.h169 inline vixl::aarch64::Operand OperandFrom(Location location, DataType::Type type) { in OperandFrom()
171 return vixl::aarch64::Operand(RegisterFrom(location, type)); in OperandFrom()
173 return vixl::aarch64::Operand(Int64FromLocation(location)); in OperandFrom()
177 inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) { in InputOperandAt()
227 inline vixl::aarch64::Operand OperandFromMemOperand( in OperandFromMemOperand()
230 return vixl::aarch64::Operand(mem_op.GetOffset()); in OperandFromMemOperand()
234 return vixl::aarch64::Operand(mem_op.GetRegisterOffset(), in OperandFromMemOperand()
238 return vixl::aarch64::Operand(mem_op.GetRegisterOffset(), in OperandFromMemOperand()
Dcommon_arm.h191 inline vixl::aarch32::Operand OperandFrom(Location location, DataType::Type type) { in OperandFrom()
193 return vixl::aarch32::Operand(RegisterFrom(location, type)); in OperandFrom()
195 return vixl::aarch32::Operand(Int32ConstantFrom(location)); in OperandFrom()
199 inline vixl::aarch32::Operand InputOperandAt(HInstruction* instr, int input_index) { in InputOperandAt()
Dcode_generator_arm_vixl.cc213 __ Add(base, sp, Operand::From(stack_offset)); in SaveContiguousSRegisterList()
261 __ Add(base, sp, Operand::From(stack_offset)); in RestoreContiguousSRegisterList()
1125 const Operand& second, in GenerateDataProcInstruction()
1128 const Operand in = kind == HInstruction::kAnd in GenerateDataProcInstruction()
1129 ? Operand(0) in GenerateDataProcInstruction()
1130 : Operand(first); in GenerateDataProcInstruction()
1160 const Operand& second_lo, in GenerateDataProc()
1161 const Operand& second_hi, in GenerateDataProc()
1180 static Operand GetShifterOperand(vixl32::Register rm, ShiftType shift, uint32_t shift_imm) { in GetShifterOperand()
1181 return shift_imm == 0 ? Operand(rm) : Operand(rm, shift, shift_imm); in GetShifterOperand()
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Dcode_generator_arm64.cc681 __ Add(index_reg, index_reg, Operand(offset_)); in EmitNativeCode()
1238 __ Cmp(value, Operand(instrumentation::Instrumentation::kFastTraceListeners)); in GenerateMethodEntryExitHook()
1268 __ Orr(tmp, tmp, Operand(enum_cast<int32_t>(TraceAction::kTraceMethodExit))); in GenerateMethodEntryExitHook()
1971 Operand op = OperandFromMemOperand(dst); in StoreRelease()
2379 Operand rhs = InputOperandAt(instr, 1); in HandleBinaryOp()
2458 Operand rhs = InputOperandAt(instr, 1); in HandleShift()
2562 Operand right_operand(0); in VisitDataProcWithShifterOp()
2566 right_operand = Operand(right_reg, helpers::ExtendFromOpKind(op_kind)); in VisitDataProcWithShifterOp()
2568 right_operand = Operand(right_reg, in VisitDataProcWithShifterOp()
2617 Operand(InputOperandAt(instruction, 1))); in VisitIntermediateAddress()
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Dintrinsics_arm64.cc446 __ Bic(dst, dst, Operand(temp, LSL, high_bit - clz_high_bit)); // Clear dst if src was 0. in GenHighestOneBit()
1390 __ Add(tmp_ptr, base_.X(), Operand(offset_)); in EmitNativeCode()
1500 __ Add(tmp_ptr, base.X(), Operand(offset)); in GenUnsafeCas()
1740 __ Add(tmp_ptr, base.X(), Operand(offset)); in GenUnsafeGetAndUpdate()
1912 __ Eor(temp2, temp2, Operand(temp3)); in VisitStringCompareTo()
1915 __ Ands(temp3.W(), temp3.W(), Operand(1)); in VisitStringCompareTo()
1967 __ Cmp(temp0, Operand(temp1.W(), LSR, (mirror::kUseStringCompression) ? 3 : 4)); in VisitStringCompareTo()
1973 __ Bic(temp1, temp1, Operand(temp3.X(), LSL, 3u)); in VisitStringCompareTo()
1982 __ Sub(out, temp1.W(), Operand(temp2.W(), UXTB)); in VisitStringCompareTo()
1986 __ Sub(out, temp4.W(), Operand(temp2.W(), UXTH)); in VisitStringCompareTo()
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Dintrinsics_arm_vixl.cc739 __ Cmp(temp0, Operand(temp1, vixl32::LSR, (mirror::kUseStringCompression ? 3 : 4))); in GenerateStringCompareToLoop()
748 __ Bic(temp1, temp1, Operand(temp3, vixl32::LSR, 31 - 3)); // &= ~(uncompressed ? 0xfu : 0x7u) in GenerateStringCompareToLoop()
950 __ Cmp(temp, Operand(mirror::String::GetFlaggedCount(const_string_length, is_compressed))); in VisitStringEquals()
1022 __ Add(temp1, temp1, Operand::From(sizeof(uint32_t))); in VisitStringEquals()
1210 __ Add(dest, base, Operand(RegisterFrom(pos), LSL, DataType::SizeShift(type))); in GenArrayAddress()
1545 __ Add(src, src, Operand(rb_tmp, vixl32::LSR, 32)); in VisitSystemArrayCopy()
2012 Operand mov_src(0); in GenHighestOneBit()
2015 mov_src = Operand(temp); in GenHighestOneBit()
2078 Operand mov_src(0); in GenLowestOneBit()
2081 mov_src = Operand(temp); in GenLowestOneBit()
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Dcode_generator_vector_arm_vixl.cc920 __ Add(*scratch, base, Operand(RegisterFrom(index), ShiftType::LSL, shift)); in VecAddress()
947 __ Add(*scratch, *scratch, Operand(RegisterFrom(index), ShiftType::LSL, shift)); in VecAddressUnaligned()
Dcode_generator_vector_arm64_neon.cc1643 masm->Add(new_base, base, Operand(spill_offset + core_spill_size)); in SaveRestoreLiveRegistersHelperNeonImpl()
/art/compiler/utils/x86/
Dassembler_x86.cc417 EmitOperand(0, Operand(dst)); in setb()
614 EmitOperand(dst, Operand(src)); in movd()
623 EmitOperand(src, Operand(dst)); in movd()
1678 EmitOperand(dst, Operand(src)); in cvtsi2ss()
1687 EmitOperand(dst, Operand(src)); in cvtsi2sd()
3020 EmitComplex(7, Operand(reg), imm); in cmpl()
3027 EmitOperand(reg0, Operand(reg1)); in cmpl()
3098 EmitOperand(0, Operand(reg)); in testl()
3124 EmitOperand(dst, Operand(src)); in andl()
3137 EmitComplex(4, Operand(dst), imm); in andl()
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Dassembler_x86.h54 class Operand : public ValueObject {
97 inline bool operator==(const Operand &op) const {
106 Operand() : length_(0), disp_(0), fixup_(nullptr) { } in Operand() function
152 explicit Operand(Register reg) : disp_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand() function
165 class Address : public Operand {
267 return static_cast<const Operand&>(*this) == static_cast<const Operand&>(addr);
1040 void EmitOperand(int rm, const Operand& operand);
1043 int rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
1048 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm);
1049 void EmitGenericShift(int rm, const Operand& operand, Register shifter);
/art/compiler/utils/x86_64/
Dassembler_x86_64.h61 class Operand : public ValueObject {
140 inline bool operator==(const Operand &op) const {
149 Operand() : rex_(0), length_(0), fixup_(nullptr) { } in Operand() function
196 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand() function
209 class Address : public Operand {
345 return static_cast<const Operand&>(*this) == static_cast<const Operand&>(addr);
1124 void EmitOperand(uint8_t rm, const Operand& operand);
1127 uint8_t rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
1144 void EmitOptionalRex32(const Operand& operand);
1145 void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
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Dassembler_x86_64.cc750 EmitOperand(dst.LowBits(), Operand(src)); in movd()
759 EmitOperand(src.LowBits(), Operand(dst)); in movd()
2360 EmitOperand(dst.LowBits(), Operand(src)); in cvtsi2ss()
2395 EmitOperand(dst.LowBits(), Operand(src)); in cvtsi2sd()
4089 EmitComplex(7, Operand(reg), imm); in cmpl()
4097 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpl()
4129 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpq()
4137 EmitComplex(7, Operand(reg), imm); in cmpq()
4209 EmitOperand(0, Operand(reg)); in testl()
4254 EmitOperand(dst.LowBits(), Operand(src)); in andl()
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/art/compiler/utils/arm/
Dassembler_arm_vixl.h103 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
128 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
151 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add()
Dassembler_arm_vixl.cc379 ___ Add(base, sp, Operand::From(stack_offset)); in StoreRegisterList()
399 ___ Add(base, sp, Operand::From(stack_offset)); in LoadRegisterList()
/art/compiler/utils/arm64/
Dassembler_arm64.cc167 ___ Neg(reg, Operand(reg)); in PoisonHeapReference()
173 ___ Neg(reg, Operand(reg)); in UnpoisonHeapReference()