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Searched refs:Out (Results 1 – 25 of 27) sorted by relevance

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/art/compiler/optimizing/
Dcode_generator_vector_x86.cc64 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReplicateScalar()
106 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
111 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
161 __ movd(locations->Out().AsRegister<Register>(), src); in VisitVecExtractScalar()
166 __ movd(locations->Out().AsRegisterPairLow<Register>(), src); in VisitVecExtractScalar()
168 __ movd(locations->Out().AsRegisterPairHigh<Register>(), tmp); in VisitVecExtractScalar()
175 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
218 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReduce()
264 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecCnv()
282 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecNeg()
[all …]
Dcode_generator_vector_x86_64.cc59 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReplicateScalar()
97 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
102 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitVecReplicateScalar()
148 __ movd(locations->Out().AsRegister<CpuRegister>(), src, /*64-bit*/ false); in VisitVecExtractScalar()
152 __ movd(locations->Out().AsRegister<CpuRegister>(), src, /*64-bit*/ true); in VisitVecExtractScalar()
158 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
201 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReduce()
247 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecCnv()
265 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecNeg()
316 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecAbs()
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Dcode_generator_vector_arm_vixl.cc56 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReplicateScalar()
137 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce()
174 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNeg()
203 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAbs()
230 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNot()
278 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAdd()
308 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSaturationAdd()
340 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecHalvingAdd()
380 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSub()
410 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSaturationSub()
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Dcode_generator_vector_arm64_neon.cc111 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecReplicateScalar()
210 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
252 VRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce()
292 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecCnv()
310 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecNeg()
351 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecAbs()
390 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecNot()
442 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecAdd()
484 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecSaturationAdd()
516 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecHalvingAdd()
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Dcode_generator_vector_arm64_sve.cc112 const ZRegister dst = ZRegisterFrom(locations->Out()); in VisitVecReplicateScalar()
204 DCHECK(locations->InAt(0).Equals(locations->Out())); // no code required in VisitVecExtractScalar()
247 const VRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce()
285 const ZRegister dst = ZRegisterFrom(locations->Out()); in VisitVecCnv()
305 const ZRegister dst = ZRegisterFrom(locations->Out()); in VisitVecNeg()
343 const ZRegister dst = ZRegisterFrom(locations->Out()); in VisitVecAbs()
379 const ZRegister dst = ZRegisterFrom(locations->Out()); in VisitVecNot()
439 const ZRegister dst = ZRegisterFrom(locations->Out()); in VisitVecAdd()
498 const ZRegister dst = ZRegisterFrom(locations->Out()); in VisitVecSub()
547 const ZRegister dst = ZRegisterFrom(locations->Out()); in VisitVecMul()
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Dssa_liveness_analysis.cc55 if (locations != nullptr && locations->Out().IsValid()) { in NumberInstructions()
73 if (locations != nullptr && locations->Out().IsValid()) { in NumberInstructions()
113 bool has_out_location = input->GetLocations()->Out().IsValid(); in RecursivelyProcessInputs()
221 DCHECK(!current->GetLocations()->Out().IsValid()); in ComputeLiveRanges()
456 Location out = locations->Out(); in FindHintAtDefinition()
524 return defined_by->GetLocations()->Out(); in ToLocation()
Dcommon_arm.h91 return SRegisterFrom(instr->GetLocations()->Out()); in OutputSRegister()
97 return DRegisterFrom(instr->GetLocations()->Out()); in OutputDRegister()
137 return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputRegister()
Dintrinsics_x86.cc173 Location output = locations->Out(); in MoveFPToInt()
188 Location output = locations->Out(); in MoveIntToFP()
254 Register out = locations->Out().AsRegister<Register>(); in GenReverseBytes()
288 Location output = locations->Out(); in VisitLongReverseBytes()
322 XmmRegister out = locations->Out().AsFpuRegister<XmmRegister>(); in VisitMathSqrt()
342 XmmRegister out = locations->Out().AsFpuRegister<XmmRegister>(); in GenSSE41FPToFPIntrinsic()
397 Register out = locations->Out().AsRegister<Register>(); in VisitMathRoundFloat()
501 Location out_loc = locations->Out(); in GenLowestOneBit()
1040 Register esi = locations->Out().AsRegister<Register>(); in VisitStringEquals()
1177 Register out = locations->Out().AsRegister<Register>(); in GenerateStringIndexOf()
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Dintrinsics_arm64.cc190 Location output = locations->Out(); in MoveFPToInt()
197 Location output = locations->Out(); in MoveIntToFP()
290 Location out = locations->Out(); in GenReverseBytes()
324 Location out = locations->Out(); in GenNumberOfLeadingZeros()
351 Location out = locations->Out(); in GenNumberOfTrailingZeros()
379 Location out = locations->Out(); in GenReverse()
408 Register dst = RegisterFrom(instr->GetLocations()->Out(), type); in GenBitCount()
439 Register dst = RegisterFrom(invoke->GetLocations()->Out(), type); in GenHighestOneBit()
472 Register dst = RegisterFrom(invoke->GetLocations()->Out(), type); in GenLowestOneBit()
509 __ Fsqrt(DRegisterFrom(locations->Out()), DRegisterFrom(locations->InAt(0))); in VisitMathSqrt()
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Dintrinsics_x86_64.cc160 Location output = locations->Out(); in MoveFPToInt()
166 Location output = locations->Out(); in MoveIntToFP()
210 codegen_->GetInstructionCodegen()->Bswap(invoke->GetLocations()->Out(), DataType::Type::kInt32); in VisitIntegerReverseBytes()
218 codegen_->GetInstructionCodegen()->Bswap(invoke->GetLocations()->Out(), DataType::Type::kInt64); in VisitLongReverseBytes()
226 codegen_->GetInstructionCodegen()->Bswap(invoke->GetLocations()->Out(), DataType::Type::kInt16); in VisitShortReverseBytes()
235 CpuRegister output = locations->Out().AsRegister<CpuRegister>(); in GenIsInfinite()
304 XmmRegister out = locations->Out().AsFpuRegister<XmmRegister>(); in VisitMathSqrt()
324 XmmRegister out = locations->Out().AsFpuRegister<XmmRegister>(); in GenSSE41FPToFPIntrinsic()
377 CpuRegister out = locations->Out().AsRegister<CpuRegister>(); in VisitMathRoundFloat()
418 CpuRegister out = locations->Out().AsRegister<CpuRegister>(); in VisitMathRoundDouble()
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Dcode_generator_riscv64.cc416 Location out = locations->Out(); in EmitNativeCode()
624 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
646 riscv64_codegen->MoveLocation(locations->Out(), ret_loc, ret_type); in EmitNativeCode()
763 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
778 locations->Out(), calling_convention.GetReturnLocation(type), type); in EmitNativeCode()
1435 XRegister out = locations->Out().AsRegister<XRegister>(); in DivRemOneOrMinusOne()
1465 XRegister out = locations->Out().AsRegister<XRegister>(); in DivRemByPowerOfTwo()
1510 XRegister out = locations->Out().AsRegister<XRegister>(); in GenerateDivRemWithAnyConstant()
1540 XRegister out = locations->Out().AsRegister<XRegister>(); in GenerateDivRemIntegral()
1576 XRegister rd = locations->Out().AsRegister<XRegister>(); in GenerateIntLongCondition()
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Dcode_generator_x86_64.cc279 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
293 x86_64_codegen->Move(locations->Out(), Location::RegisterLocation(RAX)); in EmitNativeCode()
315 Location out = locations->Out(); in EmitNativeCode()
375 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
389 x86_64_codegen->Move(locations->Out(), Location::RegisterLocation(RAX)); in EmitNativeCode()
410 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
446 x86_64_codegen->Move(locations->Out(), Location::RegisterLocation(RAX)); in EmitNativeCode()
2427 __ movl(flag->GetLocations()->Out().AsRegister<CpuRegister>(), in VisitShouldDeoptimizeFlag()
2478 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitSelect()
2523 codegen_->MoveLocation(locations->Out(), locations->InAt(1), select->GetType()); in VisitSelect()
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Dintrinsics_riscv64.cc177 __ FMvXD(locations->Out().AsRegister<XRegister>(), locations->InAt(0).AsFpuRegister<FRegister>()); in VisitDoubleDoubleToRawLongBits()
187 __ FMvDX(locations->Out().AsFpuRegister<FRegister>(), locations->InAt(0).AsRegister<XRegister>()); in VisitDoubleLongBitsToDouble()
197 __ FMvXW(locations->Out().AsRegister<XRegister>(), locations->InAt(0).AsFpuRegister<FRegister>()); in VisitFloatFloatToRawIntBits()
207 __ FMvWX(locations->Out().AsFpuRegister<FRegister>(), locations->InAt(0).AsRegister<XRegister>()); in VisitFloatIntBitsToFloat()
217 XRegister out = locations->Out().AsRegister<XRegister>(); in VisitDoubleIsInfinite()
230 XRegister out = locations->Out().AsRegister<XRegister>(); in VisitFloatIsInfinite()
246 emit_op(locations->Out().AsRegister<XRegister>(), locations->InAt(0).AsRegister<XRegister>()); in EmitMemoryPeek()
388 GenerateReverseBytes(codegen, locations->Out(), locations->InAt(0).AsRegister<XRegister>(), type); in GenerateReverseBytes()
396 XRegister out = locations->Out().AsRegister<XRegister>(); in GenerateReverse()
479 emit_op(locations->Out().AsRegister<XRegister>(), locations->InAt(0).AsRegister<XRegister>()); in EmitIntegralUnOp()
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Dcode_generator_x86.cc273 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
284 x86_codegen->Move32(locations->Out(), Location::RegisterLocation(EAX)); in EmitNativeCode()
306 Location out = locations->Out(); in EmitNativeCode()
367 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
409 x86_codegen->Move32(locations->Out(), Location::RegisterLocation(EAX)); in EmitNativeCode()
2315 __ movl(flag->GetLocations()->Out().AsRegister<Register>(), in VisitShouldDeoptimizeFlag()
2366 DCHECK(locations->InAt(0).Equals(locations->Out())); in VisitSelect()
2429 codegen_->MoveLocation(locations->Out(), locations->InAt(1), select->GetType()); in VisitSelect()
2503 Register reg = locations->Out().AsRegister<Register>(); in HandleCondition()
3005 Location out = locations->Out(); in VisitNeg()
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Dcommon_arm64.h83 return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputRegister()
127 return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputFPRegister()
Dintrinsics_utils.h79 Location out = invoke_->GetLocations()->Out(); in EmitNativeCode()
Dintrinsics_arm_vixl.cc180 Location output = locations->Out(); in MoveFPToInt()
190 Location output = locations->Out(); in MoveIntToFP()
262 vixl32::Register out = RegisterFrom(locations->Out()); in GenNumberOfLeadingZeros()
306 vixl32::Register out = RegisterFrom(locations->Out()); in GenNumberOfTrailingZeros()
447 vixl32::Register lo = LowRegisterFrom(invoke->GetLocations()->Out()); in VisitMemoryPeekLongNative()
448 vixl32::Register hi = HighRegisterFrom(invoke->GetLocations()->Out()); in VisitMemoryPeekLongNative()
1861 vixl32::Register out_reg_lo = LowRegisterFrom(locations->Out()); in VisitLongReverse()
1862 vixl32::Register out_reg_hi = HighRegisterFrom(locations->Out()); in VisitLongReverse()
1914 GenerateReverseBytes(assembler, DataType::Type::kInt32, locations->InAt(0), locations->Out()); in VisitIntegerReverseBytes()
1924 GenerateReverseBytes(assembler, DataType::Type::kInt64, locations->InAt(0), locations->Out()); in VisitLongReverseBytes()
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Dcode_generator.cc114 if (locations->Out().IsUnallocated() in CheckTypeConsistency()
115 && (locations->Out().GetPolicy() == Location::kSameAsFirstInput)) { in CheckTypeConsistency()
120 DCHECK(CheckType(instruction->GetType(), locations->Out())) in CheckTypeConsistency()
122 << " " << locations->Out(); in CheckTypeConsistency()
750 MoveLocation(locations->Out(), calling_convention.GetReturnLocation(field_type), field_type); in GenerateUnresolvedFieldAccess()
1493 Location location = current_phi->GetLocations()->Out(); in EmitVRegInfoOnlyCatchPhis()
Dcode_generator_arm_vixl.cc501 Location out = locations->Out(); in EmitNativeCode()
539 arm_codegen->Move32(locations->Out(), LocationFrom(r0)); in EmitNativeCode()
563 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
575 arm_codegen->Move32(locations->Out(), LocationFrom(r0)); in EmitNativeCode()
595 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
620 arm_codegen->Move32(locations->Out(), LocationFrom(r0)); in EmitNativeCode()
1194 const Location out = locations->Out(); in GenerateLongDataProc()
3128 const Location out = locations->Out(); in VisitSelect()
3867 Location out = locations->Out(); in VisitNeg()
4052 Location out = locations->Out(); in VisitTypeConversion()
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Dregister_allocation_resolver.cc62 Location location = locations->Out(); in Resolve()
466 location_source = defined_by->GetLocations()->Out(); in ConnectSplitSiblings()
Dregister_allocator_test.cc727 ASSERT_EQ(first_sub->GetLocations()->Out().GetPolicy(), Location::kSameAsFirstInput); in TEST_F()
728 ASSERT_EQ(second_sub->GetLocations()->Out().GetPolicy(), Location::kSameAsFirstInput); in TEST_F()
Dcode_generator_arm64.cc280 Location out = locations->Out(); in EmitNativeCode()
343 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
355 arm64_codegen->MoveLocation(locations->Out(), calling_convention.GetReturnLocation(type), type); in EmitNativeCode()
444 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg())); in EmitNativeCode()
468 arm64_codegen->MoveLocation(locations->Out(), ret_loc, ret_type); in EmitNativeCode()
2258 Location out = locations->Out(); in HandleFieldGet()
2751 Location out = locations->Out(); in VisitArrayGet()
3314 Register res = RegisterFrom(locations->Out(), instruction->GetType()); in HandleCondition()
4184 Location out_loc = locations->Out(); in VisitInstanceOf()
5588 Location out_loc = cls->GetLocations()->Out(); in VisitLoadClass()
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Dssa_liveness_analysis.h594 DCHECK(defined_by_->GetLocations()->Out().IsValid()); in FirstUseAfter()
955 Location location = locations->Out(); in DefinitionRequiresRegister()
Dlocations.h604 Location Out() const { return output_; } in Out() function
/art/tools/dexfuzz/
DREADME85 |Iterations|VerifyFail|MutateFail|Timed Out |Successful|Divergence|
96 Timed Out - mutated files that timed out for one or more backends.

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