Searched refs:RelOffset (Results 1 – 12 of 12) sorted by relevance
| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 119 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
126 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
127 cfi_.RelOffset(DWARFReg(dst1), offset + size); in SpillRegisters()
133 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
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| /art/compiler/debug/dwarf/ |
| D | dwarf_test.cc | 111 opcodes.RelOffset(Reg(0), 0); // push R0 in TEST_F()
113 opcodes.RelOffset(Reg(1), 4); // push R1 in TEST_F()
158 opcodes.RelOffset(Reg::X86_64Core(i), 0); in TEST_F()
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| /art/libelffile/dwarf/ |
| D | debug_frame_opcode_writer.h | 73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset() function
94 RelOffset(Reg(reg_base.num() + i), offset); in RelOffsetForMany()
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| /art/compiler/utils/riscv64/ |
| D | jni_macro_assembler_riscv64.cc | 78 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(RA), offset); in BuildFrame()
83 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(enum_cast<XRegister>(reg)), offset); in BuildFrame()
88 __ cfi().RelOffset(dwarf::Reg::Riscv64Fp(enum_cast<FRegister>(reg)), offset); in BuildFrame()
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 65 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); in BuildFrame()
84 cfi().RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset); in BuildFrame()
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 66 cfi().RelOffset(DWARFReg(spill), 0); in BuildFrame()
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 112 cfi().RelOffset(DWARFReg(lr), kFramePointerSize); in BuildFrame()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 6033 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(reg), offset); in GenerateFrameEntry()
6043 __ cfi().RelOffset(dwarf::Reg::Riscv64Fp(reg), offset); in GenerateFrameEntry()
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| D | code_generator_x86_64.cc | 1887 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
1900 __ cfi().RelOffset(DWARFReg(kFpuCalleeSaves[i]), offset); in GenerateFrameEntry()
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| D | code_generator_arm64.cc | 1436 GetAssembler()->cfi().RelOffset(DWARFReg(lowest_spill), core_spills_offset); in GenerateFrameEntry()
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| D | code_generator_x86.cc | 1445 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
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| D | code_generator_arm_vixl.cc | 2449 GetAssembler()->cfi().RelOffset(DWARFReg(sreg), /*offset=*/ fp_spills_offset); in GenerateFrameEntry()
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