Searched refs:S5 (Results 1 – 12 of 12) sorted by relevance
| /art/runtime/arch/arm/ |
| D | registers_arm.h | 65 S5 = 5, enumerator
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| D | context_arm.cc | 87 fprs_[S5] = nullptr; in SmashCallerSaves()
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| D | callee_save_frame_arm.h | 49 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
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| /art/runtime/arch/riscv64/ |
| D | registers_riscv64.h | 53 S5 = 21, // X21, callee-saved 5 enumerator
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| D | callee_save_frame_riscv64.h | 38 (1 << art::riscv64::S4) | (1 << art::riscv64::S5) | (1 << art::riscv64::S6) |
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 161 S5 = 5, enumerator
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| /art/compiler/jni/quick/riscv64/ |
| D | calling_convention_riscv64.cc | 52 Riscv64ManagedRegister::FromXRegister(S5),
109 Riscv64ManagedRegister::FromXRegister(S5),
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 46 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 56 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 233 reg = Arm64ManagedRegister::FromSRegister(S5); in TEST()
241 EXPECT_EQ(S5, reg.AsSRegister()); in TEST()
243 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S5))); in TEST()
712 EXPECT_TRUE(vixl::aarch64::s5.Is(Arm64Assembler::reg_s(S5))); in TEST()
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 185 secondary_register_names_.emplace(S5, "s5"); in SetUpHelpers()
231 S5, in GetRegisters()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 62 S0, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, RA
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