Searched refs:S7 (Results 1 – 12 of 12) sorted by relevance
| /art/runtime/arch/arm/ |
| D | registers_arm.h | 67 S7 = 7, enumerator
|
| D | context_arm.cc | 89 fprs_[S7] = nullptr; in SmashCallerSaves()
|
| D | callee_save_frame_arm.h | 49 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
|
| /art/runtime/arch/riscv64/ |
| D | registers_riscv64.h | 55 S7 = 23, // X23, callee-saved 7 enumerator
|
| D | callee_save_frame_riscv64.h | 39 (1 << art::riscv64::S7) | (1 << art::riscv64::S8) | (1 << art::riscv64::S9) |
|
| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 163 S7 = 7, enumerator
|
| /art/compiler/jni/quick/riscv64/ |
| D | calling_convention_riscv64.cc | 54 Riscv64ManagedRegister::FromXRegister(S7),
111 Riscv64ManagedRegister::FromXRegister(S7),
|
| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 46 S0, S1, S2, S3, S4, S5, S6, S7
|
| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 56 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
|
| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 245 reg = Arm64ManagedRegister::FromSRegister(S7); in TEST()
253 EXPECT_EQ(S7, reg.AsSRegister()); in TEST()
255 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S7))); in TEST()
714 EXPECT_TRUE(vixl::aarch64::s7.Is(Arm64Assembler::reg_s(S7))); in TEST()
|
| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 187 secondary_register_names_.emplace(S7, "s7"); in SetUpHelpers()
233 S7, in GetRegisters()
|
| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 62 S0, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, RA
|