Searched refs:Sh (Results 1 – 5 of 5) sorted by relevance
| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 2463 TEST_F(AssemblerRISCV64Test, Sh) { in TEST_F() argument
2464 DriverStr(RepeatRRIb(&Riscv64Assembler::Sh, /*imm_bits=*/-12, "sh {reg1}, {imm}({reg2})"), "Sh"); in TEST_F()
2469 DriverStr(RepeatRRIb(&Riscv64Assembler::Sh, /*imm_bits=*/-12, "sh {reg1}, {imm}({reg2})"), in TEST_F()
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| D | assembler_riscv64.h | 284 void Sh(XRegister rs2, XRegister rs1, int32_t offset);
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| D | assembler_riscv64.cc | 258 void Riscv64Assembler::Sh(XRegister rs2, XRegister rs1, int32_t offset) { in Sh() function in art::riscv64::Riscv64Assembler
6344 StoreToOffset<&Riscv64Assembler::Sh>(rs2, rs1, offset); in Storeh()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 281 __ Sh(counter, base_, imm12_); in EmitNativeCode() local
5899 __ Sh(counter, method, ArtMethod::HotnessCountOffset().Int32Value()); in MaybeIncrementHotness() local
5922 __ Sh(counter, tmp, imm12); in MaybeIncrementHotness() local
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| D | intrinsics_riscv64.cc | 340 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sh(rs2, rs1, 0); }); in VisitMemoryPokeShortNative() local
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