Searched refs:Subw (Results 1 – 5 of 5) sorted by relevance
| /art/compiler/optimizing/ |
| D | intrinsics_riscv64.cc | 871 __ Subw(out, out, other); in VisitReferenceRefersTo() local
2897 __ Subw(out, temp0, temp1); in VisitStringCompareTo() local
2969 __ Subw(out, temp4, temp2); in VisitStringCompareTo() local
5121 __ Subw(number_of_chars, source_end_index, source_begin_index); in VisitStringGetCharsNoCheck() local
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| D | code_generator_riscv64.cc | 1445 __ Subw(out, Zero, dividend); in DivRemOneOrMinusOne() local
2190 __ Subw(rd, rs1, rs2); in HandleBinaryOp() local
2727 __ Subw(out, out, tmp); in VisitAbs() local
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 2659 TEST_F(AssemblerRISCV64Test, Subw) { in TEST_F() argument
2660 DriverStr(RepeatRRR(&Riscv64Assembler::Subw, "subw {reg1}, {reg2}, {reg3}"), "Subw"); in TEST_F()
2665 DriverStr(RepeatRRR(&Riscv64Assembler::Subw, "subw {reg1}, {reg2}, {reg3}"), "Subw_WithoutC"); in TEST_F()
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| D | assembler_riscv64.h | 319 void Subw(XRegister rd, XRegister rs1, XRegister rs2);
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| D | assembler_riscv64.cc | 582 void Riscv64Assembler::Subw(XRegister rd, XRegister rs1, XRegister rs2) { in Subw() function in art::riscv64::Riscv64Assembler
6125 void Riscv64Assembler::NegW(XRegister rd, XRegister rs) { Subw(rd, Zero, rs); } in NegW()
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