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Searched refs:T5 (Results 1 – 5 of 5) sorted by relevance

/art/runtime/arch/riscv64/
Dregisters_riscv64.h63 T5 = 30, // X30, temporary 5 enumerator
72 TMP2 = T5, // Reserved for special uses, such as assembler macro instructions.
Dcontext_riscv64.cc89 gprs_[T5] = nullptr; in SmashCallerSaves()
Dcallee_save_frame_riscv64.h52 (1 << art::riscv64::T3) | (1 << art::riscv64::T4) | (1 << art::riscv64::T5) |
/art/compiler/utils/riscv64/
Dassembler_riscv64_test.cc194 secondary_register_names_.emplace(T5, "t5"); in SetUpHelpers()
240 T5, in GetRegisters()
/art/compiler/optimizing/
Dcode_generator_riscv64.cc6938 XRegister ic_reg = T5; in MaybeGenerateInlineCacheCheck()